138 lines
5.1 KiB
C
138 lines
5.1 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "clocks.h"
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#include "hpl_gclk_config.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "py/runtime.h"
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bool gclk_enabled(uint8_t gclk) {
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common_hal_mcu_disable_interrupts();
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// Explicitly do a byte write so the peripheral knows we're just wanting to read the channel
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// rather than write to it.
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*((uint8_t*) &GCLK->GENCTRL.reg) = gclk;
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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bool enabled = GCLK->GENCTRL.bit.GENEN;
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common_hal_mcu_enable_interrupts();
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return enabled;
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}
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void disable_gclk(uint8_t gclk) {
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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}
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void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk) | GCLK_CLKCTRL_CLKEN;
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}
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void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk);
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}
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void enable_clock_generator(uint8_t gclk, uint32_t source, uint16_t divisor) {
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uint32_t divsel = 0;
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if (gclk == 2 && divisor > 31) {
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divsel = GCLK_GENCTRL_DIVSEL;
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for (int i = 15; i > 4; i++) {
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if (divisor & (1 << i)) {
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divisor = i - 1;
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break;
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}
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}
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}
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk) | GCLK_GENDIV_DIV(divisor);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk) | GCLK_GENCTRL_SRC(source) | divsel | GCLK_GENCTRL_OE | GCLK_GENCTRL_GENEN;
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while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
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}
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void disable_clock_generator(uint8_t gclk) {
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
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while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
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}
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static void init_clock_source_osc8m(void) {
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// Preserve CALIB and FRANGE
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SYSCTRL->OSC8M.bit.ONDEMAND = 0;
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SYSCTRL->OSC8M.bit.PRESC = 3;
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SYSCTRL->OSC8M.bit.ENABLE = 1;
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while (!SYSCTRL->PCLKSR.bit.OSC8MRDY) {}
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}
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static void init_clock_source_osc32k(void) {
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uint32_t calib = (*((uint32_t *)FUSES_OSC32K_CAL_ADDR) & FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
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SYSCTRL->OSC32K.reg = SYSCTRL_OSC32K_CALIB(calib) |
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SYSCTRL_OSC32K_EN32K |
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SYSCTRL_OSC32K_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.OSC32KRDY) {}
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}
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static void init_clock_source_xosc32k(void) {
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_EN32K |
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SYSCTRL_XOSC32K_XTALEN |
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SYSCTRL_XOSC32K_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.XOSC32KRDY) {}
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}
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static void init_clock_source_dfll48m(void) {
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(1) |
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SYSCTRL_DFLLMUL_FSTEP(1) |
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SYSCTRL_DFLLMUL_MUL(48000);
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uint32_t coarse = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR) & FUSES_DFLL48M_COARSE_CAL_Msk) >> FUSES_DFLL48M_COARSE_CAL_Pos;
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if (coarse == 0x3f)
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coarse = 0x1f;
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SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) |
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SYSCTRL_DFLLVAL_FINE(512);
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_CCDIS |
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SYSCTRL_DFLLCTRL_USBCRM |
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SYSCTRL_DFLLCTRL_MODE |
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SYSCTRL_DFLLCTRL_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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}
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void clock_init(void)
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{
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init_clock_source_osc8m();
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if (board_has_crystal())
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init_clock_source_xosc32k();
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else
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init_clock_source_osc32k();
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enable_clock_generator(0, GCLK_GENCTRL_SRC_DFLL48M_Val, 1);
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enable_clock_generator(1, GCLK_GENCTRL_SRC_DFLL48M_Val, 150);
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init_clock_source_dfll48m();
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if (board_has_crystal())
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enable_clock_generator(2, GCLK_GENCTRL_SRC_XOSC32K_Val, 32);
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else
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enable_clock_generator(2, GCLK_GENCTRL_SRC_OSC32K_Val, 32);
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}
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