84 lines
3.8 KiB
C
84 lines
3.8 KiB
C
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/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "stm32h7xx_hal.h"
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void stm32_peripherals_clocks_init(void) {
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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/* The PWR block is always enabled on the H7 series- there is no clock
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enable. For now, use the default VOS3 scale mode (lowest) and limit clock
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frequencies to avoid potential current draw problems from bus
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power when using the max clock speeds throughout the chip. */
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/* Enable HSE Oscillator and activate PLL1 with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV;
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RCC_OscInitStruct.PLL.PLLN = 336;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \
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RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \
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RCC_CLOCKTYPE_D3PCLK1);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
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/* Unlike on the STM32F4 family, it appears the maximum APB frequencies are
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device-dependent- 120 MHz for this board according to Figure 2 of
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the datasheet. Dividing by half will be safe for now. */
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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/* 4 wait states required for 168MHz and VOS3. */
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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/* Like on F4, on H7, USB's actual peripheral clock and bus clock are
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separate. However, the main system PLL (PLL1) doesn't have a direct
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connection to the USB peripheral clock to generate 48 MHz, so we do this
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dance. This will connect PLL1's Q output to the USB peripheral clock. */
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RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
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RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
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RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
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HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
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}
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