61698eb5d8
Make changes in asf4_conf even though I think in these cases the "peripherals" submodule is running the show. Arduino clocks the DAC at 12MHz but uses the CCTRL setting for clocking < 1.2MHz (100kSPS). A fresh clock (6) is allocated for the new 12MHz clock. This matches the Arduino value, though not the GCLK index. Modify other settings to more closely resemble Arduino. In AudioOut, actually clock the waveform data from the timer we set up for this purpose. This gives good waveforms when setting AnalogOut full-scale in a loop, but the rise/fall of waveforms that come from AudioOut are still erratic. Weirdly, if AudioOut limits its range even slightly (e.g., to 1000..64000) then the erratic Note that this will require https://github.com/adafruit/samd-peripherals/pull/26 to be accepted for the submodule update here to work.
474 lines
16 KiB
C
474 lines
16 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "extmod/vfs_fat.h"
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#include "py/gc.h"
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#include "py/mperrno.h"
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#include "py/runtime.h"
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#include "common-hal/audioio/AudioOut.h"
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#include "shared-bindings/audioio/AudioOut.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "shared-bindings/microcontroller/Pin.h"
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#include "supervisor/shared/translate.h"
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#include "atmel_start_pins.h"
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#include "hal/include/hal_gpio.h"
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#include "hpl/gclk/hpl_gclk_base.h"
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#include "peripheral_clk_config.h"
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#ifdef SAMD21
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#include "hpl/pm/hpl_pm_base.h"
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#endif
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#include "audio_dma.h"
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#include "timer_handler.h"
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#include "samd/dma.h"
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#include "samd/events.h"
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#include "samd/pins.h"
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#include "samd/timers.h"
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#ifdef SAMD21
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static void ramp_value(uint16_t start, uint16_t end) {
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start = DAC->DATA.reg;
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int32_t diff = (int32_t) end - start;
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int32_t step = 49;
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int32_t steps = diff / step;
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if (diff < 0) {
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steps = -steps;
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step = -step;
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}
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for (int32_t i = 0; i < steps; i++) {
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uint32_t value = start + step * i;
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DAC->DATA.reg = value;
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DAC->DATABUF.reg = value;
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common_hal_mcu_delay_us(50);
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RUN_BACKGROUND_TASKS;
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}
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}
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#endif
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#ifdef SAMD51
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static void ramp_value(uint16_t start, uint16_t end) {
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int32_t diff = (int32_t) end - start;
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int32_t step = 49;
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int32_t steps = diff / step;
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if (diff < 0) {
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steps = -steps;
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step = -step;
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}
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for (int32_t i = 0; i < steps; i++) {
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uint16_t value = start + step * i;
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DAC->DATA[0].reg = value;
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DAC->DATABUF[0].reg = value;
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DAC->DATA[1].reg = value;
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DAC->DATABUF[1].reg = value;
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common_hal_mcu_delay_us(50);
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RUN_BACKGROUND_TASKS;
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}
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}
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#endif
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void audioout_reset(void) {
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#if defined(SAMD21) && !defined(PIN_PA02)
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return;
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#endif
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#ifdef SAMD21
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while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {}
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#endif
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#ifdef SAMD51
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while (DAC->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) {}
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#endif
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if (DAC->CTRLA.bit.ENABLE) {
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ramp_value(0x8000, 0);
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}
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DAC->CTRLA.reg |= DAC_CTRLA_SWRST;
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// TODO(tannewt): Turn off the DAC clocks to save power.
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}
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void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
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const mcu_pin_obj_t* left_channel, const mcu_pin_obj_t* right_channel, uint16_t quiescent_value) {
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#ifdef SAMD51
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bool dac_clock_enabled = hri_mclk_get_APBDMASK_DAC_bit(MCLK);
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#endif
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#ifdef SAMD21
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bool dac_clock_enabled = PM->APBCMASK.bit.DAC_;
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#endif
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// Only support exclusive use of the DAC.
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if (dac_clock_enabled && DAC->CTRLA.bit.ENABLE == 1) {
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mp_raise_RuntimeError(translate("DAC already in use"));
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}
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#ifdef SAMD21
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if (right_channel != NULL) {
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mp_raise_ValueError(translate("Right channel unsupported"));
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}
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if (left_channel != &pin_PA02) {
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mp_raise_ValueError(translate("Invalid pin"));
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}
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assert_pin_free(left_channel);
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claim_pin(left_channel);
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#endif
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#ifdef SAMD51
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self->right_channel = NULL;
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if (left_channel != &pin_PA02 && left_channel != &pin_PA05) {
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mp_raise_ValueError(translate("Invalid pin for left channel"));
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}
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assert_pin_free(left_channel);
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if (right_channel != NULL && right_channel != &pin_PA02 && right_channel != &pin_PA05) {
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mp_raise_ValueError(translate("Invalid pin for right channel"));
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}
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if (right_channel == left_channel) {
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mp_raise_ValueError(translate("Cannot output both channels on the same pin"));
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}
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claim_pin(left_channel);
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if (right_channel != NULL) {
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claim_pin(right_channel);
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self->right_channel = right_channel;
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audio_dma_init(&self->right_dma);
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}
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#endif
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self->left_channel = left_channel;
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audio_dma_init(&self->left_dma);
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#ifdef SAMD51
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hri_mclk_set_APBDMASK_DAC_bit(MCLK);
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#endif
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#ifdef SAMD21
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_pm_enable_bus_clock(PM_BUS_APBC, DAC);
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#endif
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// SAMD51: This clock should be <= 12 MHz, per datasheet section 47.6.3.
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// SAMD21: This clock is 48mhz despite the datasheet saying it must only be <= 350kHz, per
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// datasheet table 37-6. It's incorrect because the max output rate is 350ksps and is only
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// achieved when the GCLK is more than 8mhz.
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_gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC);
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DAC->CTRLA.bit.SWRST = 1;
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while (DAC->CTRLA.bit.SWRST == 1) {}
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// Make sure there are no outstanding access errors. (Reading DATA can cause this.)
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#ifdef SAMD51
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PAC->INTFLAGD.reg = PAC_INTFLAGD_DAC;
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#endif
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bool channel0_enabled = true;
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#ifdef SAMD51
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channel0_enabled = self->left_channel == &pin_PA02 || self->right_channel == &pin_PA02;
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bool channel1_enabled = self->left_channel == &pin_PA05 || self->right_channel == &pin_PA05;
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#endif
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if (channel0_enabled) {
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#ifdef SAMD21
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DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI;
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// We disable the voltage pump because we always run at 3.3v.
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DAC->CTRLB.reg = DAC_CTRLB_REFSEL_AVCC |
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DAC_CTRLB_LEFTADJ |
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DAC_CTRLB_EOEN |
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DAC_CTRLB_VPD;
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#endif
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#ifdef SAMD51
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DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI0;
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DAC->DACCTRL[0].reg = DAC_DACCTRL_CCTRL_CC100K |
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DAC_DACCTRL_ENABLE |
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DAC_DACCTRL_LEFTADJ;
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DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU;
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#endif
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}
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#ifdef SAMD51
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if (channel1_enabled) {
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DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI1;
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DAC->DACCTRL[1].reg = DAC_DACCTRL_CCTRL_CC100K |
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DAC_DACCTRL_ENABLE |
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DAC_DACCTRL_LEFTADJ;
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DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU;
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}
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#endif
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// Re-enable the DAC
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DAC->CTRLA.bit.ENABLE = 1;
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#ifdef SAMD21
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while (DAC->STATUS.bit.SYNCBUSY == 1) {}
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#endif
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#ifdef SAMD51
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while (DAC->SYNCBUSY.bit.ENABLE == 1) {}
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while (channel0_enabled && DAC->STATUS.bit.READY0 == 0) {}
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while (channel1_enabled && DAC->STATUS.bit.READY1 == 0) {}
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#endif
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// Use a timer to coordinate when DAC conversions occur.
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Tc *t = NULL;
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uint8_t tc_index = TC_INST_NUM;
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for (uint8_t i = TC_INST_NUM; i > 0; i--) {
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if (tc_insts[i - 1]->COUNT16.CTRLA.bit.ENABLE == 0) {
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t = tc_insts[i - 1];
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tc_index = i - 1;
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break;
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}
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}
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if (t == NULL) {
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common_hal_audioio_audioout_deinit(self);
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mp_raise_RuntimeError(translate("All timers in use"));
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return;
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}
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self->tc_index = tc_index;
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// Use the 48mhz clocks on both the SAMD21 and 51 because we will be going much slower.
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uint8_t tc_gclk = 0;
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#ifdef SAMD51
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tc_gclk = 1;
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#endif
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set_timer_handler(true, tc_index, TC_HANDLER_NO_INTERRUPT);
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turn_on_clocks(true, tc_index, tc_gclk);
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// Don't bother setting the period. We set it before you playback anything.
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tc_set_enable(t, false);
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tc_reset(t);
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#ifdef SAMD51
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t->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;
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#endif
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#ifdef SAMD21
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t->COUNT16.CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_MFRQ_Val;
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#endif
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t->COUNT16.EVCTRL.reg = TC_EVCTRL_OVFEO;
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tc_set_enable(t, true);
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t->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
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// Connect the timer overflow event, which happens at the target frequency,
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// to the DAC conversion trigger(s).
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#ifdef SAMD21
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#define FIRST_TC_GEN_ID EVSYS_ID_GEN_TC3_OVF
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#endif
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#ifdef SAMD51
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#define FIRST_TC_GEN_ID EVSYS_ID_GEN_TC0_OVF
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#endif
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uint8_t tc_gen_id = FIRST_TC_GEN_ID + 3 * tc_index;
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turn_on_event_system();
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// Find a free event channel. We start at the highest channels because we only need and async
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// path.
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uint8_t channel = find_async_event_channel();
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if (channel >= EVSYS_CHANNELS) {
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mp_raise_RuntimeError(translate("All event channels in use"));
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}
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#ifdef SAMD51
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connect_event_user_to_channel(EVSYS_ID_USER_DAC_START_1, channel);
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if (right_channel != NULL) {
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gpio_set_pin_function(self->right_channel->number, GPIO_PIN_FUNCTION_B);
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}
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#define EVSYS_ID_USER_DAC_START EVSYS_ID_USER_DAC_START_0
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#endif
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connect_event_user_to_channel(EVSYS_ID_USER_DAC_START, channel);
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gpio_set_pin_function(self->left_channel->number, GPIO_PIN_FUNCTION_B);
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init_async_event_channel(channel, tc_gen_id);
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self->tc_to_dac_event_channel = channel;
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// Ramp the DAC up.
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self->quiescent_value = quiescent_value;
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ramp_value(0, quiescent_value);
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// Leave the DMA setup to playback.
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}
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bool common_hal_audioio_audioout_deinited(audioio_audioout_obj_t* self) {
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return self->left_channel == mp_const_none;
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}
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void common_hal_audioio_audioout_deinit(audioio_audioout_obj_t* self) {
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if (common_hal_audioio_audioout_deinited(self)) {
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return;
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}
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if (common_hal_audioio_audioout_get_playing(self)) {
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common_hal_audioio_audioout_stop(self);
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}
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// Ramp the DAC down.
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ramp_value(self->quiescent_value, 0);
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DAC->CTRLA.bit.ENABLE = 0;
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#ifdef SAMD21
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while (DAC->STATUS.bit.SYNCBUSY == 1) {}
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#endif
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#ifdef SAMD51
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while (DAC->SYNCBUSY.bit.ENABLE == 1) {}
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#endif
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disable_event_channel(self->tc_to_dac_event_channel);
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tc_set_enable(tc_insts[self->tc_index], false);
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reset_pin_number(self->left_channel->number);
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self->left_channel = mp_const_none;
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#ifdef SAMD51
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reset_pin_number(self->right_channel->number);
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self->right_channel = mp_const_none;
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#endif
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}
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static void set_timer_frequency(Tc* timer, uint32_t frequency) {
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uint32_t system_clock = 48000000;
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uint32_t new_top;
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uint8_t new_divisor;
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for (new_divisor = 0; new_divisor < 8; new_divisor++) {
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new_top = (system_clock / prescaler[new_divisor] / frequency) - 1;
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if (new_top < (1u << 16)) {
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break;
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}
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}
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uint8_t old_divisor = timer->COUNT16.CTRLA.bit.PRESCALER;
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if (new_divisor != old_divisor) {
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tc_set_enable(timer, false);
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timer->COUNT16.CTRLA.bit.PRESCALER = new_divisor;
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tc_set_enable(timer, true);
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}
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tc_wait_for_sync(timer);
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timer->COUNT16.CC[0].reg = new_top;
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tc_wait_for_sync(timer);
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}
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void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self,
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mp_obj_t sample, bool loop) {
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if (common_hal_audioio_audioout_get_playing(self)) {
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common_hal_audioio_audioout_stop(self);
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}
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audio_dma_result result = AUDIO_DMA_OK;
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uint32_t sample_rate = audiosample_sample_rate(sample);
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#ifdef SAMD21
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uint32_t max_sample_rate = 350000;
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#endif
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#ifdef SAMD51
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uint32_t max_sample_rate = 1000000;
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#endif
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if (sample_rate > max_sample_rate) {
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mp_raise_ValueError_varg(translate("Sample rate too high. It must be less than %d"), max_sample_rate);
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}
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#ifdef SAMD21
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result = audio_dma_setup_playback(&self->left_dma, sample, loop, true, 0,
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false /* output unsigned */,
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(uint32_t) &DAC->DATABUF.reg,
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DAC_DMAC_ID_EMPTY);
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#endif
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#ifdef SAMD51
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uint32_t left_channel_reg = (uint32_t) &DAC->DATABUF[0].reg;
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uint8_t tc_trig_id = TC0_DMAC_ID_OVF + 3 * self->tc_index;
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uint8_t left_channel_trigger = tc_trig_id;
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uint32_t right_channel_reg = 0;
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uint8_t right_channel_trigger = tc_trig_id;
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if (self->left_channel == &pin_PA05) {
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left_channel_reg = (uint32_t) &DAC->DATABUF[1].reg;
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} else if (self->right_channel == &pin_PA05) {
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right_channel_reg = (uint32_t) &DAC->DATABUF[1].reg;
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}
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if (self->right_channel == &pin_PA02) {
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right_channel_reg = (uint32_t) &DAC->DATABUF[0].reg;
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}
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result = audio_dma_setup_playback(&self->left_dma, sample, loop, true, 0,
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false /* output unsigned */,
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left_channel_reg,
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left_channel_trigger);
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if (right_channel_reg != 0 && result == AUDIO_DMA_OK) {
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result = audio_dma_setup_playback(&self->right_dma, sample, loop, true, 1,
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false /* output unsigned */,
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right_channel_reg,
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right_channel_trigger);
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}
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#endif
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if (result != AUDIO_DMA_OK) {
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audio_dma_stop(&self->left_dma);
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#ifdef SAMD51
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audio_dma_stop(&self->right_dma);
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#endif
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if (result == AUDIO_DMA_DMA_BUSY) {
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mp_raise_RuntimeError(translate("No DMA channel found"));
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} else if (result == AUDIO_DMA_MEMORY_ERROR) {
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mp_raise_RuntimeError(translate("Unable to allocate buffers for signed conversion"));
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}
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}
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Tc* timer = tc_insts[self->tc_index];
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set_timer_frequency(timer, audiosample_sample_rate(sample));
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timer->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
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while (timer->COUNT16.STATUS.bit.STOP == 1) {}
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self->playing = true;
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}
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void common_hal_audioio_audioout_pause(audioio_audioout_obj_t* self) {
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audio_dma_pause(&self->left_dma);
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#ifdef SAMD51
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audio_dma_pause(&self->right_dma);
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#endif
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}
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void common_hal_audioio_audioout_resume(audioio_audioout_obj_t* self) {
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// Clear any overrun/underrun errors
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#ifdef SAMD21
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DAC->INTFLAG.reg = DAC_INTFLAG_UNDERRUN;
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#endif
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#ifdef SAMD51
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DAC->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_UNDERRUN1;
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#endif
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audio_dma_resume(&self->left_dma);
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#ifdef SAMD51
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audio_dma_resume(&self->right_dma);
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#endif
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}
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bool common_hal_audioio_audioout_get_paused(audioio_audioout_obj_t* self) {
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return audio_dma_get_paused(&self->left_dma);
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}
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void common_hal_audioio_audioout_stop(audioio_audioout_obj_t* self) {
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Tc* timer = tc_insts[self->tc_index];
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timer->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
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audio_dma_stop(&self->left_dma);
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#ifdef SAMD51
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audio_dma_stop(&self->right_dma);
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#endif
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// Ramp the DAC to default. The start is ignored when the current value can be readback.
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// Otherwise, we just set it immediately.
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ramp_value(self->quiescent_value, self->quiescent_value);
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}
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bool common_hal_audioio_audioout_get_playing(audioio_audioout_obj_t* self) {
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bool now_playing = audio_dma_get_playing(&self->left_dma);
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if (self->playing && !now_playing) {
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common_hal_audioio_audioout_stop(self);
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}
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return now_playing;
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}
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