349 lines
12 KiB
C
349 lines
12 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Dan Halbert for Adafruit Industries
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* Copyright (c) 2018 Artur Pacholec
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <string.h>
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#include "shared-bindings/busio/SPI.h"
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#include "py/mperrno.h"
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#include "py/runtime.h"
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#include "nrfx_spim.h"
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#include "nrf_gpio.h"
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#ifndef NRFX_SPIM3_ENABLED
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#define NRFX_SPIM3_ENABLED (0)
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#endif
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#ifndef NRFX_SPIM2_ENABLED
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#define NRFX_SPIM2_ENABLED (0)
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#endif
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#ifndef NRFX_SPIM1_ENABLED
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#define NRFX_SPIM1_ENABLED (0)
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#endif
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#ifndef NRFX_SPIM0_ENABLED
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#define NRFX_SPIM0_ENABLED (0)
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#endif
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// These are in order from highest available frequency to lowest (32MHz first, then 8MHz).
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STATIC const spim_peripheral_t spim_peripherals[] = {
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#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
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// SPIM3 exists only on nRF52840 and supports 32MHz max. All other SPIM's are only 8MHz max.
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// Allocate SPIM3 first.
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{ .spim = NRFX_SPIM_INSTANCE(3),
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.max_frequency = 32000000,
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.max_xfer_size = MIN(SPIM3_BUFFER_RAM_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1)},
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#endif
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#if NRFX_CHECK(NRFX_SPIM2_ENABLED)
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// SPIM2 is not shared with a TWIM, so allocate before the shared ones.
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{ .spim = NRFX_SPIM_INSTANCE(2),
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.max_frequency = 8000000,
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.max_xfer_size = (1UL << SPIM2_EASYDMA_MAXCNT_SIZE) - 1},
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#endif
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#if NRFX_CHECK(NRFX_SPIM1_ENABLED)
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// SPIM1 and TWIM1 share an address.
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{ .spim = NRFX_SPIM_INSTANCE(1),
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.max_frequency = 8000000,
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.max_xfer_size = (1UL << SPIM1_EASYDMA_MAXCNT_SIZE) - 1},
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#endif
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#if NRFX_CHECK(NRFX_SPIM0_ENABLED)
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// SPIM0 and TWIM0 share an address.
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{ .spim = NRFX_SPIM_INSTANCE(0),
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.max_frequency = 8000000,
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.max_xfer_size = (1UL << SPIM0_EASYDMA_MAXCNT_SIZE) - 1},
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#endif
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};
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STATIC bool never_reset[MP_ARRAY_SIZE(spim_peripherals)];
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// Separate RAM area for SPIM3 transmit buffer to avoid SPIM3 hardware errata.
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// https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF52840_Rev2%2FERR%2FnRF52840%2FRev2%2Flatest%2Fanomaly_840_198.html
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STATIC uint8_t *spim3_transmit_buffer = (uint8_t *)SPIM3_BUFFER_RAM_START_ADDR;
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void spi_reset(void) {
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for (size_t i = 0; i < MP_ARRAY_SIZE(spim_peripherals); i++) {
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if (never_reset[i]) {
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continue;
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}
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nrfx_spim_uninit(&spim_peripherals[i].spim);
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}
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}
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void common_hal_busio_spi_never_reset(busio_spi_obj_t *self) {
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for (size_t i = 0; i < MP_ARRAY_SIZE(spim_peripherals); i++) {
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if (self->spim_peripheral == &spim_peripherals[i]) {
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never_reset[i] = true;
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never_reset_pin_number(self->clock_pin_number);
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never_reset_pin_number(self->MOSI_pin_number);
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never_reset_pin_number(self->MISO_pin_number);
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break;
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}
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}
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}
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// Convert frequency to clock-speed-dependent value. Choose the next lower baudrate if in between
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// available baudrates.
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static nrf_spim_frequency_t baudrate_to_spim_frequency(const uint32_t baudrate) {
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static const struct {
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const uint32_t boundary;
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nrf_spim_frequency_t spim_frequency;
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} baudrate_map[] = {
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#ifdef SPIM_FREQUENCY_FREQUENCY_M32
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{ 32000000, NRF_SPIM_FREQ_32M },
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#endif
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#ifdef SPIM_FREQUENCY_FREQUENCY_M16
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{ 16000000, NRF_SPIM_FREQ_16M },
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#endif
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{ 8000000, NRF_SPIM_FREQ_8M },
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{ 4000000, NRF_SPIM_FREQ_4M },
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{ 2000000, NRF_SPIM_FREQ_2M },
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{ 1000000, NRF_SPIM_FREQ_1M },
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{ 500000, NRF_SPIM_FREQ_500K },
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{ 250000, NRF_SPIM_FREQ_250K },
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{ 0, NRF_SPIM_FREQ_125K },
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};
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size_t i = 0;
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uint32_t boundary;
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do {
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boundary = baudrate_map[i].boundary;
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if (baudrate >= boundary) {
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return baudrate_map[i].spim_frequency;
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}
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i++;
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} while (boundary != 0);
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// Should not get here.
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return 0;
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}
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void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, const mcu_pin_obj_t *miso) {
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// Find a free instance, with most desirable (highest freq and not shared) allocated first.
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self->spim_peripheral = NULL;
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for (size_t i = 0; i < MP_ARRAY_SIZE(spim_peripherals); i++) {
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if ((spim_peripherals[i].spim.p_reg->ENABLE & SPIM_ENABLE_ENABLE_Msk) == 0) {
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self->spim_peripheral = &spim_peripherals[i];
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break;
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}
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}
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if (self->spim_peripheral == NULL) {
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mp_raise_ValueError(translate("All SPI peripherals are in use"));
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}
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nrfx_spim_config_t config = NRFX_SPIM_DEFAULT_CONFIG(NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED,
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NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED);
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config.frequency = baudrate_to_spim_frequency(self->spim_peripheral->max_frequency);
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config.sck_pin = clock->number;
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self->clock_pin_number = clock->number;
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claim_pin(clock);
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if (mosi != NULL) {
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config.mosi_pin = mosi->number;
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self->MOSI_pin_number = mosi->number;
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claim_pin(mosi);
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} else {
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self->MOSI_pin_number = NO_PIN;
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}
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if (miso != NULL) {
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config.miso_pin = miso->number;
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self->MISO_pin_number = miso->number;
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claim_pin(miso);
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} else {
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self->MISO_pin_number = NO_PIN;
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}
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nrfx_err_t err = nrfx_spim_init(&self->spim_peripheral->spim, &config, NULL, NULL);
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if (err != NRFX_SUCCESS) {
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common_hal_busio_spi_deinit(self);
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mp_raise_OSError(MP_EIO);
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}
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}
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bool common_hal_busio_spi_deinited(busio_spi_obj_t *self) {
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return self->clock_pin_number == NO_PIN;
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}
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void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
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if (common_hal_busio_spi_deinited(self)) {
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return;
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}
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nrfx_spim_uninit(&self->spim_peripheral->spim);
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reset_pin_number(self->clock_pin_number);
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reset_pin_number(self->MOSI_pin_number);
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reset_pin_number(self->MISO_pin_number);
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}
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bool common_hal_busio_spi_configure(busio_spi_obj_t *self, uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
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// nrf52 does not support 16 bit
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if (bits != 8) {
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return false;
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}
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// Set desired frequency, rounding down, and don't go above available frequency for this SPIM.
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nrf_spim_frequency_set(self->spim_peripheral->spim.p_reg,
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baudrate_to_spim_frequency(MIN(baudrate, self->spim_peripheral->max_frequency)));
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nrf_spim_mode_t mode = NRF_SPIM_MODE_0;
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if (polarity) {
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mode = (phase) ? NRF_SPIM_MODE_3 : NRF_SPIM_MODE_2;
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} else {
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mode = (phase) ? NRF_SPIM_MODE_1 : NRF_SPIM_MODE_0;
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}
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nrf_spim_configure(self->spim_peripheral->spim.p_reg, mode, NRF_SPIM_BIT_ORDER_MSB_FIRST);
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return true;
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}
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bool common_hal_busio_spi_try_lock(busio_spi_obj_t *self) {
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bool grabbed_lock = false;
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// NRFX_CRITICAL_SECTION_ENTER();
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if (!self->has_lock) {
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grabbed_lock = true;
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self->has_lock = true;
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}
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// NRFX_CRITICAL_SECTION_EXIT();
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return grabbed_lock;
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}
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bool common_hal_busio_spi_has_lock(busio_spi_obj_t *self) {
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return self->has_lock;
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}
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void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
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self->has_lock = false;
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}
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bool common_hal_busio_spi_write(busio_spi_obj_t *self, const uint8_t *data, size_t len) {
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const bool is_spim3 = self->spim_peripheral->spim.p_reg == NRF_SPIM3;
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uint8_t *next_chunk = (uint8_t *)data;
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while (len > 0) {
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size_t chunk_size = MIN(len, self->spim_peripheral->max_xfer_size);
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uint8_t *chunk = next_chunk;
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if (is_spim3) {
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// If SPIM3, copy into unused RAM block, and do DMA from there.
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memcpy(spim3_transmit_buffer, chunk, chunk_size);
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chunk = spim3_transmit_buffer;
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}
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const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_TX(chunk, chunk_size);
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if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS) {
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return false;
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}
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next_chunk += chunk_size;
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len -= chunk_size;
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}
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return true;
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}
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bool common_hal_busio_spi_read(busio_spi_obj_t *self, uint8_t *data, size_t len, uint8_t write_value) {
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uint8_t *next_chunk = data;
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while (len > 0) {
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size_t chunk_size = MIN(len, self->spim_peripheral->max_xfer_size);
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const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_XFER_RX(next_chunk, chunk_size);
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if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS) {
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return false;
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}
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next_chunk += chunk_size;
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len -= chunk_size;
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}
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return true;
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}
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bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_out, uint8_t *data_in, size_t len) {
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const bool is_spim3 = self->spim_peripheral->spim.p_reg == NRF_SPIM3;
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const uint8_t *next_chunk_out = data_out;
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uint8_t *next_chunk_in = data_in;
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while (len > 0) {
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const uint8_t *chunk_out = next_chunk_out;
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size_t chunk_size = MIN(len, self->spim_peripheral->max_xfer_size);
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if (is_spim3) {
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// If SPIM3, copy into unused RAM block, and do DMA from there.
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memcpy(spim3_transmit_buffer, chunk_out, chunk_size);
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chunk_out = spim3_transmit_buffer;
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}
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const nrfx_spim_xfer_desc_t xfer =
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NRFX_SPIM_SINGLE_XFER(next_chunk_out, chunk_size,
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next_chunk_in, chunk_size);
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if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS) {
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return false;
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}
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next_chunk_out += chunk_size;
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next_chunk_in += chunk_size;
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len -= chunk_size;
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}
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return true;
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}
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uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) {
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switch (self->spim_peripheral->spim.p_reg->FREQUENCY) {
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case NRF_SPIM_FREQ_125K:
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return 125000;
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case NRF_SPIM_FREQ_250K:
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return 250000;
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case NRF_SPIM_FREQ_500K:
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return 500000;
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case NRF_SPIM_FREQ_1M:
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return 1000000;
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case NRF_SPIM_FREQ_2M:
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return 2000000;
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case NRF_SPIM_FREQ_4M:
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return 4000000;
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case NRF_SPIM_FREQ_8M:
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return 8000000;
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#ifdef SPIM_FREQUENCY_FREQUENCY_M16
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case NRF_SPIM_FREQ_16M:
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return 16000000;
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#endif
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#ifdef SPIM_FREQUENCY_FREQUENCY_M32
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case NRF_SPIM_FREQ_32M:
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return 32000000;
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#endif
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default:
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return 0;
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}
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}
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uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) {
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return (self->spim_peripheral->spim.p_reg->CONFIG & SPIM_CONFIG_CPHA_Msk) >> SPIM_CONFIG_CPHA_Pos;
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}
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uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) {
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return (self->spim_peripheral->spim.p_reg->CONFIG & SPIM_CONFIG_CPOL_Msk) >> SPIM_CONFIG_CPOL_Pos;
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}
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