6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
679 lines
20 KiB
C
679 lines
20 KiB
C
/* Auto-generated config file hpl_sysctrl_config.h */
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#ifndef HPL_SYSCTRL_CONFIG_H
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#define HPL_SYSCTRL_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#define CONF_DFLL_OPEN_LOOP_MODE 0
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#define CONF_DFLL_CLOSED_LOOP_MODE 1
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#define CONF_XOSC_STARTUP_TIME_31MCS 0
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#define CONF_XOSC_STARTUP_TIME_61MCS 1
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#define CONF_XOSC_STARTUP_TIME_122MCS 2
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#define CONF_XOSC_STARTUP_TIME_244MCS 3
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#define CONF_XOSC_STARTUP_TIME_488MCS 4
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#define CONF_XOSC_STARTUP_TIME_977MCS 5
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#define CONF_XOSC_STARTUP_TIME_1953MCS 6
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#define CONF_XOSC_STARTUP_TIME_3906MCS 7
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#define CONF_XOSC_STARTUP_TIME_7813MCS 8
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#define CONF_XOSC_STARTUP_TIME_15625MCS 9
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#define CONF_XOSC_STARTUP_TIME_31250MCS 10
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#define CONF_XOSC_STARTUP_TIME_62500MCS 11
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#define CONF_XOSC_STARTUP_TIME_125000MCS 12
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#define CONF_XOSC_STARTUP_TIME_250000MCS 13
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#define CONF_XOSC_STARTUP_TIME_500000MCS 14
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#define CONF_XOSC_STARTUP_TIME_1000000MCS 15
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#define CONF_OSC_STARTUP_TIME_92MCS 0
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#define CONF_OSC_STARTUP_TIME_122MCS 1
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#define CONF_OSC_STARTUP_TIME_183MCS 2
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#define CONF_OSC_STARTUP_TIME_305MCS 3
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#define CONF_OSC_STARTUP_TIME_549MCS 4
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#define CONF_OSC_STARTUP_TIME_1038MCS 5
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#define CONF_OSC_STARTUP_TIME_2014MCS 6
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#define CONF_OSC_STARTUP_TIME_3967MCS 7
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#define CONF_XOSC32K_STARTUP_TIME_122MCS 0
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#define CONF_XOSC32K_STARTUP_TIME_1068MCS 1
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#define CONF_XOSC32K_STARTUP_TIME_65592MCS 2
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#define CONF_XOSC32K_STARTUP_TIME_125092MCS 3
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#define CONF_XOSC32K_STARTUP_TIME_500092MCS 4
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#define CONF_XOSC32K_STARTUP_TIME_1000092MCS 5
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#define CONF_XOSC32K_STARTUP_TIME_2000092MCS 6
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#define CONF_XOSC32K_STARTUP_TIME_4000092MCS 7
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// <e> 8MHz Internal Oscillator Configuration
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// <i> Indicates whether configuration for OSC8M is enabled or not
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// <id> enable_osc8m
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#ifndef CONF_OSC8M_CONFIG
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#define CONF_OSC8M_CONFIG 1
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#endif
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// <h> 8MHz Internal Oscillator (OSC8M) Control
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// <q> Internal 8M Oscillator Enable
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// <i> Indicates whether Internal 8 Mhz Oscillator is enabled or not
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// <id> osc8m_arch_enable
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#ifndef CONF_OSC8M_ENABLE
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#define CONF_OSC8M_ENABLE 1
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not.
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// <i> If enabled, the oscillator will only be running when requested by a peripheral.
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// <i> If disabled, the oscillator will always be running when enabled.
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// <id> osc8m_arch_ondemand
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#ifndef CONF_OSC8M_ONDEMAND
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#define CONF_OSC8M_ONDEMAND 1
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#endif
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// <q> Run In Standby
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// <i> Run In standby Mode
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// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
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// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
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// <id> osc8m_arch_runstdby
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#ifndef CONF_OSC8M_RUNSTDBY
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#define CONF_OSC8M_RUNSTDBY 0
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#endif
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// <y> Prescaler
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// <SYSCTRL_OSC8M_PRESC_0_Val"> 1
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// <SYSCTRL_OSC8M_PRESC_1_Val"> 2
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// <SYSCTRL_OSC8M_PRESC_2_Val"> 4
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// <SYSCTRL_OSC8M_PRESC_3_Val"> 8
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// <i> Prescaler for Internal 8Mhz OSC
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// <i> Default: No Prescaling
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// <id> osc8m_presc
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#ifndef CONF_OSC8M_PRESC
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#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val
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#endif
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// <q> Overwrite Default Osc Calibration
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// <i> Overwrite Default Osc Calibration
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// <id> osc8m_arch_overwrite_calibration
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#ifndef CONF_OSC8M_OVERWRITE_CALIBRATION
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#define CONF_OSC8M_OVERWRITE_CALIBRATION 0
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#endif
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// <o>Osc Calibration Value <0-65535>
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// <i> Set the Oscillator Calibration Value
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// <i> Default: 1
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// <id> osc8m_arch_calib
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#ifndef CONF_OSC8M_CALIB
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#define CONF_OSC8M_CALIB 0
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#endif
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// </h>
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// </e>
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// <e> 32kHz Internal Oscillator Configuration
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// <i> Indicates whether configuration for OSC32K is enabled or not
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// <id> enable_osc32k
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#ifndef CONF_OSC32K_CONFIG
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#define CONF_OSC32K_CONFIG 0
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#endif
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// <h> 32kHz Internal Oscillator (OSC32K) Control
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// <q> Internal 32K Oscillator Enable
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// <i> Indicates whether Internal 32K Oscillator is enabled or not
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// <id> osc32k_arch_enable
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#ifndef CONF_OSC32K_ENABLE
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#define CONF_OSC32K_ENABLE 0
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#endif
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// <q> On Demand Control
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// <i> Enable On Demand
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// <i> If this bit is 0: The oscillator is always on, if enabled.
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// <i> If this bit is 1, the oscillator will only be running when requested by a peripheral.
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// <id> osc32k_arch_ondemand
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#ifndef CONF_OSC32K_ONDEMAND
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#define CONF_OSC32K_ONDEMAND 1
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#endif
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// <q> Run In Standby
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// <i> Run In standby Mode
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// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
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// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
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// <id> osc32k_arch_runstdby
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#ifndef CONF_OSC32K_RUNSTDBY
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#define CONF_OSC32K_RUNSTDBY 0
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#endif
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// <q> Enable 32Khz Output
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// <i> Enable 32 Khz Output
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// <id> osc32k_arch_en32k
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#ifndef CONF_OSC32K_EN32K
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#define CONF_OSC32K_EN32K 0
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#endif
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// <q> Enable 1K
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// <i> Enable 1K
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// <id> osc32k_arch_en1k
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#ifndef CONF_OSC32K_EN1K
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#define CONF_OSC32K_EN1K 0
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#endif
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// <q> Write Lock
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// <i> Write Lock
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// <id> osc32k_arch_wrtlock
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#ifndef CONF_OSC32K_WRTLOCK
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#define CONF_OSC32K_WRTLOCK 0
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#endif
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// <y> Start up time for the 32K Oscillator
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// <CONF_OSC_STARTUP_TIME_92MCS"> 3 Clock Cycles (92us)
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// <CONF_OSC_STARTUP_TIME_122MCS"> 4 Clock Cycles (122us)
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// <CONF_OSC_STARTUP_TIME_183MCS"> 6 Clock Cycles (183us)
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// <CONF_OSC_STARTUP_TIME_305MCS"> 10 Clock Cycles (305us)
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// <CONF_OSC_STARTUP_TIME_549MCS"> 18 Clock Cycles (549us)
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// <CONF_OSC_STARTUP_TIME_1038MCS"> 34 Clock Cycles (1038us)
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// <CONF_OSC_STARTUP_TIME_2014MCS"> 66 Clock Cycles (2014us)
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// <CONF_OSC_STARTUP_TIME_3967MCS"> 130 Clock Cycles (3967us)
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// <i> Start Up Time for the 32K Oscillator
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// <i> Default: 10 Clock Cycles (305us)
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// <id> osc32k_arch_startup
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#ifndef CONF_OSC32K_STARTUP
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#define CONF_OSC32K_STARTUP CONF_OSC_STARTUP_TIME_92MCS
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#endif
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// <q> Overwrite Default Osc Calibration
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// <i> Overwrite Default Osc Calibration
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// <id> osc32k_arch_overwrite_calibration
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#ifndef CONF_OSC32K_OVERWRITE_CALIBRATION
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#define CONF_OSC32K_OVERWRITE_CALIBRATION 0
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#endif
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// <o>Osc Calibration Value <0-65535>
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// <i> Set the Oscillator Calibration Value
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// <i> Default: 0
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// <id> osc32k_arch_calib
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#ifndef CONF_OSC32K_CALIB
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#define CONF_OSC32K_CALIB 0
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#endif
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// </h>
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// </e>
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// <e> 32kHz External Crystal Oscillator Configuration
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// <i> Indicates whether configuration for External 32K Osc is enabled or not
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// <id> enable_xosc32k
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#ifndef CONF_XOSC32K_CONFIG
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#define CONF_XOSC32K_CONFIG 0
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#endif
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// <h> 32kHz External Crystal Oscillator (XOSC32K) Control
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// <q> External 32K Oscillator Enable
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// <i> Indicates whether External 32K Oscillator is enabled or not
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// <id> xosc32k_arch_enable
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#ifndef CONF_XOSC32K_ENABLE
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#define CONF_XOSC32K_ENABLE 0
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#endif
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// <q> On Demand
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// <i> Enable On Demand.
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// <i> If this bit is 0: The oscillator is always on, if enabled.
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// <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
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// <id> xosc32k_arch_ondemand
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#ifndef CONF_XOSC32K_ONDEMAND
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#define CONF_XOSC32K_ONDEMAND 1
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#endif
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// <q> Run In Standby
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// <i> Run In standby Mode
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// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
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// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
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// <id> xosc32k_arch_runstdby
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#ifndef CONF_XOSC32K_RUNSTDBY
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#define CONF_XOSC32K_RUNSTDBY 0
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#endif
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// <q> Enable 1K
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// <i> Enable 1K
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// <id> xosc32k_arch_en1k
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#ifndef CONF_XOSC32K_EN1K
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#define CONF_XOSC32K_EN1K 0
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#endif
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// <q> Enable 32Khz Output
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// <i> Enable 32 Khz Output
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// <id> xosc32k_arch_en32k
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#ifndef CONF_XOSC32K_EN32K
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#define CONF_XOSC32K_EN32K 0
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#endif
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// <q> Enable XTAL
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// <i> Enable XTAL
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// <id> xosc32k_arch_xtalen
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#ifndef CONF_XOSC32K_XTALEN
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#define CONF_XOSC32K_XTALEN 0
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#endif
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// <q> Write Lock
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// <i> Write Lock
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// <id> xosc32k_arch_wrtlock
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#ifndef CONF_XOSC32K_WRTLOCK
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#define CONF_XOSC32K_WRTLOCK 0
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#endif
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// <q> Automatic Amplitude Control Enable
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// <i> Indicates whether Automatic Amplitude Control is Enabled or not
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// <id> xosc32k_arch_aampen
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#ifndef CONF_XOSC32K_AAMPEN
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#define CONF_XOSC32K_AAMPEN 0
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#endif
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// <y> Start up time for the 32K Oscillator
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// <CONF_XOSC32K_STARTUP_TIME_122MCS"> 122 us
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// <CONF_XOSC32K_STARTUP_TIME_1068MCS"> 1068 us
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// <CONF_XOSC32K_STARTUP_TIME_65592MCS"> 62592 us
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// <CONF_XOSC32K_STARTUP_TIME_125092MCS"> 1125092 us
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// <CONF_XOSC32K_STARTUP_TIME_500092MCS"> 500092 us
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// <CONF_XOSC32K_STARTUP_TIME_1000092MCS"> 1000092 us
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// <CONF_XOSC32K_STARTUP_TIME_2000092MCS"> 2000092 us
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// <CONF_XOSC32K_STARTUP_TIME_4000092MCS"> 4000092 us
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// <i> Start Up Time for the 32K Oscillator
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// <i> Default: 122 us
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// <id> xosc32k_arch_startup
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#ifndef CONF_XOSC32K_STARTUP
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#define CONF_XOSC32K_STARTUP CONF_XOSC32K_STARTUP_TIME_122MCS
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#endif
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// </h>
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// </e>
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// <e> External Multipurpose Crystal Oscillator Configuration
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// <i> Indicates whether configuration for External Multipurpose Osc is enabled or not
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// <id> enable_xosc
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#ifndef CONF_XOSC_CONFIG
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#define CONF_XOSC_CONFIG 0
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#endif
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// <o> Frequency <400000-32000000>
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// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
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// <id> xosc_frequency
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#ifndef CONF_XOSC_FREQUENCY
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#define CONF_XOSC_FREQUENCY 400000
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#endif
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// <h> External Multipurpose Crystal Oscillator (XOSC) Control
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// <q> Enable
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// <i> Indicates whether External Multipurpose Oscillator is enabled or not
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// <id> xosc_arch_enable
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#ifndef CONF_XOSC_ENABLE
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#define CONF_XOSC_ENABLE 0
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#endif
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// <q> On Demand
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// <i> Enable On Demand
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// <i> If this bit is 0: The oscillator is always on, if enabled.
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// <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
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// <id> xosc_arch_ondemand
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#ifndef CONF_XOSC_ONDEMAND
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#define CONF_XOSC_ONDEMAND 1
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#endif
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// <q> Run In Standby
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// <i> Run In standby Mode
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// <i> If this bit is 0: The oscillator is disabled in standby sleep mode.
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// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
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// <id> xosc_arch_runstdby
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#ifndef CONF_XOSC_RUNSTDBY
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#define CONF_XOSC_RUNSTDBY 0
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#endif
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// <q> Enable XTAL
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// <i> Enable XTAL
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// <id> xosc_arch_xtalen
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#ifndef CONF_XOSC_XTALEN
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#define CONF_XOSC_XTALEN 0
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#endif
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// <q> Automatic Amplitude Control Enable
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// <i> Indicates whether Automatic Amplitude Control is Enabled or not
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// <id> xosc_arch_ampgc
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#ifndef CONF_XOSC_AMPGC
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#define CONF_XOSC_AMPGC 0
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#endif
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// <y> Gain of the Oscillator
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// <SYSCTRL_XOSC_GAIN_0_Val"> 2Mhz
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// <SYSCTRL_XOSC_GAIN_1_Val"> 4Mhz
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// <SYSCTRL_XOSC_GAIN_2_Val"> 8Mhz
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// <SYSCTRL_XOSC_GAIN_3_Val"> 16Mhz
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// <SYSCTRL_XOSC_GAIN_4_Val"> 30Mhz
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// <i> Select the Gain of the oscillator
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// <id> xosc_arch_gain
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#ifndef CONF_XOSC_GAIN
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#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val
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#endif
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// <y> Start up time for the External Oscillator
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// <CONF_XOSC_STARTUP_TIME_31MCS"> 31 us
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// <CONF_XOSC_STARTUP_TIME_61MCS"> 61 us
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// <CONF_XOSC_STARTUP_TIME_122MCS"> 122 us
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// <CONF_XOSC_STARTUP_TIME_244MCS"> 244 us
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// <CONF_XOSC_STARTUP_TIME_488MCS"> 488 us
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// <CONF_XOSC_STARTUP_TIME_977MCS"> 977 us
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// <CONF_XOSC_STARTUP_TIME_1953MCS"> 1953 us
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// <CONF_XOSC_STARTUP_TIME_3906MCS"> 3906 us
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// <CONF_XOSC_STARTUP_TIME_7813MCS"> 7813 us
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// <CONF_XOSC_STARTUP_TIME_15625MCS"> 15625 us
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// <CONF_XOSC_STARTUP_TIME_31250MCS"> 31250 us
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// <CONF_XOSC_STARTUP_TIME_62500MCS"> 62500 us
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// <CONF_XOSC_STARTUP_TIME_125000MCS"> 125000 us
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// <CONF_XOSC_STARTUP_TIME_250000MCS"> 250000 us
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// <CONF_XOSC_STARTUP_TIME_500000MCS"> 500000 us
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// <CONF_XOSC_STARTUP_TIME_1000000MCS"> 1000000 us
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// <i> Start Up Time for the External Oscillator
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// <i> Default: 31 us
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// <id> xosc_arch_startup
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#ifndef CONF_XOSC_STARTUP
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#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS
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#endif
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// </h>
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// </e>
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// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
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// <i> Indicates whether configuration for OSCULP32K is enabled or not
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// <id> enable_osculp32k
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#ifndef CONF_OSCULP32K_CONFIG
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#define CONF_OSCULP32K_CONFIG 1
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#endif
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// <h> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
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// <q> Write Lock
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// <i> Locks the OSCULP32K register for future writes to fix the OSCULP32K configuration
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// <id> osculp32k_arch_wrtlock
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#ifndef CONF_OSCULP32K_WRTLOCK
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#define CONF_OSCULP32K_WRTLOCK 0
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#endif
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// <q> Overwrite Default Osc Calibration
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// <i> Overwrite Default Osc Calibration
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// <id> osculp32k_arch_overwrite_calibration
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#ifndef CONF_OSCULP32K_OVERWRITE_CALIBRATION
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#define CONF_OSCULP32K_OVERWRITE_CALIBRATION 0
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#endif
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// <o>Osc Calibration Value <0-255>
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// <i> Set the Oscillator Calibration Value
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// <i> Default: 0
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// <id> osculp32k_arch_calib
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#ifndef CONF_OSCULP32K_CALIB
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#define CONF_OSCULP32K_CALIB 0
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#endif
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// </h>
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// </e>
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// <e> DFLL Configuration
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// <i> Indicates whether configuration for DFLL is enabled or not
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// <id> enable_dfll48m
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#ifndef CONF_DFLL_CONFIG
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#define CONF_DFLL_CONFIG 1
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#endif
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// <y> Reference Clock Source
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source.
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// <id> dfll48m_ref_clock
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#ifndef CONF_DFLL_GCLK
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#define CONF_DFLL_GCLK GCLK_CLKCTRL_GEN_GCLK4_Val
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#endif
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// <h> DFLL Control
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// <q> DFLL Enable
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// <i> Indicates whether DFLL is enabled or not
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// <id> dfll48m_arch_enable
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#ifndef CONF_DFLL_ENABLE
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#define CONF_DFLL_ENABLE 1
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#endif
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// <q> Wait Lock
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// <i> Indicates whether Wait Lock is Enables or not
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// <id> dfll48m_arch_waitlock
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#ifndef CONF_DFLL_WAITLOCK
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#define CONF_DFLL_WAITLOCK 0
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#endif
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// <q> Bypass Coarse Lock
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// <i> Indicates whether Bypass coarse lock is enabled or not
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// <id> dfll48m_arch_bplckc
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#ifndef CONF_DFLL_BPLCKC
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#define CONF_DFLL_BPLCKC 0
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#endif
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// <q> Quick Lock Disable
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// <i> Quick Lock Disable
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// <id> dfll48m_arch_qldis
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#ifndef CONF_DFLL_QLDIS
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#define CONF_DFLL_QLDIS 0
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#endif
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// <q> Chill Cycle Disable
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// <i> Chill Cycle Disable
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// <id> dfll48m_arch_ccdis
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#ifndef CONF_DFLL_CCDIS
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#define CONF_DFLL_CCDIS 1
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#endif
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// <q> On Demand
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// <i> Enable On Demand
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// <i> If this bit is 0: The DFLL is always on, if enabled.
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// <i> If this bit is 1: the DFLL will only be running when requested by a peripheral.
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// <id> dfll48m_arch_ondemand
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#ifndef CONF_DFLL_ONDEMAND
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#define CONF_DFLL_ONDEMAND 0
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#endif
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// <q> Run In Standby
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// <i> Run In standby Mode
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// <i> If this bit is 0: The DFLL is disabled in standby sleep mode.
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// <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
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// <id> dfll48m_arch_runstdby
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#ifndef CONF_DFLL_RUNSTDBY
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#define CONF_DFLL_RUNSTDBY 0
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#endif
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// <q> USB Clock Recovery Mode
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// <i> USB Clock Recovery Mode
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// <id> dfll48m_arch_usbcrm
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#ifndef CONF_DFLL_USBCRM
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#define CONF_DFLL_USBCRM 1
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#endif
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#if CONF_DFLL_USBCRM == 1
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#if CONF_DFLL_QLDIS == 1
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#warning QLDIS must be cleared to speed up the lock phase
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#endif
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#if CONF_DFLL_CCDIS == 0
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#warning CCDIS should be set to speed up the lock phase
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#endif
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#endif
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// <q> Lose Lock After Wake
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// <i> Lose Lock After Wake
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// <id> dfll48m_arch_llaw
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#ifndef CONF_DFLL_LLAW
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#define CONF_DFLL_LLAW 0
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#endif
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// <q> Stable DFLL Frequency
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// <i> Stable DFLL Frequency
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// <i> If 0: FINE calibration tracks changes in output frequency.
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// <i> If 1: FINE calibration register value will be fixed after a fine lock.
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// <id> dfll48m_arch_stable
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#ifndef CONF_DFLL_STABLE
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#define CONF_DFLL_STABLE 0
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#endif
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// <y> Operating Mode Selection
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// <CONF_DFLL_OPEN_LOOP_MODE"> Open Loop Mode
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// <CONF_DFLL_CLOSED_LOOP_MODE"> Closed Loop Mode
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// <i> Mode
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// <id> dfll48m_mode
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#ifndef CONF_DFLL_MODE
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#define CONF_DFLL_MODE CONF_DFLL_CLOSED_LOOP_MODE
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#endif
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// <o> Coarse Maximum Step <0x0-0x1F>
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// <id> dfll_arch_cstep
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#ifndef CONF_DFLL_CSTEP
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#define CONF_DFLL_CSTEP 1
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#endif
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// <o> Fine Maximum Step <0x0-0x3FF>
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// <id> dfll_arch_fstep
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#ifndef CONF_DFLL_FSTEP
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#define CONF_DFLL_FSTEP 1
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#endif
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// <o>DFLL Multiply Factor<0-65535>
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// <i> Set the DFLL Multiply Factor
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// <i> Default: 0
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// <id> dfll48m_mul
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#ifndef CONF_DFLL_MUL
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#define CONF_DFLL_MUL 48000
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#endif
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// <e> DFLL Calibration Overwrite
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// <i> Indicates whether Overwrite Calibration value of DFLL
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// <id> dfll48m_arch_calibration
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#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
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#define CONF_DFLL_OVERWRITE_CALIBRATION 0
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#endif
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// <o> Coarse Value <0x0-0x3F>
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// <id> dfll48m_arch_coarse
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#ifndef CONF_DFLL_COARSE
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#define CONF_DFLL_COARSE (0x1f)
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#endif
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// <o> Fine Value <0x0-0x3FF>
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// <id> dfll48m_arch_fine
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#ifndef CONF_DFLL_FINE
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#define CONF_DFLL_FINE (0x200)
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#endif
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#if CONF_DFLL_OVERWRITE_CALIBRATION == 0
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#define CONF_DEFAULT_CORASE \
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((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos)
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#define CONF_DFLLVAL \
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SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \
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| SYSCTRL_DFLLVAL_FINE(512)
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#else
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#define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)
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#endif
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//</e>
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// </h>
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// </e>
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// <e> DPLL Configuration
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// <i> Indicates whether configuration for DPLL is enabled or not
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// <id> enable_fdpll96m
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#ifndef CONF_DPLL_CONFIG
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#define CONF_DPLL_CONFIG 0
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#endif
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// <y> Reference Clock Source
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source.
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// <id> fdpll96m_ref_clock
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#ifndef CONF_DPLL_GCLK
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#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val
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#endif
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#if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K)
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#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val
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#elif (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC)
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#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val
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#else
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#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val
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#endif
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// <h> DPLL Control
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// <q> ON Demand
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// <i> Enable On Demand
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// <i> If this bit is 0: The DFLL is always on, if enabled.
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// <i> If this bit is 1: the DFLL will only be running when requested by a peripheral.
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// <id> fdpll96m_arch_ondemand
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#ifndef CONF_DPLL_ONDEMAND
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#define CONF_DPLL_ONDEMAND 1
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#endif
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// <q> Run In Standby
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// <i> Run In standby Mode
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// <i> If this bit is 0: The DFLL is disabled in standby sleep mode.
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// <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
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// <id> fdpll96m_arch_runstdby
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#ifndef CONF_DPLL_RUNSTDBY
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#define CONF_DPLL_RUNSTDBY 0
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#endif
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// <q> DPLL Enable
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// <i> Indicates whether DPLL is enabled or not
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// <id> fdpll96m_arch_enable
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#ifndef CONF_DPLL_ENABLE
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#define CONF_DPLL_ENABLE 0
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#endif
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// <q> Lock ByPass
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// <i> Enabling it makes the CLK_FDPLL96M always running otherwise it will be turned off when lock signal is low
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// <id> fdpll96m_arch_lbypass
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#ifndef CONF_DPLL_LBYPASS
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#define CONF_DPLL_LBYPASS 0
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#endif
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// <o>Clock Divider <0-2047>
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// <i> Clock Division Factor (Applicable if reference clock is XOSC)
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// <id> fdpll96m_clock_div
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#ifndef CONF_DPLL_DIV
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#define CONF_DPLL_DIV 0
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#endif
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// <o>DPLL LDRFRAC<0-15>
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// <i> Set the fractional part of the frequency multiplier.
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// <id> fdpll96m_ldrfrac
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#ifndef CONF_DPLL_LDRFRAC
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#define CONF_DPLL_LDRFRAC 13
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#endif
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// <o>DPLL LDR <0-4095>
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// <i> Set the integer part of the frequency multiplier.
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// <id> fdpll96m_ldr
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#ifndef CONF_DPLL_LDR
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#define CONF_DPLL_LDR 1463
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#endif
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// </h>
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// </e>
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#define CONF_DPLL_LTIME SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val
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#define CONF_DPLL_WUF 0
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#define CONF_DPLL_LPEN 0
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#define CONF_DPLL_FILTER SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val
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// <<< end of configuration section >>>
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#endif // HPL_SYSCTRL_CONFIG_H
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