6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/* Auto-generated config file hpl_pm_config.h */
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#ifndef HPL_PM_CONFIG_H
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#define HPL_PM_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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// <e> System Configuration
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// <i> Indicates whether configuration for system is enabled or not
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// <id> enable_cpu_clock
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#ifndef CONF_SYSTEM_CONFIG
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#define CONF_SYSTEM_CONFIG 1
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#endif
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// <h> CPU Clock Settings
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// <y> CPU Clock source
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <i> This defines the clock source for the CPU
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// <id> cpu_clock_source
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#ifndef CONF_CPU_SRC
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#define CONF_CPU_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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// <y> CPU clock Prescalar
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// <PM_CPUSEL_CPUDIV_DIV1_Val"> 1
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// <PM_CPUSEL_CPUDIV_DIV2_Val"> 2
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// <PM_CPUSEL_CPUDIV_DIV4_Val"> 4
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// <PM_CPUSEL_CPUDIV_DIV8_Val"> 8
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// <PM_CPUSEL_CPUDIV_DIV16_Val"> 16
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// <PM_CPUSEL_CPUDIV_DIV32_Val"> 32
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// <PM_CPUSEL_CPUDIV_DIV64_Val"> 64
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// <PM_CPUSEL_CPUDIV_DIV128_Val"> 128
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// <i> Prescalar for Main CPU clock
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// <id> cpu_div
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#ifndef CONF_CPU_DIV
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#define CONF_CPU_DIV PM_CPUSEL_CPUDIV_DIV1_Val
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#endif
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// </h>
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// <h> NVM Settings
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// <o> NVM Wait States
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// <i> These bits select the number of wait states for a read operation.
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// <0=> 0
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// <1=> 1
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// <2=> 2
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// <3=> 3
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// <4=> 4
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// <5=> 5
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// <6=> 6
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// <7=> 7
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// <8=> 8
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// <9=> 9
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// <10=> 10
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// <11=> 11
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// <12=> 12
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// <13=> 13
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// <14=> 14
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// <15=> 15
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// <id> nvm_wait_states
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#ifndef CONF_NVM_WAIT_STATE
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#define CONF_NVM_WAIT_STATE 2
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#endif
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// </h>
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// <h> APBA Clock Select
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// <y> APBA clock prescalar
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// <PM_APBASEL_APBADIV_DIV1"> 1
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// <PM_APBASEL_APBADIV_DIV2"> 2
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// <PM_APBASEL_APBADIV_DIV4"> 4
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// <PM_APBASEL_APBADIV_DIV8"> 8
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// <PM_APBASEL_APBADIV_DIV16"> 16
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// <PM_APBASEL_APBADIV_DIV32"> 32
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// <PM_APBASEL_APBADIV_DIV64"> 64
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// <PM_APBASEL_APBADIV_DIV128"> 128
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// <i> APBA clock prescalar
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// <id> apba_div
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#ifndef CONF_APBA_DIV
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#define CONF_APBA_DIV PM_APBASEL_APBADIV_DIV1
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#endif
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// </h>
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#if CONF_APBA_DIV < CONF_CPU_DIV
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#warning APBA DIV cannot less than CPU DIV
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#endif
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// <h> APBB Clock Select
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// <y> APBB clock prescalar
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// <PM_APBBSEL_APBBDIV_DIV1"> 1
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// <PM_APBBSEL_APBBDIV_DIV2"> 2
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// <PM_APBBSEL_APBBDIV_DIV4"> 4
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// <PM_APBBSEL_APBBDIV_DIV8"> 8
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// <PM_APBBSEL_APBBDIV_DIV16"> 16
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// <PM_APBBSEL_APBBDIV_DIV32"> 32
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// <PM_APBBSEL_APBBDIV_DIV64"> 64
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// <PM_APBBSEL_APBBDIV_DIV128"> 128
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// <i> APBB clock prescalar
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// <id> apbb_div
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#ifndef CONF_APBB_DIV
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#define CONF_APBB_DIV PM_APBBSEL_APBBDIV_DIV1
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#endif
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// </h>
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#if CONF_APBB_DIV < CONF_CPU_DIV
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#warning APBB DIV cannot less than CPU DIV
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#endif
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// <h> APBC Clock Select
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// <y> APBC clock prescalar
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// <PM_APBCSEL_APBCDIV_DIV1"> 1
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// <PM_APBCSEL_APBCDIV_DIV2"> 2
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// <PM_APBCSEL_APBCDIV_DIV4"> 4
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// <PM_APBCSEL_APBCDIV_DIV8"> 8
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// <PM_APBCSEL_APBCDIV_DIV16"> 16
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// <PM_APBCSEL_APBCDIV_DIV32"> 32
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// <PM_APBCSEL_APBCDIV_DIV64"> 64
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// <PM_APBCSEL_APBCDIV_DIV128"> 128
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// <i> APBC clock prescalar
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// <id> apbc_div
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#ifndef CONF_APBC_DIV
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#define CONF_APBC_DIV PM_APBCSEL_APBCDIV_DIV1
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#endif
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// </h>
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#if CONF_APBC_DIV < CONF_CPU_DIV
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#warning APBC DIV cannot less than CPU DIV
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#endif
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// </e>
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// <<< end of configuration section >>>
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#endif // HPL_PM_CONFIG_H
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