437 lines
15 KiB
C
437 lines
15 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "shared_dma.h"
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#include <string.h>
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#include "py/gc.h"
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#include "py/mpstate.h"
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#include "hal/utils/include/utils.h"
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#include "shared-bindings/microcontroller/__init__.h"
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// We allocate three DMA resources for the entire lifecycle of the board (not the
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// vm) because the general_dma resource will be shared between the REPL and SPI
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// flash. Both uses must block each other in order to prevent conflict.
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COMPILER_ALIGNED(16) static DmacDescriptor dma_descriptors[3];
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// Don't use these directly. They are used by the DMA engine itself.
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COMPILER_ALIGNED(16) static DmacDescriptor write_back_descriptors[3];
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#define AUDIO_DMA_CHANNEL 0
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#define SHARED_TX_CHANNEL 1
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#define SHARED_RX_CHANNEL 2
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#ifdef SAMD21
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#define FIRST_SERCOM_RX_TRIGSRC 0x01
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#define FIRST_SERCOM_TX_TRIGSRC 0x02
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#endif
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#ifdef SAMD51
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#define FIRST_SERCOM_RX_TRIGSRC 0x04
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#define FIRST_SERCOM_TX_TRIGSRC 0x05
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#endif
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// static void dma_configure_audio(uint8_t channel) {
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// system_interrupt_enter_critical_section();
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// /** Select the DMA channel and clear software trigger */
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// DMAC->CHID.reg = DMAC_CHID_ID(channel);
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// DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
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// DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
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// DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << channel));
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// uint32_t event_output_enable = 0;
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// if (output_event) {
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// event_output_enable = DMAC_CHCTRLB_EVOE;
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// }
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// DMAC->CHCTRLB.reg = DMAC_CHCTRLB_LVL(DMA_PRIORITY_LEVEL_0) |
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// DMAC_CHCTRLB_TRIGSRC(trigsrc) |
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// DMAC_CHCTRLB_TRIGACT(DMA_TRIGGER_ACTION_BEAT) |
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// event_output_enable;
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// // config.peripheral_trigger = DAC_DMAC_ID_EMPTY;
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// // config.trigger_action = DMA_TRIGGER_ACTION_BEAT;
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// // config.event_config.input_action = DMA_EVENT_INPUT_TRIG;
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// // config.event_config.event_output_enable = true;
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// system_interrupt_leave_critical_section();
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// }
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void init_shared_dma(void) {
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// Turn on the clocks
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#ifdef SAMD51
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MCLK->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
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#endif
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#ifdef SAMD21
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PM->AHBMASK.reg |= PM_AHBMASK_DMAC;
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PM->APBBMASK.reg |= PM_APBBMASK_DMAC;
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#endif
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DMAC->CTRL.reg = DMAC_CTRL_SWRST;
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DMAC->BASEADDR.reg = (uint32_t) dma_descriptors;
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DMAC->WRBADDR.reg = (uint32_t) write_back_descriptors;
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DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN0;
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// This allocates the lowest channel first so make sure the audio is first
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// so it gets the highest priority.
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// dma_configure_audio(0);
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}
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static uint8_t sercom_index(Sercom* sercom) {
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#ifdef SAMD21
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return ((uint32_t) sercom - (uint32_t) SERCOM0) / 0x400;
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#else
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const Sercom* sercoms[SERCOM_INST_NUM] = SERCOM_INSTS;
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for (uint8_t i = 0; i < SERCOM_INST_NUM; i++) {
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if (sercoms[i] == sercom) {
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return i;
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}
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}
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return 0;
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#endif
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}
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static void dma_configure(uint8_t channel_number, uint8_t trigsrc, bool output_event) {
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#ifdef SAMD21
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common_hal_mcu_disable_interrupts();
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/** Select the DMA channel and clear software trigger */
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DMAC->CHID.reg = DMAC_CHID_ID(channel_number);
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DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
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DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
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DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << channel_number));
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uint32_t event_output_enable = 0;
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if (output_event) {
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event_output_enable = DMAC_CHCTRLB_EVOE;
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}
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DMAC->CHCTRLB.reg = DMAC_CHCTRLB_LVL_LVL0 |
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DMAC_CHCTRLB_TRIGSRC(trigsrc) |
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DMAC_CHCTRLB_TRIGACT_BEAT |
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event_output_enable;
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common_hal_mcu_enable_interrupts();
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#endif
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#ifdef SAMD51
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DmacChannel* channel = &DMAC->Channel[channel_number];
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channel->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
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channel->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
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if (output_event) {
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channel->CHEVCTRL.reg = DMAC_CHEVCTRL_EVOE;
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}
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channel->CHCTRLA.reg = DMAC_CHCTRLA_TRIGSRC(trigsrc) |
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DMAC_CHCTRLA_TRIGACT_BURST |
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DMAC_CHCTRLA_BURSTLEN_SINGLE;
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#endif
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}
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static void enable_channel(uint8_t channel_number) {
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#ifdef SAMD21
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common_hal_mcu_disable_interrupts();
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/** Select the DMA channel and clear software trigger */
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DMAC->CHID.reg = DMAC_CHID_ID(channel_number);
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DMAC->CHCTRLA.bit.ENABLE = true;
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common_hal_mcu_enable_interrupts();
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#endif
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#ifdef SAMD51
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DmacChannel* channel = &DMAC->Channel[channel_number];
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channel->CHCTRLA.bit.ENABLE = true;
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#endif
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}
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static uint8_t transfer_status(uint8_t channel_number) {
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#ifdef SAMD21
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common_hal_mcu_disable_interrupts();
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/** Select the DMA channel and clear software trigger */
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DMAC->CHID.reg = DMAC_CHID_ID(channel_number);
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uint8_t status = DMAC->CHINTFLAG.reg;
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common_hal_mcu_enable_interrupts();
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return status;
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#endif
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#ifdef SAMD51
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DmacChannel* channel = &DMAC->Channel[channel_number];
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return channel->CHINTFLAG.reg;
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#endif
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}
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static bool channel_free(uint8_t channel_number) {
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#ifdef SAMD21
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common_hal_mcu_disable_interrupts();
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/** Select the DMA channel and clear software trigger */
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DMAC->CHID.reg = DMAC_CHID_ID(channel_number);
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bool channel_free = DMAC->CHSTATUS.reg == 0;
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common_hal_mcu_enable_interrupts();
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return channel_free;
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#endif
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#ifdef SAMD51
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DmacChannel* channel = &DMAC->Channel[channel_number];
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return channel->CHSTATUS.reg == 0;
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#endif
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}
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// Do write and read simultaneously. If buffer_out is NULL, write the tx byte over and over.
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// If buffer_out is a real buffer, ignore tx.
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// DMAs buffer_out -> dest
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// DMAs src -> buffer_in
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static int32_t shared_dma_transfer(void* peripheral,
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const uint8_t* buffer_out, volatile uint32_t* dest,
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volatile uint32_t* src, uint8_t* buffer_in,
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uint32_t length, uint8_t tx) {
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if (!channel_free(SHARED_TX_CHANNEL) ||
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(buffer_in != NULL && !channel_free(SHARED_RX_CHANNEL))) {
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return -1;
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}
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uint32_t beat_size = DMAC_BTCTRL_BEATSIZE_BYTE;
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bool sercom = true;
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bool tx_active = false;
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bool rx_active = false;
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uint16_t beat_length = length;
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#ifdef SAMD51
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if (peripheral == QSPI) {
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// Check input alignment on word boundaries.
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if ((((uint32_t) buffer_in) & 0x3) != 0 ||
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(((uint32_t) buffer_out) & 0x3) != 0) {
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return -3;
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}
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beat_size = DMAC_BTCTRL_BEATSIZE_WORD | DMAC_BTCTRL_SRCINC | DMAC_BTCTRL_DSTINC;
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beat_length /= 4;
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sercom = false;
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if (buffer_out != NULL) {
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dma_configure(SHARED_TX_CHANNEL, QSPI_DMAC_ID_TX, false);
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tx_active = true;
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} else {
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dma_configure(SHARED_RX_CHANNEL, QSPI_DMAC_ID_RX, false);
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rx_active = true;
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}
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} else {
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#endif
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// sercom index is incorrect for SAMD51
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dma_configure(SHARED_TX_CHANNEL, sercom_index(peripheral) * 2 + FIRST_SERCOM_TX_TRIGSRC, false);
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tx_active = true;
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if (buffer_in != NULL) {
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dma_configure(SHARED_RX_CHANNEL, sercom_index(peripheral) * 2 + FIRST_SERCOM_RX_TRIGSRC, false);
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rx_active = true;
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}
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#ifdef SAMD51
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}
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#endif
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// Set up RX first.
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if (rx_active) {
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DmacDescriptor* rx_descriptor = &dma_descriptors[SHARED_RX_CHANNEL];
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rx_descriptor->BTCTRL.reg = beat_size | DMAC_BTCTRL_DSTINC;
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rx_descriptor->BTCNT.reg = beat_length;
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rx_descriptor->SRCADDR.reg = ((uint32_t) src);
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#ifdef SAMD51
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if (peripheral == QSPI) {
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rx_descriptor->SRCADDR.reg = ((uint32_t) src + length);
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}
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#endif
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rx_descriptor->DSTADDR.reg = ((uint32_t)buffer_in + length);
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rx_descriptor->BTCTRL.bit.VALID = true;
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}
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// Set up TX second.
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if (tx_active) {
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DmacDescriptor* tx_descriptor = &dma_descriptors[SHARED_TX_CHANNEL];
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tx_descriptor->BTCTRL.reg = beat_size;
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tx_descriptor->BTCNT.reg = beat_length;
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if (buffer_out != NULL) {
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tx_descriptor->SRCADDR.reg = ((uint32_t)buffer_out + length);
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tx_descriptor->BTCTRL.reg |= DMAC_BTCTRL_SRCINC;
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} else {
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tx_descriptor->SRCADDR.reg = ((uint32_t) &tx);
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}
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tx_descriptor->DSTADDR.reg = ((uint32_t) dest);
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tx_descriptor->BTCTRL.bit.VALID = true;
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}
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if (sercom) {
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SercomSpi *s = &((Sercom*) peripheral)->SPI;
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s->INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_DRE;
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} else {
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//QSPI->INTFLAG.reg = QSPI_INTFLAG_RXC | QSPI_INTFLAG_DRE;
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}
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// Start the RX job first so we don't miss the first byte. The TX job clocks
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// the output.
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if (rx_active) {
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enable_channel(SHARED_RX_CHANNEL);
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}
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if (tx_active) {
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enable_channel(SHARED_TX_CHANNEL);
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}
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if (sercom) {
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//DMAC->SWTRIGCTRL.reg |= (1 << SHARED_TX_CHANNEL);
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} else {
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// Do a manual copy to trigger then DMA. We do 32-bit accesses to match the DMA.
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wcast-align"
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if (rx_active) {
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//buffer_in[0] = *src;
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DMAC->SWTRIGCTRL.reg |= (1 << SHARED_RX_CHANNEL);
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} else {
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//*(uint32_t*)dest = ((uint32_t*) buffer_out)[0];
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}
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#pragma GCC diagnostic pop
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}
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// Channels cycle between Suspend -> Pending -> Busy and back while transfering. So, we check
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// the channels transfer status for an error or completion.
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if (rx_active) {
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while ((transfer_status(SHARED_RX_CHANNEL) & 0x3) == 0) {}
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}
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if (tx_active) {
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while ((transfer_status(SHARED_TX_CHANNEL) & 0x3) == 0) {}
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}
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if (sercom) {
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Sercom* s = (Sercom*) peripheral;
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// Wait for the SPI transfer to complete.
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while (s->SPI.INTFLAG.bit.TXC == 0) {}
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// This transmit will cause the RX buffer overflow but we're OK with that.
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// So, read the garbage and clear the overflow flag.
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if (!rx_active) {
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while (s->SPI.INTFLAG.bit.RXC == 1) {
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s->SPI.DATA.reg;
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}
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s->SPI.STATUS.bit.BUFOVF = 1;
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s->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
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}
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}
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if ((!rx_active || transfer_status(SHARED_RX_CHANNEL) == DMAC_CHINTFLAG_TCMPL) &&
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(!tx_active || transfer_status(SHARED_TX_CHANNEL) == DMAC_CHINTFLAG_TCMPL)) {
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return length;
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}
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return -2;
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}
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int32_t sercom_dma_transfer(Sercom* sercom, const uint8_t* buffer_out, uint8_t* buffer_in,
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uint32_t length) {
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return shared_dma_transfer(sercom, buffer_out, &sercom->SPI.DATA.reg, &sercom->SPI.DATA.reg, buffer_in, length, 0);
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}
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int32_t sercom_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_t length) {
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return shared_dma_transfer(sercom, buffer, &sercom->SPI.DATA.reg, NULL, NULL, length, 0);
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}
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int32_t sercom_dma_read(Sercom* sercom, uint8_t* buffer, uint32_t length, uint8_t tx) {
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return shared_dma_transfer(sercom, NULL, &sercom->SPI.DATA.reg, &sercom->SPI.DATA.reg, buffer, length, tx);
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}
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#ifdef SAMD51
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int32_t qspi_dma_write(uint32_t address, const uint8_t* buffer, uint32_t length) {
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return shared_dma_transfer(QSPI, buffer, (uint32_t*) (QSPI_AHB + address), NULL, NULL, length, 0);
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}
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int32_t qspi_dma_read(uint32_t address, uint8_t* buffer, uint32_t length) {
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return shared_dma_transfer(QSPI, NULL, NULL, (uint32_t*) (QSPI_AHB + address), buffer, length, 0);
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}
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#endif
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bool allocate_block_counter() {
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// // Find a timer to count DMA block completions.
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// Tc *t = NULL;
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// Tc *tcs[TC_INST_NUM] = TC_INSTS;
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// for (uint8_t i = TC_INST_NUM; i > 0; i--) {
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// if (tcs[i - 1]->COUNT16.CTRLA.bit.ENABLE == 0) {
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// t = tcs[i - 1];
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// break;
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// }
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// }
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// if (t == NULL) {
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// return false;
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// }
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// MP_STATE_VM(audiodma_block_counter) = gc_alloc(sizeof(struct tc_module), false);
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// if (MP_STATE_VM(audiodma_block_counter) == NULL) {
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// return false;
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// }
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//
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// // Don't bother setting the period. We set it before you playback anything.
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// struct tc_config config_tc;
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// tc_get_config_defaults(&config_tc);
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// config_tc.counter_size = TC_COUNTER_SIZE_16BIT;
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// config_tc.clock_prescaler = TC_CLOCK_PRESCALER_DIV1;
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// if (tc_init(MP_STATE_VM(audiodma_block_counter), t, &config_tc) != STATUS_OK) {
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// return false;
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// };
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//
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// struct tc_events events_tc;
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// events_tc.generate_event_on_overflow = false;
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// events_tc.on_event_perform_action = true;
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// events_tc.event_action = TC_EVENT_ACTION_INCREMENT_COUNTER;
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// tc_enable_events(MP_STATE_VM(audiodma_block_counter), &events_tc);
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//
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// // Connect the timer overflow event, which happens at the target frequency,
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// // to the DAC conversion trigger.
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// MP_STATE_VM(audiodma_block_event) = gc_alloc(sizeof(struct events_resource), false);
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// if (MP_STATE_VM(audiodma_block_event) == NULL) {
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// return false;
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// }
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// struct events_config config;
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// events_get_config_defaults(&config);
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//
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// uint8_t user = EVSYS_ID_USER_TC3_EVU;
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// if (t == TC4) {
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// user = EVSYS_ID_USER_TC4_EVU;
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// } else if (t == TC5) {
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// user = EVSYS_ID_USER_TC5_EVU;
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// #ifdef TC6
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// } else if (t == TC6) {
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// user = EVSYS_ID_USER_TC6_EVU;
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// #endif
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// #ifdef TC7
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// } else if (t == TC7) {
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// user = EVSYS_ID_USER_TC7_EVU;
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// #endif
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// }
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//
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// config.generator = EVSYS_ID_GEN_DMAC_CH_0;
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// config.path = EVENTS_PATH_ASYNCHRONOUS;
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// if (events_allocate(MP_STATE_VM(audiodma_block_event), &config) != STATUS_OK ||
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// events_attach_user(MP_STATE_VM(audiodma_block_event), user) != STATUS_OK) {
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// return false;
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// }
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//
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// tc_enable(MP_STATE_VM(audiodma_block_counter));
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// tc_stop_counter(MP_STATE_VM(audiodma_block_counter));
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return true;
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}
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void switch_audiodma_trigger(uint8_t trigger_dmac_id) {
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//dma_configure(audio_dma.channel_id, trigger_dmac_id, true);
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}
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