139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexspi.h"
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#include "internal_flash.h"
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#include "boards/flash_config.h"
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#include "supervisor/internal_flash.h"
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#include "supervisor/linker.h"
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STATIC status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type * base, uint32_t baseAddr)
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{
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flexspi_transfer_t flashXfer;
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status_t status;
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/* Write enable */
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flashXfer.deviceAddress = baseAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = ROM_INDEX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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return status;
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}
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STATIC status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type * base)
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{
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/* Wait status ready. */
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bool isBusy;
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uint32_t readValue;
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status_t status;
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flexspi_transfer_t flashXfer;
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = ROM_INDEX_READSTATUSREG;
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flashXfer.data = &readValue;
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flashXfer.dataSize = 1;
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do
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{
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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size_t busyBit = readValue & (1U << qspiflash_config.memConfig.busyOffset);
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isBusy = (qspiflash_config.memConfig.busyBitPolarity == 0 && busyBit != 0) ||
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(qspiflash_config.memConfig.busyBitPolarity == 1 && busyBit == 0);
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} while (isBusy);
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return status;
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}
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status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type * base, uint32_t address)
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{
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Write enable */
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = ROM_INDEX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = ROM_INDEX_ERASESECTOR;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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/* Do software reset. */
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FLEXSPI_SoftwareReset(base);
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return status;
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}
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status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type * base, uint32_t dstAddr, const uint32_t *src)
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{
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Write enable */
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status = flexspi_nor_write_enable(base, dstAddr);
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if (status != kStatus_Success) {
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return status;
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}
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/* Prepare page program command */
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flashXfer.deviceAddress = dstAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = ROM_INDEX_PAGEPROGRAM;
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flashXfer.data = (uint32_t *)src;
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flashXfer.dataSize = FLASH_PAGE_SIZE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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/* Do software reset. */
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#if defined(FSL_FEATURE_SOC_OTFAD_COUNT)
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base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK;
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base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK);
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#else
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FLEXSPI_SoftwareReset(base);
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#endif
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return status;
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}
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