04c7cdb668
Entering a bootloader (ST system bootloader, or custom mboot) from software by directly branching to it is not reliable, and the reliability of it working can depend on the peripherals that were enabled by the application code. It's also not possible to branch to a bootloader if the WDT is enabled (unless the bootloader has specific provisions to feed the WDT). This patch changes the way a bootloader is entered from software by first doing a complete system reset, then branching to the desired bootloader early on in the start-up process. The top two words of RAM (of the stack) are reserved to store flags indicating that the bootloader should be entered after a reset.
463 lines
16 KiB
C
463 lines
16 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013-2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "powerctrl.h"
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#include "rtc.h"
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#include "genhdr/pllfreqtable.h"
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#if defined(STM32H7)
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#define RCC_SR RSR
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#define RCC_SR_SFTRSTF RCC_RSR_SFTRSTF
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#define RCC_SR_RMVF RCC_RSR_RMVF
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#else
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#define RCC_SR CSR
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#define RCC_SR_SFTRSTF RCC_CSR_SFTRSTF
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#define RCC_SR_RMVF RCC_CSR_RMVF
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#endif
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// Location in RAM of bootloader state (just after the top of the stack)
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extern uint32_t _estack[];
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#define BL_STATE ((uint32_t*)&_estack)
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NORETURN void powerctrl_mcu_reset(void) {
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BL_STATE[1] = 1; // invalidate bootloader address
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#if __DCACHE_PRESENT == 1
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SCB_CleanDCache();
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#endif
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NVIC_SystemReset();
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}
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NORETURN void powerctrl_enter_bootloader(uint32_t r0, uint32_t bl_addr) {
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BL_STATE[0] = r0;
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BL_STATE[1] = bl_addr;
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#if __DCACHE_PRESENT == 1
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SCB_CleanDCache();
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#endif
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NVIC_SystemReset();
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}
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static __attribute__((naked)) void branch_to_bootloader(uint32_t r0, uint32_t bl_addr) {
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__asm volatile (
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"ldr r2, [r1, #0]\n" // get address of stack pointer
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"msr msp, r2\n" // get stack pointer
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"ldr r2, [r1, #4]\n" // get address of destination
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"bx r2\n" // branch to bootloader
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);
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}
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void powerctrl_check_enter_bootloader(void) {
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uint32_t bl_addr = BL_STATE[1];
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BL_STATE[1] = 1; // invalidate bootloader address
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if ((bl_addr & 0xfff) == 0 && (RCC->RCC_SR & RCC_SR_SFTRSTF)) {
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// Reset by NVIC_SystemReset with bootloader data set -> branch to bootloader
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RCC->RCC_SR = RCC_SR_RMVF;
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#if defined(STM32F0) || defined(STM32F4) || defined(STM32L4)
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__HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH();
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#endif
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uint32_t r0 = BL_STATE[0];
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branch_to_bootloader(r0, bl_addr);
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}
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}
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#if !defined(STM32F0)
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// Assumes that PLL is used as the SYSCLK source
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int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk_mhz, bool need_pllsai) {
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uint32_t flash_latency;
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#if defined(STM32F7)
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if (need_pllsai) {
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// Configure PLLSAI at 48MHz for those peripherals that need this freq
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const uint32_t pllsain = 192;
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const uint32_t pllsaip = 4;
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const uint32_t pllsaiq = 2;
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RCC->PLLSAICFGR = pllsaiq << RCC_PLLSAICFGR_PLLSAIQ_Pos
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| (pllsaip / 2 - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos
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| pllsain << RCC_PLLSAICFGR_PLLSAIN_Pos;
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RCC->CR |= RCC_CR_PLLSAION;
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uint32_t ticks = mp_hal_ticks_ms();
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while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {
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if (mp_hal_ticks_ms() - ticks > 200) {
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return -MP_ETIMEDOUT;
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}
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}
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RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
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}
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// If possible, scale down the internal voltage regulator to save power
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uint32_t volt_scale;
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if (sysclk_mhz <= 151) {
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volt_scale = PWR_REGULATOR_VOLTAGE_SCALE3;
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} else if (sysclk_mhz <= 180) {
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volt_scale = PWR_REGULATOR_VOLTAGE_SCALE2;
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} else {
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volt_scale = PWR_REGULATOR_VOLTAGE_SCALE1;
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}
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if (HAL_PWREx_ControlVoltageScaling(volt_scale) != HAL_OK) {
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return -MP_EIO;
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}
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// These flash_latency values assume a supply voltage between 2.7V and 3.6V
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if (sysclk_mhz <= 30) {
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flash_latency = FLASH_LATENCY_0;
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} else if (sysclk_mhz <= 60) {
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flash_latency = FLASH_LATENCY_1;
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} else if (sysclk_mhz <= 90) {
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flash_latency = FLASH_LATENCY_2;
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} else if (sysclk_mhz <= 120) {
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flash_latency = FLASH_LATENCY_3;
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} else if (sysclk_mhz <= 150) {
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flash_latency = FLASH_LATENCY_4;
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} else if (sysclk_mhz <= 180) {
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flash_latency = FLASH_LATENCY_5;
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} else if (sysclk_mhz <= 210) {
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flash_latency = FLASH_LATENCY_6;
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} else {
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flash_latency = FLASH_LATENCY_7;
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}
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#elif defined(MICROPY_HW_FLASH_LATENCY)
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flash_latency = MICROPY_HW_FLASH_LATENCY;
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#else
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flash_latency = FLASH_LATENCY_5;
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#endif
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rcc_init->SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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if (HAL_RCC_ClockConfig(rcc_init, flash_latency) != HAL_OK) {
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return -MP_EIO;
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}
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return 0;
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}
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#endif
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#if !(defined(STM32F0) || defined(STM32L4))
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STATIC uint32_t calc_ahb_div(uint32_t wanted_div) {
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if (wanted_div <= 1) { return RCC_SYSCLK_DIV1; }
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else if (wanted_div <= 2) { return RCC_SYSCLK_DIV2; }
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else if (wanted_div <= 4) { return RCC_SYSCLK_DIV4; }
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else if (wanted_div <= 8) { return RCC_SYSCLK_DIV8; }
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else if (wanted_div <= 16) { return RCC_SYSCLK_DIV16; }
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else if (wanted_div <= 64) { return RCC_SYSCLK_DIV64; }
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else if (wanted_div <= 128) { return RCC_SYSCLK_DIV128; }
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else if (wanted_div <= 256) { return RCC_SYSCLK_DIV256; }
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else { return RCC_SYSCLK_DIV512; }
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}
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STATIC uint32_t calc_apb_div(uint32_t wanted_div) {
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if (wanted_div <= 1) { return RCC_HCLK_DIV1; }
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else if (wanted_div <= 2) { return RCC_HCLK_DIV2; }
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else if (wanted_div <= 4) { return RCC_HCLK_DIV4; }
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else if (wanted_div <= 8) { return RCC_HCLK_DIV8; }
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else { return RCC_SYSCLK_DIV16; }
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}
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int powerctrl_set_sysclk(uint32_t sysclk, uint32_t ahb, uint32_t apb1, uint32_t apb2) {
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// Return straightaway if the clocks are already at the desired frequency
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if (sysclk == HAL_RCC_GetSysClockFreq()
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&& ahb == HAL_RCC_GetHCLKFreq()
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&& apb1 == HAL_RCC_GetPCLK1Freq()
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&& apb2 == HAL_RCC_GetPCLK2Freq()) {
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return 0;
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}
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// Default PLL parameters that give 48MHz on PLL48CK
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uint32_t m = MICROPY_HW_CLK_VALUE / 1000000, n = 336, p = 2, q = 7;
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uint32_t sysclk_source;
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bool need_pllsai = false;
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// Search for a valid PLL configuration that keeps USB at 48MHz
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uint32_t sysclk_mhz = sysclk / 1000000;
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for (const uint16_t *pll = &pll_freq_table[MP_ARRAY_SIZE(pll_freq_table) - 1]; pll >= &pll_freq_table[0]; --pll) {
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uint32_t sys = *pll & 0xff;
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if (sys <= sysclk_mhz) {
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m = (*pll >> 10) & 0x3f;
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p = ((*pll >> 7) & 0x6) + 2;
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if (m == 0) {
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// special entry for using HSI directly
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sysclk_source = RCC_SYSCLKSOURCE_HSI;
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} else if (m == 1) {
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// special entry for using HSE directly
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sysclk_source = RCC_SYSCLKSOURCE_HSE;
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} else {
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// use PLL
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sysclk_source = RCC_SYSCLKSOURCE_PLLCLK;
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uint32_t vco_out = sys * p;
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n = vco_out * m / (MICROPY_HW_CLK_VALUE / 1000000);
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q = vco_out / 48;
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#if defined(STM32F7)
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need_pllsai = vco_out % 48 != 0;
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#endif
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}
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goto set_clk;
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}
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}
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return -MP_EINVAL;
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set_clk:
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// Let the USB CDC have a chance to process before we change the clock
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mp_hal_delay_ms(5);
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// Desired system clock source is in sysclk_source
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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if (sysclk_source == RCC_SYSCLKSOURCE_PLLCLK) {
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// Set HSE as system clock source to allow modification of the PLL configuration
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// We then change to PLL after re-configuring PLL
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#if MICROPY_HW_CLK_USE_HSI
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
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#else
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
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#endif
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} else {
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// Directly set the system clock source as desired
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RCC_ClkInitStruct.SYSCLKSource = sysclk_source;
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}
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// Determine the bus clock dividers
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// Note: AHB freq required to be >= 14.2MHz for USB operation
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RCC_ClkInitStruct.AHBCLKDivider = calc_ahb_div(sysclk / ahb);
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#if !defined(STM32H7)
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ahb = sysclk >> AHBPrescTable[RCC_ClkInitStruct.AHBCLKDivider >> RCC_CFGR_HPRE_Pos];
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#endif
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RCC_ClkInitStruct.APB1CLKDivider = calc_apb_div(ahb / apb1);
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RCC_ClkInitStruct.APB2CLKDivider = calc_apb_div(ahb / apb2);
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#if MICROPY_HW_CLK_LAST_FREQ
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// Save the bus dividers for use later
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uint32_t h = RCC_ClkInitStruct.AHBCLKDivider >> 4;
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uint32_t b1 = RCC_ClkInitStruct.APB1CLKDivider >> 10;
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uint32_t b2 = RCC_ClkInitStruct.APB2CLKDivider >> 10;
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#endif
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// Configure clock
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
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return -MP_EIO;
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}
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#if defined(STM32F7)
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// Deselect PLLSAI as 48MHz source if we were using it
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RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_CK48MSEL;
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// Turn PLLSAI off because we are changing PLLM (which drives PLLSAI)
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RCC->CR &= ~RCC_CR_PLLSAION;
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#endif
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// Re-configure PLL
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// Even if we don't use the PLL for the system clock, we still need it for USB, RNG and SDIO
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_OscInitStruct.OscillatorType = MICROPY_HW_RCC_OSCILLATOR_TYPE;
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RCC_OscInitStruct.HSEState = MICROPY_HW_RCC_HSE_STATE;
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RCC_OscInitStruct.HSIState = MICROPY_HW_RCC_HSI_STATE;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = MICROPY_HW_RCC_PLL_SRC;
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RCC_OscInitStruct.PLL.PLLM = m;
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RCC_OscInitStruct.PLL.PLLN = n;
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RCC_OscInitStruct.PLL.PLLP = p;
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RCC_OscInitStruct.PLL.PLLQ = q;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return -MP_EIO;
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}
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// Set PLL as system clock source if wanted
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if (sysclk_source == RCC_SYSCLKSOURCE_PLLCLK) {
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
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int ret = powerctrl_rcc_clock_config_pll(&RCC_ClkInitStruct, sysclk_mhz, need_pllsai);
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if (ret != 0) {
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return ret;
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}
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}
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#if MICROPY_HW_CLK_LAST_FREQ
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// Save settings in RTC backup register to reconfigure clocks on hard-reset
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#if defined(STM32F7)
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#define FREQ_BKP BKP31R
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#else
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#define FREQ_BKP BKP19R
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#endif
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// qqqqqqqq pppppppp nnnnnnnn nnmmmmmm
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// qqqqQQQQ ppppppPP nNNNNNNN NNMMMMMM
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// 222111HH HHQQQQPP nNNNNNNN NNMMMMMM
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p = (p / 2) - 1;
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RTC->FREQ_BKP = m
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| (n << 6) | (p << 16) | (q << 18)
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| (h << 22)
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| (b1 << 26)
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| (b2 << 29);
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#endif
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return 0;
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}
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#endif
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void powerctrl_enter_stop_mode(void) {
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// Disable IRQs so that the IRQ that wakes the device from stop mode is not
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// executed until after the clocks are reconfigured
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uint32_t irq_state = disable_irq();
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#if defined(STM32L4)
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// Configure the MSI as the clock source after waking up
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__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
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#endif
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#if !defined(STM32F0) && !defined(STM32L4)
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// takes longer to wake but reduces stop current
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HAL_PWREx_EnableFlashPowerDown();
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#endif
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# if defined(STM32F7)
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HAL_PWR_EnterSTOPMode((PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS | PWR_CR1_UDEN), PWR_STOPENTRY_WFI);
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# else
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HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
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#endif
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// reconfigure the system clock after waking up
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#if defined(STM32F0)
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// Enable HSI48
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__HAL_RCC_HSI48_ENABLE();
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while (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY)) {
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}
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// Select HSI48 as system clock source
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_HSI48);
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI48) {
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}
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#else
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#if !defined(STM32L4)
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// enable clock
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__HAL_RCC_HSE_CONFIG(MICROPY_HW_RCC_HSE_STATE);
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#if MICROPY_HW_CLK_USE_HSI
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__HAL_RCC_HSI_ENABLE();
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#endif
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while (!__HAL_RCC_GET_FLAG(MICROPY_HW_RCC_FLAG_HSxRDY)) {
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}
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#endif
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// enable PLL
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__HAL_RCC_PLL_ENABLE();
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while (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)) {
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}
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// select PLL as system clock source
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
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#if defined(STM32H7)
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) {
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}
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#else
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
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}
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#endif
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#if defined(STM32F7)
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if (RCC->DCKCFGR2 & RCC_DCKCFGR2_CK48MSEL) {
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// Enable PLLSAI if it is selected as 48MHz source
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RCC->CR |= RCC_CR_PLLSAION;
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while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {
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}
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}
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#endif
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#if defined(STM32L4)
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// Enable PLLSAI1 for peripherals that use it
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RCC->CR |= RCC_CR_PLLSAI1ON;
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while (!(RCC->CR & RCC_CR_PLLSAI1RDY)) {
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}
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#endif
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#endif
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// Enable IRQs now that all clocks are reconfigured
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enable_irq(irq_state);
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}
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void powerctrl_enter_standby_mode(void) {
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rtc_init_finalise();
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// We need to clear the PWR wake-up-flag before entering standby, since
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// the flag may have been set by a previous wake-up event. Furthermore,
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// we need to disable the wake-up sources while clearing this flag, so
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// that if a source is active it does actually wake the device.
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// See section 5.3.7 of RM0090.
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// Note: we only support RTC ALRA, ALRB, WUT and TS.
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// TODO support TAMP and WKUP (PA0 external pin).
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#if defined(STM32F0)
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#define CR_BITS (RTC_CR_ALRAIE | RTC_CR_WUTIE | RTC_CR_TSIE)
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#define ISR_BITS (RTC_ISR_ALRAF | RTC_ISR_WUTF | RTC_ISR_TSF)
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#else
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#define CR_BITS (RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_WUTIE | RTC_CR_TSIE)
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#define ISR_BITS (RTC_ISR_ALRAF | RTC_ISR_ALRBF | RTC_ISR_WUTF | RTC_ISR_TSF)
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#endif
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// save RTC interrupts
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uint32_t save_irq_bits = RTC->CR & CR_BITS;
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// disable RTC interrupts
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RTC->CR &= ~CR_BITS;
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// clear RTC wake-up flags
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RTC->ISR &= ~ISR_BITS;
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#if defined(STM32F7)
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// disable wake-up flags
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PWR->CSR2 &= ~(PWR_CSR2_EWUP6 | PWR_CSR2_EWUP5 | PWR_CSR2_EWUP4 | PWR_CSR2_EWUP3 | PWR_CSR2_EWUP2 | PWR_CSR2_EWUP1);
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// clear global wake-up flag
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PWR->CR2 |= PWR_CR2_CWUPF6 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF1;
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#elif defined(STM32H7)
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// TODO
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#elif defined(STM32L4)
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// clear all wake-up flags
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PWR->SCR |= PWR_SCR_CWUF5 | PWR_SCR_CWUF4 | PWR_SCR_CWUF3 | PWR_SCR_CWUF2 | PWR_SCR_CWUF1;
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// TODO
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#else
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// clear global wake-up flag
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PWR->CR |= PWR_CR_CWUF;
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#endif
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// enable previously-enabled RTC interrupts
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RTC->CR |= save_irq_bits;
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|
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#if defined(STM32F7)
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// Enable the internal (eg RTC) wakeup sources
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// See Errata 2.2.2 "Wakeup from Standby mode when the back-up SRAM regulator is enabled"
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PWR->CSR1 |= PWR_CSR1_EIWUP;
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#endif
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// enter standby mode
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HAL_PWR_EnterSTANDBYMode();
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// we never return; MCU is reset on exit from standby
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}
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