a9dc31a881
This adds a script to generate the peripherals files (except clock). It adds support for the 1015, 1020, 1040, and 1050 EVKs. Some work was started on 1176 but it isn't working. So, the board def is in a separate branch. Fixes #3521. Fixes #2477.
403 lines
18 KiB
C
403 lines
18 KiB
C
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Artur Pacholec
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* Copyright 2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "mpconfigport.h"
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#include "fsl_clock.h"
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#include "fsl_iomuxc.h"
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#include "fsl_device_registers.h"
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#include "board.h"
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#include "clocks.h"
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#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
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#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
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.numerator = 0, /* 30 bit numerator of fractional loop divider */
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.denominator = 1, /* 30 bit denominator of fractional loop divider */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.postDivider = 8, /* Divider after PLL */
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.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void clocks_init(void) {
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/* Init RTC OSC clock frequency. */
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CLOCK_SetRtcXtalFreq(32768U);
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/* Enable 1MHz clock output. */
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XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
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/* Use free 1MHz clock output. */
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XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
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/* Set XTAL 24MHz clock frequency. */
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CLOCK_SetXtalFreq(24000000U);
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/* Enable XTAL 24MHz clock source. */
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CLOCK_InitExternalClk(0);
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/* Enable internal RC. */
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CLOCK_InitRcOsc24M();
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/* Switch clock source to external OSC. */
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CLOCK_SwitchOsc(kCLOCK_XtalOsc);
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/* Set Oscillator ready counter value. */
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CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
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/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
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CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
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CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
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/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
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/* Waiting for DCDC_STS_DC_OK bit is asserted */
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while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
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}
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/* Set AHB_PODF. */
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CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
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/* Disable IPG clock gate. */
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CLOCK_DisableClock(kCLOCK_Adc1);
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CLOCK_DisableClock(kCLOCK_Adc2);
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CLOCK_DisableClock(kCLOCK_Xbar1);
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CLOCK_DisableClock(kCLOCK_Xbar2);
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CLOCK_DisableClock(kCLOCK_Xbar3);
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/* Set IPG_PODF. */
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CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
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/* Set ARM_PODF. */
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CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
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/* Set PERIPH_CLK2_PODF. */
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CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
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/* Disable PERCLK clock gate. */
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CLOCK_DisableClock(kCLOCK_Gpt1);
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CLOCK_DisableClock(kCLOCK_Gpt1S);
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CLOCK_DisableClock(kCLOCK_Gpt2);
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CLOCK_DisableClock(kCLOCK_Gpt2S);
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CLOCK_DisableClock(kCLOCK_Pit);
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/* Set PERCLK_PODF. */
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CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
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/* Disable USDHC1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Usdhc1);
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/* Set USDHC1_PODF. */
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CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
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/* Set Usdhc1 clock source. */
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CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
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/* Disable USDHC2 clock gate. */
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CLOCK_DisableClock(kCLOCK_Usdhc2);
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/* Set USDHC2_PODF. */
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CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
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/* Set Usdhc2 clock source. */
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CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
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/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
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* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
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#ifndef SKIP_SYSCLK_INIT
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/* Disable Semc clock gate. */
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CLOCK_DisableClock(kCLOCK_Semc);
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/* Set SEMC_PODF. */
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CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
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/* Set Semc alt clock source. */
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CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
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/* Set Semc clock source. */
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CLOCK_SetMux(kCLOCK_SemcMux, 0);
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#endif
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/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
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* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
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#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
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#error "whoops"
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/* Disable Flexspi clock gate. */
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CLOCK_DisableClock(kCLOCK_FlexSpi);
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/* Set FLEXSPI_PODF. */
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CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
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/* Set Flexspi clock source. */
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CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
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#endif
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/* Disable CSI clock gate. */
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CLOCK_DisableClock(kCLOCK_Csi);
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/* Set CSI_PODF. */
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CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
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/* Set Csi clock source. */
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CLOCK_SetMux(kCLOCK_CsiMux, 0);
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/* Disable LPSPI clock gate. */
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CLOCK_DisableClock(kCLOCK_Lpspi1);
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CLOCK_DisableClock(kCLOCK_Lpspi2);
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CLOCK_DisableClock(kCLOCK_Lpspi3);
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CLOCK_DisableClock(kCLOCK_Lpspi4);
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/* Set LPSPI_PODF. */
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CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
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/* Set Lpspi clock source. */
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CLOCK_SetMux(kCLOCK_LpspiMux, 2);
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/* Disable TRACE clock gate. */
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CLOCK_DisableClock(kCLOCK_Trace);
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/* Set TRACE_PODF. */
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CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
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/* Set Trace clock source. */
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CLOCK_SetMux(kCLOCK_TraceMux, 0);
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/* Disable SAI1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Sai1);
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/* Set SAI1_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
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/* Set SAI1_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
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/* Set Sai1 clock source. */
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CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
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/* Disable SAI2 clock gate. */
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CLOCK_DisableClock(kCLOCK_Sai2);
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/* Set SAI2_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
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/* Set SAI2_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
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/* Set Sai2 clock source. */
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CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
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/* Disable SAI3 clock gate. */
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CLOCK_DisableClock(kCLOCK_Sai3);
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/* Set SAI3_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
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/* Set SAI3_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
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/* Set Sai3 clock source. */
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CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
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/* Disable Lpi2c clock gate. */
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CLOCK_DisableClock(kCLOCK_Lpi2c1);
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CLOCK_DisableClock(kCLOCK_Lpi2c2);
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CLOCK_DisableClock(kCLOCK_Lpi2c3);
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/* Set LPI2C_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
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/* Set Lpi2c clock source. */
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CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
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/* Disable CAN clock gate. */
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CLOCK_DisableClock(kCLOCK_Can1);
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CLOCK_DisableClock(kCLOCK_Can2);
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CLOCK_DisableClock(kCLOCK_Can1S);
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CLOCK_DisableClock(kCLOCK_Can2S);
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/* Set CAN_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_CanDiv, 1);
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/* Set Can clock source. */
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CLOCK_SetMux(kCLOCK_CanMux, 2);
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/* Disable UART clock gate. */
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CLOCK_DisableClock(kCLOCK_Lpuart1);
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CLOCK_DisableClock(kCLOCK_Lpuart2);
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CLOCK_DisableClock(kCLOCK_Lpuart3);
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CLOCK_DisableClock(kCLOCK_Lpuart4);
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CLOCK_DisableClock(kCLOCK_Lpuart5);
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CLOCK_DisableClock(kCLOCK_Lpuart6);
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CLOCK_DisableClock(kCLOCK_Lpuart7);
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CLOCK_DisableClock(kCLOCK_Lpuart8);
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/* Set UART_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_UartDiv, 0);
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/* Set Uart clock source. */
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CLOCK_SetMux(kCLOCK_UartMux, 0);
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/* Disable LCDIF clock gate. */
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CLOCK_DisableClock(kCLOCK_LcdPixel);
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/* Set LCDIF_PRED. */
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CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
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/* Set LCDIF_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
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/* Set Lcdif pre clock source. */
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CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
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/* Disable SPDIF clock gate. */
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CLOCK_DisableClock(kCLOCK_Spdif);
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/* Set SPDIF0_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
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/* Set SPDIF0_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
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/* Set Spdif clock source. */
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CLOCK_SetMux(kCLOCK_SpdifMux, 3);
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/* Disable Flexio1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Flexio1);
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/* Set FLEXIO1_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
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/* Set FLEXIO1_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
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/* Set Flexio1 clock source. */
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CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
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/* Disable Flexio2 clock gate. */
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CLOCK_DisableClock(kCLOCK_Flexio2);
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/* Set FLEXIO2_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
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/* Set FLEXIO2_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
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/* Set Flexio2 clock source. */
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CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
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/* Set Pll3 sw clock source. */
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CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
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/* Init ARM PLL. */
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CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
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/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
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* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
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#ifndef SKIP_SYSCLK_INIT
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#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
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#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
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#endif
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/* Init System PLL. */
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CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
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/* Init System pfd0. */
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CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
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/* Init System pfd1. */
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CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
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/* Init System pfd2. */
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
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/* Init System pfd3. */
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CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
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#endif
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/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
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* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
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#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
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/* Init Usb1 PLL. */
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CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
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/* Init Usb1 pfd0. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
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/* Init Usb1 pfd1. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
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/* Init Usb1 pfd2. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
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/* Init Usb1 pfd3. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
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/* Disable Usb1 PLL output for USBPHY1. */
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CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
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#endif
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/* DeInit Audio PLL. */
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CLOCK_DeinitAudioPll();
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/* Bypass Audio PLL. */
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CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
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/* Set divider for Audio PLL. */
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CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
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CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
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/* Enable Audio PLL output. */
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CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
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/* Init Video PLL. */
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uint32_t pllVideo;
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/* Disable Video PLL output before initial Video PLL. */
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CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
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/* Bypass PLL first */
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CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
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CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
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CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
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CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
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pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
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CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
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pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
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CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
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CCM_ANALOG->PLL_VIDEO = pllVideo;
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while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) {
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}
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/* Disable bypass for Video PLL. */
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CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
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/* DeInit Enet PLL. */
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CLOCK_DeinitEnetPll();
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/* Bypass Enet PLL. */
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CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
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/* Set Enet output divider. */
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CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
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/* Enable Enet output. */
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CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
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/* Enable Enet25M output. */
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CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
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/* DeInit Usb2 PLL. */
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CLOCK_DeinitUsb2Pll();
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/* Bypass Usb2 PLL. */
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CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
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/* Enable Usb2 PLL output. */
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CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
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/* Set preperiph clock source. */
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CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
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/* Set periph clock source. */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0);
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/* Set periph clock2 clock source. */
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CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
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/* Set per clock source. */
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CLOCK_SetMux(kCLOCK_PerclkMux, 0);
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/* Set lvds1 clock source. */
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CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
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/* Set clock out1 divider. */
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CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
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/* Set clock out1 source. */
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CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
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/* Set clock out2 divider. */
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CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
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/* Set clock out2 source. */
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CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
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/* Set clock out1 drives clock out1. */
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CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
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/* Disable clock out1. */
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CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
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/* Disable clock out2. */
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CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
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/* Set SAI1 MCLK1 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
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/* Set SAI1 MCLK2 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
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/* Set SAI1 MCLK3 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
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/* Set SAI2 MCLK3 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
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/* Set SAI3 MCLK3 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
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/* Set MQS configuration. */
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IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
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/* Set ENET Ref clock source. */
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#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
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IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
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#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
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/* Backward compatibility for original bitfield name */
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IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
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#else
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#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
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#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
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/* Set GPT1 High frequency reference clock source. */
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IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
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/* Set GPT2 High frequency reference clock source. */
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IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
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}
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