03075a6839
Which just sets the CPU clock to 200kHz and switches the peripheral clock
off. There are two modes:
machine.lightsleep(duration_ms)
and
machine.lightsleep()
In any mode any configured pin.irq() event will terminate the sleep.
Current consumption in lightsleep for some boards:
- 1.5 - 2.5 mA when supplied trough an active USB
(Seeed XIAO w/o power LED, Adafruit ItsyBitsy)
- 0.8 - 2 mA when supplied through Gnd/+5V (Vusb)
(Seeed XIAO w/o power LED, Adafruit ItsyBitsy)
- < 1 mA for SAMD51 when supplied trough a battery connector
(Sparkfun Thing SAMD51 plus)
Related change: move the calls to SysTick_Config() into set_cpu_freq(). It
is required after each CPU freq change to have ticks_ms run at the proper
rate.
237 lines
9.1 KiB
C
237 lines
9.1 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* This file provides functions for configuring the clocks.
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "samd_soc.h"
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static uint32_t cpu_freq = CPU_FREQ;
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static uint32_t peripheral_freq = DFLL48M_FREQ;
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static uint32_t dfll48m_calibration;
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int sercom_gclk_id[] = {
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GCLK_CLKCTRL_ID_SERCOM0_CORE, GCLK_CLKCTRL_ID_SERCOM1_CORE,
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GCLK_CLKCTRL_ID_SERCOM2_CORE, GCLK_CLKCTRL_ID_SERCOM3_CORE,
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GCLK_CLKCTRL_ID_SERCOM4_CORE, GCLK_CLKCTRL_ID_SERCOM5_CORE
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};
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uint32_t get_cpu_freq(void) {
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return cpu_freq;
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}
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uint32_t get_peripheral_freq(void) {
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return peripheral_freq;
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}
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void set_cpu_freq(uint32_t cpu_freq_arg) {
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// Set 1 waitstate to be safe
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_MANW | NVMCTRL_CTRLB_RWS(1);
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int div = DFLL48M_FREQ / cpu_freq_arg;
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peripheral_freq = cpu_freq = DFLL48M_FREQ / div;
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// Enable GCLK output: 48M on both CCLK0 and GCLK2
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(0) | GCLK_GENDIV_DIV(div);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(0);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(div);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(2);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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if (cpu_freq >= 8000000) {
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// Enable GCLK output: 48MHz on GCLK5 for USB
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(5) | GCLK_GENDIV_DIV(1);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(5);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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} else {
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// Disable GCLK output on GCLK5 for USB, since USB is not reliable below 8 Mhz.
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(5);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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}
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// Set 0 waitstates for slower CPU clock
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_MANW | NVMCTRL_CTRLB_RWS(cpu_freq > 24000000 ? 1 : 0);
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SysTick_Config(cpu_freq / 1000);
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}
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void check_usb_recovery_mode(void) {
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#if !MICROPY_HW_XOSC32K
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mp_hal_delay_ms(500);
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// Check USB status. If not connected, switch DFLL48M back to open loop
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if (USB->DEVICE.DeviceEndpoint[0].EPCFG.reg == 0) {
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// Set/keep the open loop mode of the device.
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SYSCTRL->DFLLVAL.reg = dfll48m_calibration;
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_CCDIS | SYSCTRL_DFLLCTRL_ENABLE;
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}
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#endif // MICROPY_HW_XOSC32K
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}
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void init_clocks(uint32_t cpu_freq) {
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dfll48m_calibration = 0; // please the compiler
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// SAMD21 Clock settings
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// GCLK0: 48MHz from DFLL open loop mode or closed loop mode from 32k Crystal
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// GCLK1: 32768 Hz from 32K ULP or DFLL48M
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// GCLK2: 48MHz from DFLL for Peripherals
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// GCLK3: 1Mhz for the us-counter (TC4/TC5)
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// GCLK4: 32kHz from crystal, if present
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// GCLK5: 48MHz from DFLL for USB
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// GCLK8: 1kHz clock for WDT
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NVMCTRL->CTRLB.bit.MANW = 1; // errata "Spurious Writes"
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NVMCTRL->CTRLB.bit.RWS = 1; // 1 read wait state for 48MHz
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#if MICROPY_HW_XOSC32K
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// Set up OSC32K according datasheet 17.6.3
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP(0x3) | SYSCTRL_XOSC32K_EN32K |
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SYSCTRL_XOSC32K_XTALEN;
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SYSCTRL->XOSC32K.bit.ENABLE = 1;
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while (SYSCTRL->PCLKSR.bit.XOSC32KRDY == 0) {
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}
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// Set up the DFLL48 according to the data sheet 17.6.7.1.2
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// Step 1: Set up the reference clock
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#if MICROPY_HW_MCU_OSC32KULP
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// Connect the GCLK1 to the XOSC32KULP
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(1) | GCLK_GENDIV_DIV(1);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K | GCLK_GENCTRL_ID(1);
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#else
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// Connect the GCLK1 to OSC32K via GCLK1 to the DFLL input and for further use.
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(1) | GCLK_GENDIV_DIV(1);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(1);
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#endif
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Connect the GCLK4 to OSC32K via GCLK1 to the DFLL input and for further use.
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(4) | GCLK_GENDIV_DIV(1);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(4);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Connect GCLK4 to the DFLL input and for further use.
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_DFLL48 | GCLK_CLKCTRL_GEN_GCLK4 | GCLK_CLKCTRL_CLKEN;
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// Enable access to the DFLLCTRL reg acc. to Errata 1.2.1
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
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while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
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}
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// Step 2: Set the coarse and fine values.
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// Get the coarse value from the calib data. In case it is not set,
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// set a midrange value.
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uint32_t coarse = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR) & FUSES_DFLL48M_COARSE_CAL_Msk)
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>> FUSES_DFLL48M_COARSE_CAL_Pos;
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if (coarse == 0x3f) {
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coarse = 0x1f;
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}
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SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) | SYSCTRL_DFLLVAL_FINE(512);
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while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
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}
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// Step 3: Set the multiplication values. The offset of 16384 to the freq is for rounding.
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_MUL((CPU_FREQ + 16384) / 32768) |
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SYSCTRL_DFLLMUL_FSTEP(1) | SYSCTRL_DFLLMUL_CSTEP(1);
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while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
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}
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// Step 4: Start the DFLL and wait for the PLL lock. We just wait for the fine lock, since
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// coarse adjusting is bypassed.
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_WAITLOCK | SYSCTRL_DFLLCTRL_STABLE |
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SYSCTRL_DFLLCTRL_BPLCKC | SYSCTRL_DFLLCTRL_ENABLE;
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while (SYSCTRL->PCLKSR.bit.DFLLLCKF == 0) {
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}
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#else // MICROPY_HW_XOSC32K
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// Enable DFLL48M
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {
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}
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uint32_t coarse = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR) & FUSES_DFLL48M_COARSE_CAL_Msk)
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>> FUSES_DFLL48M_COARSE_CAL_Pos;
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if (coarse == 0x3f) {
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coarse = 0x1f;
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}
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SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) | SYSCTRL_DFLLVAL_FINE(511);
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#if MICROPY_HW_DFLL_USB_SYNC
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// Configure the DFLL48M for USB clock recovery.
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// Will have to switch back if no USB
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SYSCTRL->DFLLSYNC.bit.READREQ = 1;
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dfll48m_calibration = SYSCTRL->DFLLVAL.reg;
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// Set the Multiplication factor.
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(1) | SYSCTRL_DFLLMUL_FSTEP(1)
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| SYSCTRL_DFLLMUL_MUL(48000);
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// Set the mode to closed loop USB Recovery mode
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_USBCRM | SYSCTRL_DFLLCTRL_CCDIS
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| SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_ENABLE;
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#else
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// Set/keep the open loop mode of the device.
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_CCDIS | SYSCTRL_DFLLCTRL_ENABLE;
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#endif
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {
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}
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// Enable 32768 Hz on GCLK1 for consistency
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(1) | GCLK_GENDIV_DIV(48016384 / 32768);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(1);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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#endif // MICROPY_HW_XOSC32K
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set_cpu_freq(cpu_freq);
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// Enable GCLK output: 1MHz on GCLK3 for TC4
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(3) | GCLK_GENDIV_DIV(48);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(3);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Set GCLK8 to 1 kHz.
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(8) | GCLK_GENDIV_DIV(32);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K | GCLK_GENCTRL_ID(8);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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}
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void enable_sercom_clock(int id) {
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// Enable synchronous clock. The bits are nicely arranged
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PM->APBCMASK.reg |= 0x04 << id;
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// Select multiplexer generic clock source and enable.
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | sercom_gclk_id[id];
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// Wait while it updates synchronously.
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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}
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