528 lines
14 KiB
C
528 lines
14 KiB
C
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "timers.h"
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#include "py/mpconfig.h"
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#include "py/obj.h"
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#include "py/runtime.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "shared-bindings/microcontroller/Pin.h"
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#if !(CPY_STM32H7)
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#define ALL_CLOCKS 0xFFFF
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#define NULL_IRQ 0xFF
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static bool stm_timer_reserved[MP_ARRAY_SIZE(mcu_tim_banks)];
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static bool stm_timer_never_reset[MP_ARRAY_SIZE(mcu_tim_banks)];
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typedef void (*stm_timer_callback_t)(void);
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// Array of function pointers.
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static stm_timer_callback_t stm_timer_callback[MP_ARRAY_SIZE(mcu_tim_banks)];
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static size_t irq_map[] = {
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#ifdef TIM1
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TIM1_CC_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM2
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TIM2_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM3
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TIM3_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM4
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TIM4_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM5
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TIM5_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM6
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#if !defined(DAC_BASE) && !defined(DAC1_BASE)
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TIM6_IRQn,
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#else
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TIM6_DAC_IRQn,
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#endif
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM7
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TIM7_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM8
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TIM8_CC_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM9
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TIM1_BRK_TIM9_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM10
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TIM1_UP_TIM10_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM11
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TIM1_TRG_COM_TIM11_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM12
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TIM8_BRK_TIM12_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM13
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TIM8_UP_TIM13_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM14
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TIM8_TRG_COM_TIM14_IRQn,
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM15
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#ifdef STM32L4
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TIM1_BRK_TIM15_IRQn,
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#else
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TIM15_IRQn,
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#endif
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM16
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#ifdef STM32L4
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TIM1_UP_TIM16_IRQn,
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#else
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TIM16_IRQn,
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#endif
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#else
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NULL_IRQ,
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#endif
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#ifdef TIM17
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#ifdef STM32L4
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TIM1_TRG_COM_TIM17_IRQn
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#else
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TIM17_IRQn,
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#endif
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#else
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NULL_IRQ,
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#endif
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};
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// Get the frequency (in Hz) of the source clock for the given timer.
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//
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// From STM ref manual: DM00031020 Rev 19, section 7.2, page 217:
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//
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// The timer clock frequencies for STM32F405xx/07xx and STM32F415xx/17xx are
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// automatically set by hardware. There are two cases:
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// 1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
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// that of the APB domain to which the timers are connected.
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// 2. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the
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// timers are connected.
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// From STM ref manual: DM00031020 Rev 19, section 6.2, page 153:
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//
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// The timer clock frequencies for STM32F42xxx and STM32F43xxx are automatically set by
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// hardware. There are two cases depending on the value of TIMPRE bit in RCC_CFGR [sic - should be RCC_DKCFGR]
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// register:
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// * If TIMPRE bit in RCC_DKCFGR register is reset:
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// If the APB prescaler is configured to a division factor of 1, the timer clock frequencies
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// (TIMxCLK) are set to PCLKx. Otherwise, the timer clock frequencies are twice the
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// frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.
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// * If TIMPRE bit in RCC_DKCFGR register is set:
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// If the APB prescaler is configured to a division factor of 1, 2 or 4, the timer clock
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// frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four
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// times the frequency of the APB domain to which the timers are connected: TIMxCLK = 4xPCLKx.
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uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef *timer) {
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// The timer index starts at 0, but the timer numbers start at TIM1.
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size_t tim_id = stm_peripherals_timer_get_index(timer) + 1;
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uint32_t source, clk_div;
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if (tim_id == 1 || (8 <= tim_id && tim_id <= 11)) {
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// TIM{1,8,9,10,11} are on APB2
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source = HAL_RCC_GetPCLK2Freq();
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// 0b0xx means not divided; 0b100 is divide by 2; 0b101 by 4; 0b110 by 8; 0b111 by 16.
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clk_div = (RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos;
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} else {
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// TIM{2,3,4,5,6,7,12,13,14} are on APB1
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source = HAL_RCC_GetPCLK1Freq();
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// 0b0xx means not divided; 0b100 is divide by 2; 0b101 by 4; 0b110 by 8; 0b111 by 16.
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clk_div = (RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos;
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}
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// Only some STM32's have TIMPRE.
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#if defined(RCC_CFGR_TIMPRE)
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uint32_t timpre = RCC->DCKCFGR & RCC_CFGR_TIMPRE;
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if (timpre == 0) {
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if (clk_div >= 0b100) {
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source *= 2;
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}
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} else {
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if (clk_div > 0b101) {
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source *= 4;
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} else {
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source = HAL_RCC_GetHCLKFreq();
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}
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}
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#else
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if (clk_div >= 0b100) {
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source *= 2;
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}
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#endif
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return source;
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}
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size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef *instance) {
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size_t tim_id = stm_peripherals_timer_get_index(instance);
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return irq_map[tim_id];
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}
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void timers_reset(void) {
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uint16_t never_reset_mask = 0x00;
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for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) {
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if (!stm_timer_never_reset[i]) {
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stm_timer_reserved[i] = false;
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} else {
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never_reset_mask |= 1 << i;
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}
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}
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tim_clock_disable(ALL_CLOCKS & ~(never_reset_mask));
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}
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TIM_TypeDef *stm_peripherals_find_timer(void) {
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// Check for timers on pins outside the package size
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for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) {
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bool timer_in_package = false;
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// Find each timer instance on the given bank
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for (size_t j = 0; j < MP_ARRAY_SIZE(mcu_tim_pin_list); j++) {
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// If a pin is claimed, we skip it
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if ((mcu_tim_pin_list[j].tim_index == i)
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&& (common_hal_mcu_pin_is_free(mcu_tim_pin_list[j].pin) == true)) {
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// Search whether any pins in the package array match it
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for (size_t k = 0; k < mcu_pin_globals.map.alloc; k++) {
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if ((mcu_tim_pin_list[j].pin == (mcu_pin_obj_t *)(mcu_pin_globals.map.table[k].value))) {
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timer_in_package = true;
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}
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}
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}
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}
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// If no results are found, no unclaimed pins with this timer are in this package,
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// and it is safe to pick
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if (timer_in_package == false && mcu_tim_banks[i] != NULL) {
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return mcu_tim_banks[i];
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}
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}
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// TODO: secondary search for timers outside the pins in the board profile
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// Work backwards - higher index timers have fewer pin allocations
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for (size_t i = (MP_ARRAY_SIZE(mcu_tim_banks) - 1); i >= 0; i--) {
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if ((!stm_timer_reserved[i]) && (mcu_tim_banks[i] != NULL)) {
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return mcu_tim_banks[i];
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}
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}
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mp_raise_RuntimeError(MP_ERROR_TEXT("All timers in use"));
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return NULL;
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}
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void stm_peripherals_timer_preinit(TIM_TypeDef *instance, uint8_t prio, void (*callback)(void)) {
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size_t tim_idx = stm_peripherals_timer_get_index(instance);
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stm_timer_callback[tim_idx] = callback;
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tim_clock_enable(1 << tim_idx);
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HAL_NVIC_SetPriority(irq_map[tim_idx], prio, 0);
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HAL_NVIC_EnableIRQ(irq_map[tim_idx]);
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}
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void stm_peripherals_timer_reserve(TIM_TypeDef *instance) {
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size_t tim_idx = stm_peripherals_timer_get_index(instance);
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stm_timer_reserved[tim_idx] = true;
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}
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void stm_peripherals_timer_set_callback(void (*callback)(void), TIM_TypeDef *timer) {
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stm_timer_callback[stm_peripherals_timer_get_index(timer)] = callback;
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}
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void stm_peripherals_timer_free(TIM_TypeDef *instance) {
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size_t tim_idx = stm_peripherals_timer_get_index(instance);
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HAL_NVIC_DisableIRQ(irq_map[tim_idx]);
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stm_timer_callback[tim_idx] = NULL;
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tim_clock_disable(1 << tim_idx);
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stm_timer_reserved[tim_idx] = false;
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stm_timer_never_reset[tim_idx] = false;
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}
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void stm_peripherals_timer_never_reset(TIM_TypeDef *instance) {
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size_t tim_idx = stm_peripherals_timer_get_index(instance);
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stm_timer_never_reset[tim_idx] = true;
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}
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void stm_peripherals_timer_reset_ok(TIM_TypeDef *instance) {
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size_t tim_idx = stm_peripherals_timer_get_index(instance);
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stm_timer_never_reset[tim_idx] = false;
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}
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bool stm_peripherals_timer_is_never_reset(TIM_TypeDef *instance) {
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size_t tim_idx = stm_peripherals_timer_get_index(instance);
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return stm_timer_never_reset[tim_idx];
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}
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bool stm_peripherals_timer_is_reserved(TIM_TypeDef *instance) {
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size_t tim_idx = stm_peripherals_timer_get_index(instance);
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return stm_timer_reserved[tim_idx];
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}
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// Note this returns a timer index starting at zero, corresponding to TIM1.
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size_t stm_peripherals_timer_get_index(TIM_TypeDef *instance) {
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for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) {
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if (instance == mcu_tim_banks[i]) {
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return i;
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}
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}
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return ~(size_t)0;
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}
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void tim_clock_enable(uint16_t mask) {
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#ifdef TIM1
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if (mask & (1 << 0)) {
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__HAL_RCC_TIM1_CLK_ENABLE();
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}
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#endif
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#ifdef TIM2
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if (mask & (1 << 1)) {
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__HAL_RCC_TIM2_CLK_ENABLE();
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}
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#endif
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#ifdef TIM3
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if (mask & (1 << 2)) {
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__HAL_RCC_TIM3_CLK_ENABLE();
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}
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#endif
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#ifdef TIM4
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if (mask & (1 << 3)) {
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__HAL_RCC_TIM4_CLK_ENABLE();
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}
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#endif
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#ifdef TIM5
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if (mask & (1 << 4)) {
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__HAL_RCC_TIM5_CLK_ENABLE();
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}
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#endif
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// 6 and 7 are reserved ADC timers
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#ifdef TIM8
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if (mask & (1 << 7)) {
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__HAL_RCC_TIM8_CLK_ENABLE();
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}
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#endif
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#ifdef TIM9
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if (mask & (1 << 8)) {
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__HAL_RCC_TIM9_CLK_ENABLE();
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}
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#endif
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#ifdef TIM10
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if (mask & (1 << 9)) {
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__HAL_RCC_TIM10_CLK_ENABLE();
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}
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#endif
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#ifdef TIM11
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if (mask & (1 << 10)) {
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__HAL_RCC_TIM11_CLK_ENABLE();
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}
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#endif
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#ifdef TIM12
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if (mask & (1 << 11)) {
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__HAL_RCC_TIM12_CLK_ENABLE();
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}
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#endif
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#ifdef TIM13
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if (mask & (1 << 12)) {
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__HAL_RCC_TIM13_CLK_ENABLE();
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}
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#endif
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#ifdef TIM14
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if (mask & (1 << 13)) {
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__HAL_RCC_TIM14_CLK_ENABLE();
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}
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#endif
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}
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void tim_clock_disable(uint16_t mask) {
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#ifdef TIM1
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if (mask & (1 << 0)) {
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__HAL_RCC_TIM1_CLK_DISABLE();
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}
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#endif
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#ifdef TIM2
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if (mask & (1 << 1)) {
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__HAL_RCC_TIM2_CLK_DISABLE();
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}
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#endif
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#ifdef TIM3
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if (mask & (1 << 2)) {
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__HAL_RCC_TIM3_CLK_DISABLE();
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}
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#endif
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#ifdef TIM4
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if (mask & (1 << 3)) {
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__HAL_RCC_TIM4_CLK_DISABLE();
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}
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#endif
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#ifdef TIM5
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if (mask & (1 << 4)) {
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__HAL_RCC_TIM5_CLK_DISABLE();
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}
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#endif
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// 6 and 7 are reserved ADC timers
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#ifdef TIM8
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if (mask & (1 << 7)) {
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__HAL_RCC_TIM8_CLK_DISABLE();
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}
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#endif
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#ifdef TIM9
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if (mask & (1 << 8)) {
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__HAL_RCC_TIM9_CLK_DISABLE();
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}
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#endif
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#ifdef TIM10
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if (mask & (1 << 9)) {
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__HAL_RCC_TIM10_CLK_DISABLE();
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}
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#endif
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#ifdef TIM11
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if (mask & (1 << 10)) {
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__HAL_RCC_TIM11_CLK_DISABLE();
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}
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#endif
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#ifdef TIM12
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if (mask & (1 << 11)) {
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__HAL_RCC_TIM12_CLK_DISABLE();
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}
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#endif
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#ifdef TIM13
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if (mask & (1 << 12)) {
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__HAL_RCC_TIM13_CLK_DISABLE();
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}
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#endif
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#ifdef TIM14
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if (mask & (1 << 13)) {
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__HAL_RCC_TIM14_CLK_DISABLE();
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}
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#endif
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}
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STATIC void callback_router(size_t index) {
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if (stm_timer_callback[index - 1]) {
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(*stm_timer_callback[index - 1])();
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}
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}
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void TIM1_CC_IRQHandler(void) { // Advanced timer
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callback_router(1);
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}
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void TIM2_IRQHandler(void) {
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callback_router(2);
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}
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void TIM3_IRQHandler(void) {
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callback_router(3);
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}
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void TIM4_IRQHandler(void) {
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callback_router(4);
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}
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void TIM5_IRQHandler(void) {
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callback_router(5);
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}
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void TIM6_DAC_IRQHandler(void) { // Basic timer (DAC)
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callback_router(6);
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}
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void TIM7_IRQHandler(void) { // Basic timer
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callback_router(7);
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}
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void TIM8_CC_IRQHandler(void) { // Advanced timer
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callback_router(8);
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}
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// Advanced timer interrupts are currently unused.
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void TIM1_BRK_TIM9_IRQHandler(void) {
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callback_router(9);
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}
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void TIM1_UP_TIM10_IRQHandler(void) {
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callback_router(10);
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}
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void TIM1_TRG_COM_TIM11_IRQHandler(void) {
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callback_router(11);
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}
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void TIM8_BRK_TIM12_IRQHandler(void) {
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callback_router(12);
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}
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void TIM8_UP_TIM13_IRQHandler(void) {
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callback_router(13);
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}
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void TIM8_TRG_COM_TIM14_IRQHandler(void) {
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callback_router(14);
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}
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#if (CPY_STM32H7)
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void TIM15_IRQHandler(void) {
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callback_router(15);
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||
}
|
||
|
||
void TIM16_IRQHandler(void) {
|
||
callback_router(16);
|
||
}
|
||
|
||
void TIM17_IRQHandler(void) {
|
||
callback_router(17);
|
||
}
|
||
#endif
|
||
|
||
#endif
|