/** ****************************************************************************** * @file stm32l476xx.h * @author MCD Application Team * @version V1.0.3 * @date 29-January-2016 * @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32l476xx * @{ */ #ifndef __STM32L476xx_H #define __STM32L476xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /*!< FPU present */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32L4XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum { /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ DFSDM3_IRQn = 42, /*!< SD Filter 3 global Interrupt */ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ FMC_IRQn = 48, /*!< FMC global Interrupt */ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ DFSDM0_IRQn = 61, /*!< SD Filter 0 global Interrupt */ DFSDM1_IRQn = 62, /*!< SD Filter 1 global Interrupt */ DFSDM2_IRQn = 63, /*!< SD Filter 2 global Interrupt */ COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ LCD_IRQn = 78, /*!< LCD global interrupt */ RNG_IRQn = 80, /*!< RNG global interrupt */ FPU_IRQn = 81 /*!< FPU global interrupt */ } IRQn_Type; /** * @} */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_stm32l4xx.h" #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved, 0x1C */ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x2C */ __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ uint32_t RESERVED3; /*!< Reserved, 0x44 */ uint32_t RESERVED4; /*!< Reserved, 0x48 */ __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ uint32_t RESERVED9; /*!< Reserved, 0x0AC */ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */ } ADC_Common_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ __IO uint32_t TDLR; /*!< CAN mailbox data low register */ __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ } COMP_TypeDef; typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ } COMP_Common_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ } DAC_TypeDef; /** * @brief DFSDM module registers */ typedef struct { __IO uint32_t CR1; /*!< DFSDM control register1, Address offset: 0x100 */ __IO uint32_t CR2; /*!< DFSDM control register2, Address offset: 0x104 */ __IO uint32_t ISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ __IO uint32_t ICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ __IO uint32_t JCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ __IO uint32_t FCR; /*!< DFSDM filter control register, Address offset: 0x114 */ __IO uint32_t JDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ __IO uint32_t RDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ __IO uint32_t AWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ __IO uint32_t AWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ __IO uint32_t AWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ __IO uint32_t AWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ __IO uint32_t EXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ __IO uint32_t EXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ __IO uint32_t CNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ } DFSDM_Filter_TypeDef; /** * @brief DFSDM channel configuration registers */ typedef struct { __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ __IO uint32_t AWSCDR; /*!< DFSDM channel analog watchdog and short circuit detector register, Address offset: 0x08 */ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ } DFSDM_Channel_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; typedef struct { __IO uint32_t CSELR; /*!< DMA channel selection register */ } DMA_Request_TypeDef; /* Legacy define */ #define DMA_request_TypeDef DMA_Request_TypeDef /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ } EXTI_TypeDef; /** * @brief Firewall */ typedef struct { __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ } FIREWALL_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ } FLASH_TypeDef; /** * @brief Flexible Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ } FMC_Bank1_TypeDef; /** * @brief Flexible Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; /** * @brief Flexible Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ } FMC_Bank3_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */ } GPIO_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ } IWDG_TypeDef; /** * @brief LCD */ typedef struct { __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ } LCD_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ } LPTIM_TypeDef; /** * @brief Operational Amplifier (OPAMP) */ typedef struct { __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ } OPAMP_TypeDef; typedef struct { __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ } OPAMP_Common_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ } PWR_TypeDef; /** * @brief QUAD Serial Peripheral Interface */ typedef struct { __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ } QUADSPI_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */ __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ uint32_t reserved; /*!< Reserved */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; /** * @brief Serial Audio Interface */ typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ } SAI_TypeDef; typedef struct { __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; /** * @brief Secure digital input/output Interface */ typedef struct { __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ } SDMMC_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; /** * @brief Single Wire Protocol Master Interface SPWMI */ typedef struct { __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ uint32_t RESERVED1; /*!< Reserved, 0x08 */ __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ } SWPMI_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ } SYSCFG_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ } TIM_TypeDef; /** * @brief Touch Sensing Controller (TSC) */ typedef struct { __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ } TSC_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ uint16_t RESERVED2; /*!< Reserved, 0x12 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ uint16_t RESERVED3; /*!< Reserved, 0x1A */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ uint16_t RESERVED4; /*!< Reserved, 0x26 */ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ uint16_t RESERVED5; /*!< Reserved, 0x2A */ } USART_TypeDef; /** * @brief VREFBUF */ typedef struct { __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ } VREFBUF_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; /** * @brief USB_OTG_Core_register */ typedef struct { __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ uint32_t Reserved30[2]; /* Reserved 030h*/ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ __IO uint32_t CID; /* User ID Register 03Ch*/ uint32_t Reserved5[3]; /* Reserved 040h-048h*/ __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ uint32_t Reserved6; /* Reserved 050h*/ __IO uint32_t GLPMCFG; /* LPM Register 054h*/ __IO uint32_t GPWRDN; /* Power Down Register 058h*/ __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; /** * @brief USB_OTG_device_Registers */ typedef struct { __IO uint32_t DCFG; /* dev Configuration Register 800h*/ __IO uint32_t DCTL; /* dev Control Register 804h*/ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ uint32_t Reserved0C; /* Reserved 80Ch*/ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ uint32_t Reserved20; /* Reserved 820h*/ uint32_t Reserved9; /* Reserved 824h*/ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ __IO uint32_t DTHRCTL; /* dev thr 830h*/ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ uint32_t Reserved40; /* dedicated EP mask 840h*/ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ } USB_OTG_DeviceTypeDef; /** * @brief USB_OTG_IN_Endpoint-Specific_Register */ typedef struct { __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ } USB_OTG_INEndpointTypeDef; /** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ typedef struct { __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ } USB_OTG_OUTEndpointTypeDef; /** * @brief USB_OTG_Host_Mode_Register_Structures */ typedef struct { __IO uint32_t HCFG; /* Host Configuration Register 400h*/ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ uint32_t Reserved40C; /* Reserved 40Ch*/ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ } USB_OTG_HostTypeDef; /** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct { __IO uint32_t HCCHAR; __IO uint32_t HCSPLT; __IO uint32_t HCINT; __IO uint32_t HCINTMSK; __IO uint32_t HCTSIZ; __IO uint32_t HCDMA; uint32_t Reserved[2]; } USB_OTG_HostChannelTypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address*/ #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address*/ #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE #define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */ #define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) #define FMC_BANK3 (FMC_BASE + 0x20000000U) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) #define LCD_BASE (APB1PERIPH_BASE + 0x2400U) #define RTC_BASE (APB1PERIPH_BASE + 0x2800U) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) #define USART2_BASE (APB1PERIPH_BASE + 0x4400U) #define USART3_BASE (APB1PERIPH_BASE + 0x4800U) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) #define UART5_BASE (APB1PERIPH_BASE + 0x5000U) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) #define PWR_BASE (APB1PERIPH_BASE + 0x7000U) #define DAC_BASE (APB1PERIPH_BASE + 0x7400U) #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) /*!< APB2 peripherals */ #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) #define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) #define USART1_BASE (APB2PERIPH_BASE + 0x3800U) #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) #define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) #define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) #define DFSDM_BASE (APB2PERIPH_BASE + 0x6000U) #define DFSDM_Channel0_BASE (DFSDM_BASE + 0x00) #define DFSDM_Channel1_BASE (DFSDM_BASE + 0x20) #define DFSDM_Channel2_BASE (DFSDM_BASE + 0x40) #define DFSDM_Channel3_BASE (DFSDM_BASE + 0x60) #define DFSDM_Channel4_BASE (DFSDM_BASE + 0x80) #define DFSDM_Channel5_BASE (DFSDM_BASE + 0xA0) #define DFSDM_Channel6_BASE (DFSDM_BASE + 0xC0) #define DFSDM_Channel7_BASE (DFSDM_BASE + 0xE0) #define DFSDM_Filter0_BASE (DFSDM_BASE + 0x100) #define DFSDM_Filter1_BASE (DFSDM_BASE + 0x180) #define DFSDM_Filter2_BASE (DFSDM_BASE + 0x200) #define DFSDM_Filter3_BASE (DFSDM_BASE + 0x280) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) /*!< AHB2 peripherals */ #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< USB registers base address */ #define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) #define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) #define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) #define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) #define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) #define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) #define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) #define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) #define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define LCD ((LCD_TypeDef *) LCD_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CAN ((CAN_TypeDef *) CAN1_BASE) #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC1_BASE) #define DAC1 ((DAC_TypeDef *) DAC1_BASE) #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) #define COMP1 ((COMP_TypeDef *) COMP1_BASE) #define COMP2 ((COMP_TypeDef *) COMP2_BASE) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) #define SAI2 ((SAI_TypeDef *) SAI2_BASE) #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) #define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE) #define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE) #define DFSDM_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE) #define DFSDM_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE) #define DFSDM_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE) #define DFSDM_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE) #define DFSDM_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE) #define DFSDM_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE) #define DFSDM_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE) #define DFSDM_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE) #define DFSDM_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE) #define DFSDM_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define TSC ((TSC_TypeDef *) TSC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE) #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE) #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32L4 family) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC ready flag */ #define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ #define ADC_IER_ADRDY (ADC_IER_ADRDYIE) #define ADC_IER_EOSMP (ADC_IER_EOSMPIE) #define ADC_IER_EOC (ADC_IER_EOCIE) #define ADC_IER_EOS (ADC_IER_EOSIE) #define ADC_IER_OVR (ADC_IER_OVRIE) #define ADC_IER_JEOC (ADC_IER_JEOCIE) #define ADC_IER_JEOS (ADC_IER_JEOSIE) #define ADC_IER_AWD1 (ADC_IER_AWD1IE) #define ADC_IER_AWD2 (ADC_IER_AWD2IE) #define ADC_IER_AWD3 (ADC_IER_AWD3IE) #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable */ #define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable */ #define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART ((uint32_t)0x00000008U) /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP ((uint32_t)0x00000020U) /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD ((uint32_t)0x20000000U) /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF ((uint32_t)0x40000000U) /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN ((uint32_t)0x00000001U) /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG ((uint32_t)0x00000002U) /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES ((uint32_t)0x00000018U) /*!< ADC data resolution */ #define ADC_CFGR_RES_0 ((uint32_t)0x00000008U) /*!< bit 0 */ #define ADC_CFGR_RES_1 ((uint32_t)0x00000010U) /*!< bit 1 */ #define ADC_CFGR_ALIGN ((uint32_t)0x00000020U) /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0U) /*!< ADC group regular external trigger source */ #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040U) /*!< bit 0 */ #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080U) /*!< bit 1 */ #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100U) /*!< bit 2 */ #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200U) /*!< bit 3 */ #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00U) /*!< ADC group regular external trigger polarity */ #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400U) /*!< bit 0 */ #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800U) /*!< bit 1 */ #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000U) /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT ((uint32_t)0x00002000U) /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000U) /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN ((uint32_t)0x00010000U) /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000U) /*!< ADC Discontinuous mode channel count */ #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000U) /*!< bit 0 */ #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000U) /*!< bit 1 */ #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000U) /*!< bit 2 */ #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000U) /*!< ADC Discontinuous mode on injected channels */ #define ADC_CFGR_JQM ((uint32_t)0x00200000U) /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO ((uint32_t)0x02000000U) /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000U) /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */ #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */ #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */ #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */ #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */ #define ADC_CFGR_JQDIS ((uint32_t)0x80000000U) /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE ((uint32_t)0x00000001U) /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE ((uint32_t)0x00000002U) /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< bit 0 */ #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< bit 1 */ #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< bit 2 */ #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< bit 0 */ #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< bit 1 */ #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< bit 2 */ #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< bit 3 */ #define ADC_CFGR2_TROVS ((uint32_t)0x00000200U) /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM ((uint32_t)0x00000400U) /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008U) /*!< bit 0 */ #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010U) /*!< bit 1 */ #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020U) /*!< bit 2 */ #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040U) /*!< bit 0 */ #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080U) /*!< bit 1 */ #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100U) /*!< bit 2 */ #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200U) /*!< bit 0 */ #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400U) /*!< bit 1 */ #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800U) /*!< bit 2 */ #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000U) /*!< bit 0 */ #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000U) /*!< bit 1 */ #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000U) /*!< bit 2 */ #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000U) /*!< bit 0 */ #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000U) /*!< bit 1 */ #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000U) /*!< bit 2 */ #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000U) /*!< bit 0 */ #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000U) /*!< bit 1 */ #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000U) /*!< bit 2 */ #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000U) /*!< bit 0 */ #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000U) /*!< bit 1 */ #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000U) /*!< bit 2 */ #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000U) /*!< bit 0 */ #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000U) /*!< bit 1 */ #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000U) /*!< bit 2 */ #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000U) /*!< bit 0 */ #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000U) /*!< bit 1 */ #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000U) /*!< bit 2 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< bit 0 */ #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< bit 1 */ #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< bit 2 */ #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< bit 0 */ #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< bit 1 */ #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< bit 2 */ #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< bit 0 */ #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< bit 1 */ #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< bit 2 */ #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< bit 0 */ #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< bit 1 */ #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< bit 2 */ #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< bit 0 */ #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< bit 1 */ #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< bit 2 */ #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< bit 0 */ #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< bit 1 */ #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< bit 2 */ #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< bit 0 */ #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< bit 1 */ #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< bit 2 */ #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< bit 0 */ #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< bit 1 */ #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< bit 2 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1 ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR1_LT1_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_TR1_LT1_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_TR1_LT1_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_TR1_LT1_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_TR1_LT1_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_TR1_LT1_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_TR1_LT1_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_TR1_LT1_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_TR1_LT1_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_TR1_LT1_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_TR1_LT1_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_TR1_LT1_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000U) /*!< ADC Analog watchdog 1 threshold high */ #define ADC_TR1_HT1_0 ((uint32_t)0x00010000U) /*!< bit 0 */ #define ADC_TR1_HT1_1 ((uint32_t)0x00020000U) /*!< bit 1 */ #define ADC_TR1_HT1_2 ((uint32_t)0x00040000U) /*!< bit 2 */ #define ADC_TR1_HT1_3 ((uint32_t)0x00080000U) /*!< bit 3 */ #define ADC_TR1_HT1_4 ((uint32_t)0x00100000U) /*!< bit 4 */ #define ADC_TR1_HT1_5 ((uint32_t)0x00200000U) /*!< bit 5 */ #define ADC_TR1_HT1_6 ((uint32_t)0x00400000U) /*!< bit 6 */ #define ADC_TR1_HT1_7 ((uint32_t)0x00800000U) /*!< bit 7 */ #define ADC_TR1_HT1_8 ((uint32_t)0x01000000U) /*!< bit 8 */ #define ADC_TR1_HT1_9 ((uint32_t)0x02000000U) /*!< bit 9 */ #define ADC_TR1_HT1_10 ((uint32_t)0x04000000U) /*!< bit 10 */ #define ADC_TR1_HT1_11 ((uint32_t)0x08000000U) /*!< bit 11 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 2 threshold low */ #define ADC_TR2_LT2_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_TR2_LT2_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_TR2_LT2_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_TR2_LT2_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_TR2_LT2_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_TR2_LT2_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_TR2_LT2_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_TR2_LT2_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_TR2_HT2 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 2 threshold high */ #define ADC_TR2_HT2_0 ((uint32_t)0x00010000U) /*!< bit 0 */ #define ADC_TR2_HT2_1 ((uint32_t)0x00020000U) /*!< bit 1 */ #define ADC_TR2_HT2_2 ((uint32_t)0x00040000U) /*!< bit 2 */ #define ADC_TR2_HT2_3 ((uint32_t)0x00080000U) /*!< bit 3 */ #define ADC_TR2_HT2_4 ((uint32_t)0x00100000U) /*!< bit 4 */ #define ADC_TR2_HT2_5 ((uint32_t)0x00200000U) /*!< bit 5 */ #define ADC_TR2_HT2_6 ((uint32_t)0x00400000U) /*!< bit 6 */ #define ADC_TR2_HT2_7 ((uint32_t)0x00800000U) /*!< bit 7 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 3 threshold low */ #define ADC_TR3_LT3_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_TR3_LT3_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_TR3_LT3_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_TR3_LT3_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_TR3_LT3_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_TR3_LT3_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_TR3_LT3_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_TR3_LT3_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_TR3_HT3 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 3 threshold high */ #define ADC_TR3_HT3_0 ((uint32_t)0x00010000U) /*!< bit 0 */ #define ADC_TR3_HT3_1 ((uint32_t)0x00020000U) /*!< bit 1 */ #define ADC_TR3_HT3_2 ((uint32_t)0x00040000U) /*!< bit 2 */ #define ADC_TR3_HT3_3 ((uint32_t)0x00080000U) /*!< bit 3 */ #define ADC_TR3_HT3_4 ((uint32_t)0x00100000U) /*!< bit 4 */ #define ADC_TR3_HT3_5 ((uint32_t)0x00200000U) /*!< bit 5 */ #define ADC_TR3_HT3_6 ((uint32_t)0x00400000U) /*!< bit 6 */ #define ADC_TR3_HT3_7 ((uint32_t)0x00800000U) /*!< bit 7 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L ((uint32_t)0x0000000FU) /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_SQR1_L_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_SQR1_L_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_SQR1_L_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040U) /*!< bit 0 */ #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080U) /*!< bit 1 */ #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100U) /*!< bit 2 */ #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200U) /*!< bit 3 */ #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400U) /*!< bit 4 */ #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000U) /*!< bit 0 */ #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000U) /*!< bit 1 */ #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000U) /*!< bit 2 */ #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000U) /*!< bit 3 */ #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000U) /*!< bit 4 */ #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000U) /*!< bit 0 */ #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000U) /*!< bit 1 */ #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000U) /*!< bit 2 */ #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000U) /*!< bit 3 */ #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000U) /*!< bit 4 */ #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000U) /*!< bit 0 */ #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000U) /*!< bit 1 */ #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000U) /*!< bit 2 */ #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000U) /*!< bit 3 */ #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000U) /*!< bit 4 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040U) /*!< bit 0 */ #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080U) /*!< bit 1 */ #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100U) /*!< bit 2 */ #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200U) /*!< bit 3 */ #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400U) /*!< bit 4 */ #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000U) /*!< bit 0 */ #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000U) /*!< bit 1 */ #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000U) /*!< bit 2 */ #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000U) /*!< bit 3 */ #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000U) /*!< bit 4 */ #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000U) /*!< bit 0 */ #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000U) /*!< bit 1 */ #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000U) /*!< bit 2 */ #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000U) /*!< bit 3 */ #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000U) /*!< bit 4 */ #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000U) /*!< bit 0 */ #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000U) /*!< bit 1 */ #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000U) /*!< bit 2 */ #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000U) /*!< bit 3 */ #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000U) /*!< bit 4 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040U) /*!< bit 0 */ #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080U) /*!< bit 1 */ #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100U) /*!< bit 2 */ #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200U) /*!< bit 3 */ #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400U) /*!< bit 4 */ #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000U) /*!< bit 0 */ #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000U) /*!< bit 1 */ #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000U) /*!< bit 2 */ #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000U) /*!< bit 3 */ #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000U) /*!< bit 4 */ #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000U) /*!< bit 0 */ #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000U) /*!< bit 1 */ #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000U) /*!< bit 2 */ #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000U) /*!< bit 3 */ #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000U) /*!< bit 4 */ #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000U) /*!< bit 0 */ #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000U) /*!< bit 1 */ #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000U) /*!< bit 2 */ #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000U) /*!< bit 3 */ #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000U) /*!< bit 4 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010U) /*!<5 bit 4 */ #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040U) /*!< bit 0 */ #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080U) /*!< bit 1 */ #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100U) /*!< bit 2 */ #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200U) /*!< bit 3 */ #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400U) /*!< bit 4 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */ #define ADC_DR_RDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_DR_RDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_DR_RDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_DR_RDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_DR_RDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_DR_RDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_DR_RDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_DR_RDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_DR_RDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_DR_RDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_DR_RDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_DR_RDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_DR_RDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */ #define ADC_DR_RDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */ #define ADC_DR_RDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */ #define ADC_DR_RDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL ((uint32_t)0x00000003U) /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_JSQR_JL_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003CU) /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004U) /*!< bit 0 */ #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008U) /*!< bit 1 */ #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010U) /*!< bit 2 */ #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020U) /*!< bit 3 */ #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0U) /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040U) /*!< bit 0 */ #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080U) /*!< bit 1 */ #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00U) /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100U) /*!< bit 0 */ #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200U) /*!< bit 1 */ #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400U) /*!< bit 2 */ #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800U) /*!< bit 3 */ #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000U) /*!< bit 4 */ #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000U) /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000U) /*!< bit 0 */ #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000U) /*!< bit 1 */ #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000U) /*!< bit 2 */ #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000U) /*!< bit 3 */ #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000U) /*!< bit 4 */ #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000U) /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000U) /*!< bit 0 */ #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000U) /*!< bit 1 */ #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000U) /*!< bit 2 */ #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000U) /*!< bit 3 */ #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000U) /*!< bit 4 */ #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000U) /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000U) /*!< bit 0 */ #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000U) /*!< bit 1 */ #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000U) /*!< bit 2 */ #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000U) /*!< bit 3 */ #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000U) /*!< bit 4 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC offset number 1 offset level */ #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 1 channel selection */ #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */ #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */ #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */ #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */ #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */ #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000U) /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC offset number 2 offset level */ #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 2 channel selection */ #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */ #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */ #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */ #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */ #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */ #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000U) /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC offset number 3 offset level */ #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 3 channel selection */ #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */ #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */ #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */ #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */ #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */ #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000U) /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC offset number 4 offset level */ #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 4 channel selection */ #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */ #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */ #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */ #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */ #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */ #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000U) /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */ #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */ #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */ #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */ #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */ #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */ #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */ #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */ #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */ #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */ #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */ #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */ #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */ #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */ #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */ #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */ #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 2 monitoring channel 0 */ #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 2 monitoring channel 1 */ #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 2 monitoring channel 2 */ #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 2 monitoring channel 3 */ #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 2 monitoring channel 4 */ #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 2 monitoring channel 5 */ #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 2 monitoring channel 6 */ #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 2 monitoring channel 7 */ #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 monitoring channel 8 */ #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 2 monitoring channel 9 */ #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 2 monitoring channel 10 */ #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 2 monitoring channel 11 */ #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 2 monitoring channel 12 */ #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 2 monitoring channel 13 */ #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 2 monitoring channel 14 */ #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 2 monitoring channel 15 */ #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 2 monitoring channel 16 */ #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 2 monitoring channel 17 */ #define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 2 monitoring channel 18 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 3 monitoring channel 0 */ #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 3 monitoring channel 1 */ #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 3 monitoring channel 2 */ #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 3 monitoring channel 3 */ #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 3 monitoring channel 4 */ #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 3 monitoring channel 5 */ #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 3 monitoring channel 6 */ #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 3 monitoring channel 7 */ #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 3 monitoring channel 8 */ #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 monitoring channel 9 */ #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 3 monitoring channel 10 */ #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 3 monitoring channel 11 */ #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 3 monitoring channel 12 */ #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 3 monitoring channel 13 */ #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 3 monitoring channel 14 */ #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 3 monitoring channel 15 */ #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 3 monitoring channel 16 */ #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 3 monitoring channel 17 */ #define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 3 monitoring channel 18 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFFU) /*!< ADC channel differential or single-ended mode */ #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000U) /*!< bit 12 */ #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000U) /*!< bit 13 */ #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000U) /*!< bit 14 */ #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000U) /*!< bit 15 */ #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000U) /*!< bit 16 */ #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000U) /*!< bit 17 */ #define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000U) /*!< bit 18 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007FU) /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000U) /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000U) /*!< bit 0 */ #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000U) /*!< bit 1 */ #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000U) /*!< bit 2 */ #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000U) /*!< bit 3 */ #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000U) /*!< bit 4 */ #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000U) /*!< bit 5 */ #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000U) /*!< bit 6 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST ((uint32_t)0x00000001U) /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST ((uint32_t)0x00000004U) /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST ((uint32_t)0x00000008U) /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST ((uint32_t)0x00000010U) /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST ((uint32_t)0x00000020U) /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST ((uint32_t)0x00000040U) /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST ((uint32_t)0x00000080U) /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST ((uint32_t)0x00000100U) /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST ((uint32_t)0x00000200U) /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST ((uint32_t)0x00000400U) /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV ((uint32_t)0x00010000U) /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV ((uint32_t)0x00020000U) /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV ((uint32_t)0x00040000U) /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV ((uint32_t)0x00080000U) /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV ((uint32_t)0x00100000U) /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV ((uint32_t)0x00200000U) /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV ((uint32_t)0x00400000U) /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV ((uint32_t)0x00800000U) /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV ((uint32_t)0x01000000U) /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV ((uint32_t)0x02000000U) /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV ((uint32_t)0x04000000U) /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL ((uint32_t)0x0000001FU) /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_CCR_DUAL_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_CCR_DUAL_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_CCR_DUAL_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_CCR_DUAL_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_CCR_DELAY ((uint32_t)0x00000F00U) /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100U) /*!< bit 0 */ #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200U) /*!< bit 1 */ #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400U) /*!< bit 2 */ #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800U) /*!< bit 3 */ #define ADC_CCR_DMACFG ((uint32_t)0x00002000U) /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA ((uint32_t)0x0000C000U) /*!< ADC multimode DMA transfer enable */ #define ADC_CCR_MDMA_0 ((uint32_t)0x00004000U) /*!< bit 0 */ #define ADC_CCR_MDMA_1 ((uint32_t)0x00008000U) /*!< bit 1 */ #define ADC_CCR_CKMODE ((uint32_t)0x00030000U) /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000U) /*!< bit 0 */ #define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000U) /*!< bit 1 */ #define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< bit 0 */ #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< bit 1 */ #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< bit 2 */ #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< bit 3 */ #define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN ((uint32_t)0x01000000U) /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST ((uint32_t)0x0000FFFFU) /*!< ADC multimode master group regular conversion data */ #define ADC_CDR_RDATA_MST_0 ((uint32_t)0x00000001U) /*!< bit 0 */ #define ADC_CDR_RDATA_MST_1 ((uint32_t)0x00000002U) /*!< bit 1 */ #define ADC_CDR_RDATA_MST_2 ((uint32_t)0x00000004U) /*!< bit 2 */ #define ADC_CDR_RDATA_MST_3 ((uint32_t)0x00000008U) /*!< bit 3 */ #define ADC_CDR_RDATA_MST_4 ((uint32_t)0x00000010U) /*!< bit 4 */ #define ADC_CDR_RDATA_MST_5 ((uint32_t)0x00000020U) /*!< bit 5 */ #define ADC_CDR_RDATA_MST_6 ((uint32_t)0x00000040U) /*!< bit 6 */ #define ADC_CDR_RDATA_MST_7 ((uint32_t)0x00000080U) /*!< bit 7 */ #define ADC_CDR_RDATA_MST_8 ((uint32_t)0x00000100U) /*!< bit 8 */ #define ADC_CDR_RDATA_MST_9 ((uint32_t)0x00000200U) /*!< bit 9 */ #define ADC_CDR_RDATA_MST_10 ((uint32_t)0x00000400U) /*!< bit 10 */ #define ADC_CDR_RDATA_MST_11 ((uint32_t)0x00000800U) /*!< bit 11 */ #define ADC_CDR_RDATA_MST_12 ((uint32_t)0x00001000U) /*!< bit 12 */ #define ADC_CDR_RDATA_MST_13 ((uint32_t)0x00002000U) /*!< bit 13 */ #define ADC_CDR_RDATA_MST_14 ((uint32_t)0x00004000U) /*!< bit 14 */ #define ADC_CDR_RDATA_MST_15 ((uint32_t)0x00008000U) /*!< bit 15 */ #define ADC_CDR_RDATA_SLV ((uint32_t)0xFFFF0000U) /*!< ADC multimode slave group regular conversion data */ #define ADC_CDR_RDATA_SLV_0 ((uint32_t)0x00010000U) /*!< bit 0 */ #define ADC_CDR_RDATA_SLV_1 ((uint32_t)0x00020000U) /*!< bit 1 */ #define ADC_CDR_RDATA_SLV_2 ((uint32_t)0x00040000U) /*!< bit 2 */ #define ADC_CDR_RDATA_SLV_3 ((uint32_t)0x00080000U) /*!< bit 3 */ #define ADC_CDR_RDATA_SLV_4 ((uint32_t)0x00100000U) /*!< bit 4 */ #define ADC_CDR_RDATA_SLV_5 ((uint32_t)0x00200000U) /*!< bit 5 */ #define ADC_CDR_RDATA_SLV_6 ((uint32_t)0x00400000U) /*!< bit 6 */ #define ADC_CDR_RDATA_SLV_7 ((uint32_t)0x00800000U) /*!< bit 7 */ #define ADC_CDR_RDATA_SLV_8 ((uint32_t)0x01000000U) /*!< bit 8 */ #define ADC_CDR_RDATA_SLV_9 ((uint32_t)0x02000000U) /*!< bit 9 */ #define ADC_CDR_RDATA_SLV_10 ((uint32_t)0x04000000U) /*!< bit 10 */ #define ADC_CDR_RDATA_SLV_11 ((uint32_t)0x08000000U) /*!< bit 11 */ #define ADC_CDR_RDATA_SLV_12 ((uint32_t)0x10000000U) /*!< bit 12 */ #define ADC_CDR_RDATA_SLV_13 ((uint32_t)0x20000000U) /*!< bit 13 */ #define ADC_CDR_RDATA_SLV_14 ((uint32_t)0x40000000U) /*!< bit 14 */ #define ADC_CDR_RDATA_SLV_15 ((uint32_t)0x80000000U) /*!< bit 15 */ /******************************************************************************/ /* */ /* Controller Area Network */ /* */ /******************************************************************************/ /*!*/ #define DAC_CR_CEN1 ((uint32_t)0x00004000U) /*!*/ #define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!*/ #define DAC_CR_CEN2 ((uint32_t)0x40000000U) /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!