By specifying rts=pin(x) and/or cts=Pin(x) in the constructor. The pad
numbers for the UART pins are fix in this case: TX must be at pad 0, RX at
pad 1, RTS at pad 2 and CTS at pad 3.
repr(uart) shows the pin names for rts and cts, if set. In case of a RX
overflow, the rx interrupt will be disabled instead of just discarding the
data. That allows RTS to act.
If RTS is inactive, still 2 bytes can be buffered in the FIFO.
Signed-off-by: robert-hh <robert@hammelrath.com>
With Crystal: set the crystal startup wait time to 1 second. It was 2
seconds before, and that seeemed too long.
With USB-Sync: scan for up to 1 second for the USB to be registered and
carry on with boot as soon as it it. Before, the code just waited for
500ms.
Side change: improve related comments.
Signed-off-by: robert-hh <robert@hammelrath.com>
These include ADC, DAC, I2C, SoftI2C, SPI, SoftI2C, PWM, UART, pulse. This
is useful for devices like the Adafruit Trinket series which have almost no
accessible GPIO pins.
Signed-off-by: robert-hh <robert@hammelrath.com>
If sockets were open when calling soft reset, gc_sweep_all() would try to
close them. In case of e.g. the NINA WiFi handler, connected through SPI,
spi_transfer() would be called for command exchange with the NINA module.
But at that time SerCom was already disabled.
Moving sercom_deinit_all() behind gc_sweep_all() solves this issue.
Signed-off-by: robert-hh <robert@hammelrath.com>
Such that they are easier to adapt. The maximum code size is set by:
MICROPY_HW_CODESIZE=xxxK
in mpconfigmcu.mk for the MCU family as default or in mpconfigboard.mk for
a specific board. Setting the maximum code size allows the loader to error
out if the code gets larger than the space dedicated for it.
Signed-off-by: robert-hh <robert@hammelrath.com>
Change UART clock source on S3/C3 so the UART can operate when CPU
frequency is below 80MHz. This allows the UART to remain operational when
using Dynamic Frequency Scaling (DFS).
Signed-off-by: Patrick Joy <patrick@joytech.com.au>
This commit enables the ULP for the S2 and S3 chips.
Note this is the FSM (Finite State Machine) ULP.
Signed-off-by: Patrick Joy <patrick@joytech.com.au>
Once all the firmware has been flashed and the final signatures checked,
mboot writes the "all good" byte into the header of the application. This
step uses the buffer firmware_head which, if unaligned in the build, fails
when cast to a uint64_t* in flash.c.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
These were incorrectly added in d995c010428420c7690d5cd59b9580c3f4f9649a.
The fix here includes the full differential ADC definitions.
Signed-off-by: brave ulysses <brave_ulysses@email.com>
