Commit Graph

8 Commits

Author SHA1 Message Date
Philipp Ebensberger
87f97e490c mimxrt/sdcard: Implement SDCard driver.
- Configures `PLL2->PFD0` with **198MHz** as base clock of
	`USDHCx` peripheral.
- Adds guards for SDCard related files via `MICROPY_PY_MACHINE_SDCARD`
- Adds creation of pin defines for SDCard to make-pins.py
- Adds new configuration option for SDCard peripheral pinout
        to mpconfigport.h
- Adds interrupt handling support instead of polling
- Adds support for `ADMA2` powered data transfer
- Configures SDCard to run in HS (high-speed mode) with **50MHz** only!

SDCard support is optional and requires `USDHC` peripheral.
Thus this driver is not available on `MIMXRT1010_EVK`.
SDCard support is enabled by setting `MICROPY_PY_MACHINE_SDCARD = 1`
in mpconfigboard.mk.

Signed-off-by: Philipp Ebensberger
2021-09-07 20:45:33 +02:00
robert-hh
98c5703027 mimxrt/machine_i2c: Add hardware-based machine.I2C to machine module.
It uses non-blocking transfer of data.  Advantage over SoftI2C:
- Higher data rate up to ~3 MHZ.
- Full protocol support.
2021-07-15 00:36:31 +10:00
robert-hh
f45412793e mimxrt/machine_spi: Add the SPI class to the machine module.
This class supports SPI bus controller mode, with blocking transfers.

SPI device numbers start at 0, to comply with the pinout of the Teensy
boards.  With the configured clock frequency the fastest baud rate is
33MHz.  For messages longer 16 bytes DMA is used.  The class uses the
existing framework with extmod/machine_spi.c.

Extended driver options:

- drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6.
  Since the pins used by the SPI are fixed, no Pin settings can be made.
  Thus the drive option is added allowing to control ringing and crosstalk
  on the connection.

- gap_ns=nnnnn is the time between sent data items in a frame given in ns.
  Default is 2 clock cycles.
2021-06-26 22:14:47 +10:00
robert-hh
7417c6ac91 mimxrt/machine_pin: Implement pin.irq() functionality. 2021-06-16 01:42:10 +10:00
robert-hh
689476c576 mimxrt/machine_uart: Add the UART class to the machine module.
The implementation uses the LPUARTx devices.  Up to 8 UARTs can be used,
given that the pins are accessible.  E.g. 8 on Teensy 4.1, 5 on
MIMXRT1020_EVK.

For Tennsy 4.0 and 4.1 the UART numbers are as printed on the pinout 1..N.
The MIMXRT10xx-EVK boards have only one UART named, which gets the number
1.  All other UART are assigned to different Pins:

MIMXRT1010-EVK:
    D0/D1   UART 1
    D6/D7   UART 2
    A0/D4   UART 3

MIMXRT1020-EVK:
    D0/D1   UART 1
    D6/D9   UART 2
    D10/D12 UART 3
    D14/D15 UART 4
    A0/A1   UART 5

MIMXRT1050-EVK, MIMXRT1060-EVK, MIMXRT1064-EVK:
    D0/D1   UART 1
    D7/D6   UART 2
    D8/D9   UART 3
    A1/A0   UART 4
2021-06-16 01:21:15 +10:00
Philipp Ebensberger
b8c65b174f mimxrt/machine_adc: Add the ADC class to the machine module.
This adds the machine.ADC class with the read_u16() method.  make-pins.py
and supporting files are updated to generate ADC information.
2021-06-04 00:51:58 +10:00
robert-hh
2f365d234e mimxrt/machine_rtc: Add the RTC class to the machine module.
Initial version, using the LP RTC clock.  It provides setting the date and
time with rtc.init() or rtc.datetime(), and reading the date and time with
rtc.datetime() or rtc.now().  The method weekday() reports the weekday of
the current date.  It starts with 0 for Monday.

The tuple order for datetime() and now() matches the CPython sequence:
(year, month, day, hour, minute, second, microsecond, TZ).  TZ is ignored
and reported as None.  Microsecond is provided at a best effort.

If a battery is not supplied, the default boot date/time is 1970/1/1 0:0:0.
With a battery, the clock continues to run even when the board is not
powered.  The clock is quite precise.  If not, using rtc.calibration() may
help.
2021-06-03 15:24:04 +10:00
robert-hh
4c407c790f mimxrt: Add the Timer class to the machine module.
It supports three hardware timer channels based on the PIT timers of the
MIMXRT MCU.  The timer id's are 0, 1 and 2.  On soft reboot all active
timers will be stopped via finalisers.
2021-06-02 00:33:13 +10:00