The existing qspi for stm32 implementation can only send a spi command with
exactly 0 or 2 data bytes. Certain spiflash chips (e.g. AT25SF321B) have
commands that only take a single data byte, and will ignore the command if
more than that is sent. This commit allows sending a command with a single
data byte.
Signed-off-by: Victor Rajewski <victor@allumeenergy.com.au>
This changes the signatures of QSPI write_cmd_data, write_cmd_addr_data and
read_cmd_qaddr_qdata so they return an error code. The softqspi and stm32
hardware qspi driver are updated to follow this new signature. Also the
spiflash driver is updated to use these new return values.
Signed-off-by: Damien George <damien@micropython.org>
With a SPI flash that has more than 16MB, 32-bit addressing is required
rather than the standard 24-bit. This commit adds support for 32-bit
addressing so that the SPI flash commands (read/write/erase) are selected
automatically depending on the size of the address being used at each
operation.
When going out of memory-mapped mode to do a control transfer to the QSPI
flash, the MPU settings must be changed to forbid access to the memory
mapped region. And any ongoing transfer (eg memory mapped continuous read)
must be aborted.
The Cortex-M7 CPU will do speculative loads from any memory location that
is not explicitly forbidden. This includes the QSPI memory-mapped region
starting at 0x90000000 and with size 256MiB. Speculative loads to this
QSPI region may 1) interfere with the QSPI peripheral registers (eg the
address register) if the QSPI is not in memory-mapped mode; 2) attempt to
access data outside the configured size of the QSPI flash when it is in
memory-mapped mode. Both of these scenarios will lead to issues with the
QSPI peripheral (eg Cortex bus lock up in scenario 2).
To prevent such speculative loads from interfering with the peripheral the
MPU is configured in this commit to restrict access to the QSPI mapped
region: when not memory mapped the entire region is forbidden; when memory
mapped only accesses to the valid flash size are permitted.
Prior to this patch the QSPI driver assumed that the length of all data
reads and writes was a multiple of 4. This patch allows any length. Reads
are optimised for speed by using 32-bit transfers when possible, but writes
always use a byte transfer because they only use a single data IO line and
are relatively slow.
Taking the address assumes that the pin is an object (eg a struct), but it
could be a literal (eg an int). Not taking the address makes this driver
more general for other uses.
genhdr/pins.h is an internal header file that defines all of the pin
objects and it's cleaner to have pin.h include it (where the struct's for
these objects are defined) rather than an explicit include by every user.
