Ensures consistent behaviour and resolves the D-Cache bug (the "exhaustive"
argument being lost due to cache being turned off) when O0 is used.
The changes in this commit are:
- Change -O0 to -Os because "gcc is considered broken at -O0" according to
https://github.com/ARM-software/CMSIS_5/issues/620#issuecomment-550235656
- Use volatile for mem_base so the compiler doesn't optimise away reads or
writes to the SDRAM, which is being tested.
- Use DSB to prevent any other compiler optimisations that would change the
testing logic.
- Use alternating pattern/antipattern in exhaustive test to catch more
hardware/configuration errors.
Implementation adapted by @andrewleech, taken directly from investigation
by @iabdalkader and @dpgeorge.
See #7841 and #7869 for further discussion.
* Make SDRAM test cache-aware for newer MCUs.
* Use the defined data bus width (instead of the fixed 8-bits).
* Allow optional failure on error with verbose error messages.
* Test speed is now inverted (test accepts exhaustive instead fast).
These functions enable SDRAM data retention in stop mode. Example usage,
in mpconfigboard.h:
#define MICROPY_BOARD_ENTER_STOP sdram_enter_low_power();
#define MICROPY_BOARD_LEAVE_STOP sdram_leave_low_power();
Set the active MPU region to the actual size of SDRAM configured and
invalidate the rest of the memory-mapped region, to prevent errors due to
CPU speculation. Also update the attributes of the SDRAM region as per ST
recommendations, and change region numbers to avoid conflicts elsewhere in
the codebase (see eth usage).
Currently all usages of mp_hal_pin_config_alt_static() set the pin speed to
"high" (50Mhz). The SDRAM interface typically runs much faster than this
so should be set to the maximum pin speed.
This commit adds mp_hal_pin_config_alt_static_speed() which allows setting
the pin speed along with the other alternate function details.
- Allow configuration by a board of autorefresh number and burst length.
- Increase MPU region size to 8MiB.
- Make SDRAM region cacheable and executable.
