Features are:
- 3 to 5 different frequency groups.
- Freq range of 1Hz - 24 MHz.
- Duty rate stays stable on freq change.
Keyword options to the PWM constructor:
- device=n Select a specific PWM device. If no device is specified, a free
device is chosen, if available at that pin.
- freq=nnnn
- duty_u16=nnnn
- duty_ns=nnnn
- invert=True/False Allowing two outputs on the same device/channel to have
complementary signals.
If both freq and duty are provided, PWM output will start immediately.
Pins at the same device have the same frequency. If the PWM output number
exceeds the number of channels at the PWM device, the effctive channel_no
is output_no % channel_count. So with a channel count of 4, output 7 is
assigned to channel 3. Pins at a certain channel have the same frequency
and duty rate, but may be seperately inverted.
With the method read_u16(). Keyword arguments of the constructor are:
- bits=n The resolution; default is 12.
- average=n The average of samples, which are taken and cumulated. The
default value is 16. Averaging by hw is faster than averaging
in code.
The ADC runs at a clock freq 1.5 MHz. A single 12 bit conversion takes
8 microseconds.
Clock settings:
- GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51).
- GCLK1: 32768 Hz for driving the PLL.
- GCLK2: 48 MHz for tzhe peripheral clock.
- GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer.
- GCLK8: 1 kHz for WDT (SAMD21 only).
If a 32 kHz crystal is present, it will be used as clock source. Otherwise
the DFLL48M in open-loop mode is used.
GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified
range is 96 MHz - 120 MHz.
For bare metal ARM & xtensa targets, passing -g will make the ELF file
larger but doesn't change the binary size. However, this means tools like
gdb, addr2line, etc can extract source-level information from the ELF.
Also standardise -ggdb to -g, these produce the exact same ELF file on
arm-none-eabi-gcc and will use DWARF format for all these ports.
This uses MP_REGISTER_ROOT_POINTER() to register the readline_history root
pointer array used by shared/readline.c and removes the registration from
all mpconfigport.h files.
This also required adding a new MICROPY_READLINE_HISTORY_SIZE config option
since not all ports used the same sized array.
Signed-off-by: David Lechner <david@pybricks.com>
This separates extmod source files from `py.mk`. Previously, `py.mk`
assumed that every consumer of the py/ directory also wanted to include
extmod/. However, this is not the case. For example, building mpy-cross
uses py/ but doesn't need extmod/.
This commit moves all extmod-specific items from `py.mk` to `extmod.mk` and
explicitly includes `extmod.mk` in ports that use it.
Signed-off-by: David Lechner <david@pybricks.com>
- Makefile: update to use new ASF4 files, support frozen manifest, and
include source files in upcoming commits
- boards/manifest.py: add files to freeze
- boards/samd51p19a.ld: add linker script for this MCU
- help.c: add custom help text
- main.c: execute _boot.py, boot.py and main.py on start-up
- modules/_boot.py: startup file to freeze
- modutime.c: add gmtime, localtime, mktime, time functions
- mpconfigport.h: enabled more features for sys and io and modules
- mphalport.h: add mp_hal_pin_xxx macros
- mphalport.c: add mp_hal_stdio_poll
No functionality change is intended with this commit, it just consolidates
the separate implementations of GC helper code to the lib/utils/ directory
as a general set of helper functions useful for any port. This reduces
duplication of code, and makes it easier for future ports or embedders to
get the GC implementation correct.
Ports should now link against gchelper_native.c and either gchelper_m0.s or
gchelper_m3.s (currently only Cortex-M is supported but other architectures
can follow), or use the fallback gchelper_generic.c which will work on
x86/x64/ARM.
The gc_helper_get_sp function from gchelper_m3.s is not really GC related
and was only used by cc3200, so it has been moved to that port and renamed
to cortex_m3_get_sp.
