This was introduced by 35fb90bd57, but
it is much simpler and essentially the same to just use
`tud_cdc_n_connected()`.
The only difference is that tud_cdc_n_connected() only checks for DTR,
but this is correct anyway: DTR indicates device presence, RTS indicates
that the host wants to receive data.
Signed-off-by: Damien Tournoud <damien@platform.sh>
usocket_events_deinit will only be available if MICROPY_PY_USOCKET_EVENTS
is enabled (which is only enabled when webrepl is enabled).
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
ADC: The argument of vref=num is an integer. Values for num are:
SAMD21:
0 INT1V 1.0V voltage reference
1 INTVCC0 1/1.48 Analog voltage supply
2 INTVCC1 1/2 Analog voltage supply (only for VDDANA > 2.0V)
3 VREFA External reference
4 VREFB External reference
SAMD51:
0 INTREF internal bandgap reference
1 INTVCC1 Analog voltage supply
2 INTVCC0 1/2 Analog voltage supply (only for VDDANA > 2.0v)
3 AREFA External reference A
4 AREFB External reference B
5 AREFC External reference C (ADC1 only)
DAC: The argument of vref=num is an integer. Suitable values:
SAMD21:
0 INT1V Internal voltage reference
1 VDDANA Analog voltage supply
2 VREFA External reference
SAMD51:
0 INTREF Internal bandgap reference
1 VDDANA Analog voltage supply
2 VREFAU Unbuffered external voltage reference (not buffered in DAC)
4 VREFAB Buffered external voltage reference (buffered in DAC).
Changes in this commit:
- Do not deinit IRQ when uart.deinit() is called with an inactive object.
- Remove using it for the finaliser. There is another machanism for soft
reset, and it is not needed otherwise.
- Do not tag the UART buffers with MP_STATE_PORT, it is not required.
Clearing the DRE flag for the transmit interrupt at the end of a
uart.write() also cleared the RXC flag disabling the receive interrupt.
This commit also changes the flag set/clear mechanism in the driver for SPI
as well, even if it did not cause a problem there. But at least it saves a
few bytes of code.
Applies to both SPI and I2C. The underflow caused high baudrate settings
resulting in the lowest possible baudrate. The overflow resulted in
erratic baudrates, not just the lowest possible.
The datasheet on page 55 shows PF0 (SDA) and PF1 (SCL) are the pins for
I2C2, but these pins do not work. Checking the MBED pinout for the
NUCLEO-F429ZI shows:
I2C1: PB8 (SCL) and PB9 (SDA).
I2C2: PB10 (SCL) and PB11 (SDA).
Both of these work and can be scanned and find devices connected to them.
Signed-off-by: Dale Weber <hybotics.sd@gmail.com>.
This changes the signatures of QSPI write_cmd_data, write_cmd_addr_data and
read_cmd_qaddr_qdata so they return an error code. The softqspi and stm32
hardware qspi driver are updated to follow this new signature. Also the
spiflash driver is updated to use these new return values.
Signed-off-by: Damien George <damien@micropython.org>
The assertion that is added here (to gc.c) fails when running this new test
if ALLOC_TABLE_GAP_BYTE is set to 0.
Signed-off-by: Jeff Epler <jepler@gmail.com>
Signed-off-by: Damien George <damien@micropython.org>
The STM32H7xx HAL LPUART AF macros are missing the number, this HAL is the
only one that's inconsistent in the way it defines LPUART AF macros, so we
only need to define them for H7.
Prior to this commit, only sector 0 was erase/write protected, which may
not be enough to protect all of mboot (especially if mboot lives at a
higher address than the start of flash).
This commit makes sure all internal flash sectors that mboot lives in are
protected from erasing and writing. The linker script must define
_mboot_writable_flash_start for this to work.
Signed-off-by: Damien George <damien@micropython.org>
The original ESP32 only supports timer source clock APB so it doesn't need
and doesn't have a clk_src field.
The ESP32C3 supports timer source clock APB and XTAL so it does have a
clk_src field, and this needs to be configured to get the correct period.
Fixes#8084.
Follow up to 8a91c719 to no longer explicitly disable BLE in
mpconfigport.h.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
For STM32L4, hardware I2C can be implemented by using TIMINGR.
This commit enables:
- Use of hardware I2C in machine.I2C.
- Specifying a frequency greater than or equal to 400KHz with pyb.I2C.
For STM32L4 series, the internal sensors are connected to:
- ADC1_IN0: Internal voltage reference
- ADC1_IN17: Temperature sensor
- ADC1_IN18: VBAT battery voltage monitoring
but ADC_CHANNEL_VREFINT, ADC_CHANNEL_VBAT, ADC_CHANNEL_TEMPSENSOR are not
defined as 0, 17, 18.
This commit converts channel 0, 17, 18 to ADC_CHANNEL_x in
adc_get_internal_channel().
Prior to this commit, the actual I2C frequency can be faster than specified
one and it may exceed the I2C's specification for Fast Mode. The frequency
of SCL should be less than or equal to 400KHz in Fast Mode.
This commit fixes this issue for F4 MCUs by rounding up the division in the
frequency calculation.
Excuting the code:
i2c = I2C(1, I2C.CONTROLLER, dma=True)
tmp = i2c.recv(1, i2c_addr)
recv_data = bytearray(56)
i2c.recv(recv_data, i2c_addr)
The second i2c.recv() fails with OSError: [Errno 110] ETIMEDOUT. When
receiving greater than or equal to 2 bytes at first i2c.recv(), the second
i2c.recv() succeeds. This issue does not occur without DMA.
Details of change: when executing I2C with DMA:
- Bit 11 of I2Cx_CR2 (DMA Request Enable) should be 1 to indicate that DMA
transfer is enabled. This bit is set after I2C event interrupt is
enabled in HAL_I2C_Master_Transmit_DMA()/HAL_I2C_Master_Receive_DMA(), so
DMA Request Enable bit might be 0 in IRQHandler.
- In case of data receive:
- When only 1 byte receiption, clear I2Cx_CR1's bit 10 (ACK).
- When only 2 byte receiption, clear I2Cx_CR1's bit 10 (ACK) and set
bit 11 (POS).
- When greater than or equal to 2 byte receiption, bit 12 of I2Cx_CR2
(DMA Last Transfer) should set to generate NACK when DMA transfer
completed.
Otherwise, the I2C bus may be busy after received data from peripheral.
Instead of defining `MICROPY_PY_BTREE` in `mpconfigport.h` we can define
it via CMake similar to how other ports that use Makefiles define it in
`mpconfigport.mk`.
Signed-off-by: David Lechner <david@pybricks.com>
The RT1176 has two cores, but the actual firmware supports only the CM7.
There are currently no good plans on how to use the CM4.
The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards,
with the following extensions:
- Use 64 MB RAM for the heap.
- Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1)
being the 1GB interface.
The dual LAN port interface can eventually be adapted as well for the
RT1062 MCU.
This work was done in collaboration with @alphaFred.
Avoids the 'warning: Wildcards in project items are not supported'
message from the C++ project system in Visual Studio, while otherwise
remaining completely functional.
A board can now name the CDC ports, eg:
#define MICROPY_HW_USB_CDC_NUM (3)
#define MICROPY_HW_USB_INTERFACE_CDC0_STRING "REPL"
#define MICROPY_HW_USB_INTERFACE_CDC1_STRING "GDB Server"
#define MICROPY_HW_USB_INTERFACE_CDC2_STRING "UART Port"
Signed-off-by: Damien George <damien@micropython.org>
The PWM module now detects if the pin is open drain and if so switches it
to hardware open drain before starting the PWM.
The code that was explicitly turning off the open drain output during PWM
is also removed.
Together these changes allow driving external transistor high-current
switches with PWM.
Signed-off-by: Trammell hudson <hudson@trmm.net>
Changes in this commit:
- Change file system size from 128KB to 64KB in ra6m1_ek.ld.
- Change EK-RA6M1's file system size in renesas-ra port document.
Signed-off-by: Takeo Takahashi <takeo.takahashi.xv@renesas.com>
Changes in this commit:
- Add FLASH_FS region to linker script.
- Add flash storage start & end symbols to linker script.
- Use flash storage start & end symbols in flashbdev.c
Signed-off-by: Takeo Takahashi <takeo.takahashi.xv@renesas.com>
App the mp_ prefix to usbd_ symbols and files which are defined here and
not in TinyUSB.
rp2 only for now. This includes some groundwork for dynamic USB devices
(defined in Python).
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Seems unused outside of spi.c, spi_obj[] array is the expected way to
iterate these.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
This changes the CustomEvent for stdout to use the existing `detail`
property of CustomEvent instead of adding a `data` property.
Signed-off-by: David Lechner <david@pybricks.com>
mip-cmdline adds command-line support to mip, useful for the unix port, via
micropython -m mip ...
Signed-off-by: Damien George <damien@micropython.org>
This commit executes __WFI() on core 0 only to avoid core1 locking up since
it doesn't enable any interrupts by default (except for `SIO_IRQ_PROC1`).
This fixes a lockup when calling `cyw43_do_ioctl` from core1.
Fixes issue #9597.
If USB CDC is connected and the board sends data, but the host does not
receive the data, the device locks up. This is fixed in this commit by
having a timeout of 500ms, after which time the transmission is skipped.
If USB CDC is connected and the board sends data, but the host does not
receive the data, the device locks up. This is fixed in this commit by
having a timeout of 500ms, after which time the transmission is skipped.
If USB CDC is connected and the board sends data, but the host does not
receive the data, the device locks up. This is fixed in this commit by
having a timeout of 500ms, after which time the transmission is skipped.
If USB CDC is connected and the board sends data, but the host does not
receive the data, the device locks up. This is fixed in this commit by
having a timeout of 500ms, after which time the transmission is skipped.
Fixes issue #9634.
Most of the content of README.md became obsolete and was replaced by the
documentation of MicroPython. Instead, README.md now shows build
instructions like the other ports.
Including the uasyncio scripts and the drivers for DHT, DS18x20 and
onewire. The uasyncio scripts need about 8k of flash and are not included
for the SAMD21 boards by default.
Emscripten strongly advises the use of optimisation when compiling with
ASYNCIFY enabled. Testing the difference betwen O3 and Os for various
configurations gives:
flags firmware.wasm micropython.js perf
-O3 -s ASYNCIFY 1342003 212845 0 (baseline)
-O3 -s ASYNCIFY -s WASM=0 - 7064750 -30%
-O3 367131 196569 +140%
-O3 -s WASM=0 - 2818260 +30%
-Os -s ASYNCIFY 1135450 213064 +40%
-Os -s ASYNCIFY -s WASM=0 - 6239768 -30%
-Os 295028 196569 +180%
-Os -s WASM=0 - 2271358 +30%
The first row is prior to this commit. The second and third columns show
firmware size (add them to get the total size). The fourth column shows
the approximate change in performance compared to the baseline. The
performance was measured using run-perfbench.py and the error was large, up
to 20%, although general trends in the change in performance could still be
seen.
In summary, using using Os instead of O3 makes it a little bit faster in
all cases, and smaller output (wasm/js) in all cases.
Signed-off-by: Damien George <damien@micropython.org>
This simplifies the config file. This is not a no-op, it does enable a few
new features to bring the port in line with this config level.
Signed-off-by: Damien George <damien@micropython.org>
Checks are added for pwm.freq(), pwm_duty(), pwm_duty_u10() and
pwm.duty_u16(). This avoids a core dump on ESP32C3, and misleading error
messages on Xtensa ESP32 devices.
Set the size of machine_pin_irq_handler array to GPIO_NUM_MAX:
- Min GPIO_NUM_MAX is 22 for IDF_TARGET_ESP32C3.
- Max GPIO_NUM_MAX is 49 for IDF_TARGET_ESP32S3.
The MP_REGISTER_ROOT_POINTER entry must be hard-coded, because the location
that it's evaluated by the compiler does not include the relevant IDF
header to get a definition of GPIO_NUM_MAX.
Each SoC family has its own clocks and timings/timeouts. For I2C, the
default source clock is either APB (ESP32, ESP32-S2) or XTAL (ESP32-S3,
ESP32-C3) as shown in the datasheets. Since
machine_i2c.c/machine_hw_i2c_init() uses the default clk_flags (0), the
alternate low-power clock source is never selected in ESP-IDF
i2c.c/i2c_param_config(). There is not an API in i2c.c to get the source
clock frequency, so a compile-time value is used based on SoC family.
Also, the maximum timeout is different across the SoC families, so use the
I2C_LL_MAX_TIMEOUT constant to eliminate the warning from
i2c_set_timeout().
With these changes, the following results were obtained. The I2C SCL
frequencies were measured with a Saleae logic analyzer.
ESP32 (TTGO T Dislay)
I2C(0, scl=22, sda=21, freq=101781) Measured: 100KHz
I2C(0, scl=22, sda=21, freq=430107) Measured: 400KHz
I2C(0, scl=22, sda=21, freq=1212121) Measured: 941KHz
ESP32-S3 (TTGO T-QT)
I2C(0, scl=34, sda=33, freq=111111) Measured: 107KHz
I2C(0, scl=34, sda=33, freq=444444) Measured: 400KHz
I2C(0, scl=34, sda=33, freq=1111111) Measured: 842KHz
ESP32-C3 (XIAO ESP32C3)
I2C(0, scl=7, sda=6, freq=107816) Measured: 103KHz
I2C(0, scl=7, sda=6, freq=444444) Measured: 380KHz
I2C(0, scl=7, sda=6, freq=1176470) Measured: 800KHz
(ESP32-S2 board was not available for testing.)
So that it doesn't clash with the extmod version.
Also make the default for this enabled, so that most boards do not need to
configure it.
Signed-off-by: Damien George <damien@micropython.org>
This issue affected i.MX RT 1052, 1062 and 1064. It seems to be addressed
by Errata ERR006223, which also mentions i.MX RT101x and 102x, but these
devices worked well even without the change. As a side effect, the current
consumption at an idle REPL drops significantly with this fix.
Fixes issue #7235.
Protect SerCom (UART, SPI, I2C) objects from getting freed by the GC when
they go out of scope without being deinitialized. Otherwise the ISR of a
Sercom may access an invalid data structure.
