This is a slight trade-off with code size, in places where a "_varg"
mp_raise variant is now used. The net savings on trinket_m0 is
just 32 bytes.
It also means that the translation will include the original English
text, and cannot be translated. These are usually names of Python
types such as int, set, or dict or special values such as "inf" or
"Nan".
.. this probably came from the examples that I studied at the beginning
of implementation.
The card detection feature is unused. As a "detect pin" is not
sent from the shared-bindings, there is no way to get the correct pin
anyway. Instead, if code needs to detect the insertion state it can
directly use the pin as GPIO in Python code.
Currently, only the bus specs of the stm32f405xx have been coded.
Other stm-family chips need (at a minimum) the specs added in their
periph.[ch] files.
I discussed with Hierophect on Discord about how to "de-nest" the code
for configuring SPI objects on STM, because the problems with one
nesting level per pin becomes unmanageable with the up to 10 pins of
SDIO.
This code (which is only compile-tested so far) demonstrates the concept
we discussed.
The SCK pin is always required. Loop over all possibilities of the SCK
pin. When we are considering a particular item in the mcu_spi_sck_list
we have now become committed to using a particular periph_index. If all
the other pins can be satisfied by that periph_index, then we have a
working combination. Once we have a working combination that is not
reserved, we can return that combination. On reaching the end, we have
checked all the possible possibilities and can give the same errors as
before: One if there was a possibility that worked but was reserved;
and another if no possibility worked.
When compiling with optimizations on, an issue occurs where the claimed_pins/never_reset_pins memory location is shared with another variable. This causes some bad memory read, so the USB pins ended up being reset. Setting these to have an alignment of 4 bytes resolves this.
Tested on nucleo_f746zg
Restructures the STM port of Circuitpython to be more generic about the STM32 chip lines to support
the F7 and H7 series of chips. Adds the new Packages directory to organize different chip layouts
between lines. Makes general changes to the Makefile to condense board-level flags to the minimum
and support the new chip series. Adds the new chip line to the Peripherals directory, along with
new python tools used to generate peripheral text automatically in the tools/ directory.
