It should be that:
- duty_u16=0: output low, no pulse
- duty_u16=65536: output high, no pulse
That previously did not apply to all of the three PWM mechanisms of this
port. This commit fixes it.
Signed-off-by: robert-hh <robert@hammelrath.com>
The nxp_driver v2.10 allows for/requires some changes to the code:
- Remove some part of pwm_backlog.*, which is provided by the lib now.
- Change eth.c: the newer versions have additional parameters of the
library versions.
- Change sdcard.c: use TransferBlocking instead of TransferNonblocking.
- Add some support for the MIMXRT1176 device.
- Set the clocks for UART, I2C, Timer.
- Integrate the I2S module and fix a rebase error.
- Use blocking transfer only for SPI. It's faster and interferes less with
other modules.
- Use the clock_config.c files of library v2.8.5. The mimxrt files keeps
the clock_config.c files from Verson 2.8.5. With clock_config.c from
v2.10, the boards do not work. Refactoring of the clock set-up is on the
to-do list.
- Enable expiry timers for UART, I2C and SPI, avoiding a stall in library
code.
- The clock_config.* files are moved from the board-specific directories to
the boards directory and given a MCU related name.
Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the
duty cycle. The basic API is supported as documentated, except that
keyword parameters are accepted for both the instatiaton and the
PWM.init() call.
Extensions: support PWM for channel pairs. Channel pairs are declared by
supplying 2-element tuples for the pins. The two channels of a pair must
be the A/B channel of a FLEXPWM module. These form than a complementary
pair.
Additional supported keyword arguments:
- center=value Defines the center position of a pulse within the pulse
cycle. The align keyword is actually shortcut for center.
- sync=True|False: If set to True, the channels will be synchronized to a
submodule 0 channel, which has already to be enabled.
- align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized
channels are Center-Aligned or Edge-aligned. The channels must be either
complementary a channel pair or a group of synchronized channels. It may
as well be applied to a single channel, but withiout any benefit.
- invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the
first pin, bit 1 the second.
- deadtime=time_ns time of complementary channels for delaying the rising
slope.
- xor=0|1|2 xor causes the output of channel A and B to be xored. If
applied to a X channel, it shows the value oif A ^ B. If applied to an A
or B channel, both channel show the xored signal for xor=1. For xor=2,
the xored signal is split between channels A and B. See also the
Reference Manual, chapter about double pulses. The behavior of xor=2 can
also be achieved using the center method for locating a pulse within a
clock period.
The output is enabled for board pins only.
CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal
will not be routed to the output. That applies only to FLEXPWM pins. The
use of QTMR pins which are not board pins will be rejected.
As part of this commit, the _WFE() statement is removed from
ticks_delay_us64() to prevent PWM glitching during calls to sleep().
