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Merge pull request #2789 from simmel-project/nrf52833

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Add support for nrf52833
This commit is contained in:
Scott Shawcroft 2020-04-21 11:33:36 -07:00 committed by GitHub
commit ff9e388910
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GPG Key ID: 4AEE18F83AFDEB23
16 changed files with 507 additions and 21 deletions
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5
ports/nrf/Makefile
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@ -182,6 +182,11 @@ SRC_C += \
lib/tinyusb/src/portable/nordic/nrf5x/dcd_nrf5x.c lib/tinyusb/src/portable/nordic/nrf5x/dcd_nrf5x.c
endif endif
ifeq ($(MCU_SUB_VARIANT),nrf52833)
SRC_C += \
lib/tinyusb/src/portable/nordic/nrf5x/dcd_nrf5x.c
endif
ifeq ($(CIRCUITPY_NETWORK),1) ifeq ($(CIRCUITPY_NETWORK),1)
CFLAGS += -DMICROPY_PY_NETWORK=1 CFLAGS += -DMICROPY_PY_NETWORK=1

4
ports/nrf/boards/common.template.ld
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@ -5,7 +5,7 @@
/* Specify the memory areas */ /* Specify the memory areas */
MEMORY MEMORY
{ {
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 /* entire flash, 1 MiB */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} /* entire flash */
/* nRF SoftDevice */ /* nRF SoftDevice */
FLASH_MBR (rx) : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE} FLASH_MBR (rx) : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}
FLASH_SD (rx) : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE} FLASH_SD (rx) : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}
@ -23,7 +23,7 @@ MEMORY
/* To measure the minimum required amount of memory for given configuration, set this number /* To measure the minimum required amount of memory for given configuration, set this number
high enough to work and then check the mutation of the value done by sd_ble_enable. */ high enough to work and then check the mutation of the value done by sd_ble_enable. */
SPIM3_RAM (rw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE} SPIM3_RAM (rw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}
RAM (xrw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = 256K - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE} RAM (xrw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}
} }

30
ports/nrf/common-hal/_bleio/Adapter.c
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@ -56,6 +56,26 @@
#define BLE_SLAVE_LATENCY 0 #define BLE_SLAVE_LATENCY 0
#define BLE_CONN_SUP_TIMEOUT MSEC_TO_UNITS(4000, UNIT_10_MS) #define BLE_CONN_SUP_TIMEOUT MSEC_TO_UNITS(4000, UNIT_10_MS)
#ifndef BLEIO_VS_UUID_COUNT
#define BLEIO_VS_UUID_COUNT 75
#endif
#ifndef BLEIO_HVN_TX_QUEUE_SIZE
#define BLEIO_HVN_TX_QUEUE_SIZE 9
#endif
#ifndef BLEIO_CENTRAL_ROLE_COUNT
#define BLEIO_CENTRAL_ROLE_COUNT 4
#endif
#ifndef BLEIO_PERIPH_ROLE_COUNT
#define BLEIO_PERIPH_ROLE_COUNT 4
#endif
#ifndef BLEIO_ATTR_TAB_SIZE
#define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 5)
#endif
const nvm_bytearray_obj_t common_hal_bleio_nvm_obj = { const nvm_bytearray_obj_t common_hal_bleio_nvm_obj = {
.base = { .base = {
.type = &nvm_bytearray_type, .type = &nvm_bytearray_type,
@ -124,9 +144,9 @@ STATIC uint32_t ble_stack_enable(void) {
// adv_set_count must be == 1 for S140. Cannot be increased. // adv_set_count must be == 1 for S140. Cannot be increased.
ble_conf.gap_cfg.role_count_cfg.adv_set_count = 1; ble_conf.gap_cfg.role_count_cfg.adv_set_count = 1;
// periph_role_count costs 1232 bytes for 2 to 3, then ~1840 for each further increment. // periph_role_count costs 1232 bytes for 2 to 3, then ~1840 for each further increment.
ble_conf.gap_cfg.role_count_cfg.periph_role_count = 4; ble_conf.gap_cfg.role_count_cfg.periph_role_count = BLEIO_PERIPH_ROLE_COUNT;
// central_role_count costs 648 bytes for 1 to 2, then ~1250 for each further increment. // central_role_count costs 648 bytes for 1 to 2, then ~1250 for each further increment.
ble_conf.gap_cfg.role_count_cfg.central_role_count = 4; ble_conf.gap_cfg.role_count_cfg.central_role_count = BLEIO_CENTRAL_ROLE_COUNT;
err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_conf, app_ram_start); err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_conf, app_ram_start);
if (err_code != NRF_SUCCESS) { if (err_code != NRF_SUCCESS) {
return err_code; return err_code;
@ -137,7 +157,7 @@ STATIC uint32_t ble_stack_enable(void) {
// Each increment to hvn_tx_queue_size costs 2064 bytes. // Each increment to hvn_tx_queue_size costs 2064 bytes.
// DevZone recommends not setting this directly, but instead changing gap_conn_cfg.event_length. // DevZone recommends not setting this directly, but instead changing gap_conn_cfg.event_length.
// However, we are setting connection extension, so this seems to make sense. // However, we are setting connection extension, so this seems to make sense.
ble_conf.conn_cfg.params.gatts_conn_cfg.hvn_tx_queue_size = 9; ble_conf.conn_cfg.params.gatts_conn_cfg.hvn_tx_queue_size = BLEIO_HVN_TX_QUEUE_SIZE;
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATTS, &ble_conf, app_ram_start); err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATTS, &ble_conf, app_ram_start);
if (err_code != NRF_SUCCESS) { if (err_code != NRF_SUCCESS) {
return err_code; return err_code;
@ -156,7 +176,7 @@ STATIC uint32_t ble_stack_enable(void) {
// and anything the user does. // and anything the user does.
memset(&ble_conf, 0, sizeof(ble_conf)); memset(&ble_conf, 0, sizeof(ble_conf));
// Each increment to the BLE_GATTS_ATTR_TAB_SIZE_DEFAULT multiplier costs 1408 bytes. // Each increment to the BLE_GATTS_ATTR_TAB_SIZE_DEFAULT multiplier costs 1408 bytes.
ble_conf.gatts_cfg.attr_tab_size.attr_tab_size = BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 5; ble_conf.gatts_cfg.attr_tab_size.attr_tab_size = BLEIO_ATTR_TAB_SIZE;
err_code = sd_ble_cfg_set(BLE_GATTS_CFG_ATTR_TAB_SIZE, &ble_conf, app_ram_start); err_code = sd_ble_cfg_set(BLE_GATTS_CFG_ATTR_TAB_SIZE, &ble_conf, app_ram_start);
if (err_code != NRF_SUCCESS) { if (err_code != NRF_SUCCESS) {
return err_code; return err_code;
@ -166,7 +186,7 @@ STATIC uint32_t ble_stack_enable(void) {
// service and characteristic. // service and characteristic.
memset(&ble_conf, 0, sizeof(ble_conf)); memset(&ble_conf, 0, sizeof(ble_conf));
// Each additional vs_uuid_count costs 16 bytes. // Each additional vs_uuid_count costs 16 bytes.
ble_conf.common_cfg.vs_uuid_cfg.vs_uuid_count = 75; // Defaults to 10. ble_conf.common_cfg.vs_uuid_cfg.vs_uuid_count = BLEIO_VS_UUID_COUNT; // Defaults to 10.
err_code = sd_ble_cfg_set(BLE_COMMON_CFG_VS_UUID, &ble_conf, app_ram_start); err_code = sd_ble_cfg_set(BLE_COMMON_CFG_VS_UUID, &ble_conf, app_ram_start);
if (err_code != NRF_SUCCESS) { if (err_code != NRF_SUCCESS) {
return err_code; return err_code;

2
ports/nrf/common-hal/_bleio/Adapter.h
View File

@ -35,7 +35,9 @@
#include "shared-bindings/_bleio/Connection.h" #include "shared-bindings/_bleio/Connection.h"
#include "shared-bindings/_bleio/ScanResults.h" #include "shared-bindings/_bleio/ScanResults.h"
#ifndef BLEIO_TOTAL_CONNECTION_COUNT
#define BLEIO_TOTAL_CONNECTION_COUNT 5 #define BLEIO_TOTAL_CONNECTION_COUNT 5
#endif
extern bleio_connection_internal_t bleio_connections[BLEIO_TOTAL_CONNECTION_COUNT]; extern bleio_connection_internal_t bleio_connections[BLEIO_TOTAL_CONNECTION_COUNT];

12
ports/nrf/common-hal/microcontroller/__init__.c
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@ -168,5 +168,17 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = {
{ MP_ROM_QSTR(MP_QSTR_P1_14), MP_ROM_PTR(&pin_P1_14) }, { MP_ROM_QSTR(MP_QSTR_P1_14), MP_ROM_PTR(&pin_P1_14) },
{ MP_ROM_QSTR(MP_QSTR_P1_15), MP_ROM_PTR(&pin_P1_15) }, { MP_ROM_QSTR(MP_QSTR_P1_15), MP_ROM_PTR(&pin_P1_15) },
#endif #endif
#ifdef NRF52833
{ MP_ROM_QSTR(MP_QSTR_P1_00), MP_ROM_PTR(&pin_P1_00) },
{ MP_ROM_QSTR(MP_QSTR_P1_01), MP_ROM_PTR(&pin_P1_01) },
{ MP_ROM_QSTR(MP_QSTR_P1_02), MP_ROM_PTR(&pin_P1_02) },
{ MP_ROM_QSTR(MP_QSTR_P1_03), MP_ROM_PTR(&pin_P1_03) },
{ MP_ROM_QSTR(MP_QSTR_P1_04), MP_ROM_PTR(&pin_P1_04) },
{ MP_ROM_QSTR(MP_QSTR_P1_05), MP_ROM_PTR(&pin_P1_05) },
{ MP_ROM_QSTR(MP_QSTR_P1_06), MP_ROM_PTR(&pin_P1_06) },
{ MP_ROM_QSTR(MP_QSTR_P1_07), MP_ROM_PTR(&pin_P1_07) },
{ MP_ROM_QSTR(MP_QSTR_P1_08), MP_ROM_PTR(&pin_P1_08) },
{ MP_ROM_QSTR(MP_QSTR_P1_09), MP_ROM_PTR(&pin_P1_09) },
#endif
}; };
MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);

184
ports/nrf/device/nrf52/startup_nrf52833.c Normal file
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@ -0,0 +1,184 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdint.h>
extern uint32_t _estack;
extern uint32_t _sidata;
extern uint32_t _sdata;
extern uint32_t _edata;
extern uint32_t _sbss;
extern uint32_t _ebss;
typedef void (*func)(void);
#define _start main
extern void _start(void) __attribute__((noreturn));
extern void SystemInit(void);
void Default_Handler(void) {
while (1);
}
void Reset_Handler(void) {
uint32_t * p_src = &_sidata;
uint32_t * p_dest = &_sdata;
while (p_dest < &_edata) {
*p_dest++ = *p_src++;
}
uint32_t * p_bss = &_sbss;
uint32_t * p_bss_end = &_ebss;
while (p_bss < p_bss_end) {
*p_bss++ = 0ul;
}
SystemInit();
_start();
}
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void MemoryManagement_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void RADIO_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void UARTE0_UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void NFCT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void GPIOTE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SAADC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void RTC0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void TEMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void ECB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void CCM_AAR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void RTC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void QDEC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void COMP_LPCOMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SWI0_EGU0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SWI1_EGU1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SWI2_EGU2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SWI3_EGU3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SWI4_EGU4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SWI5_EGU5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void PWM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void PDM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void MWU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void PWM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void PWM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void RTC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void I2S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void USBD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void UARTE1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void PWM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void SPIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
const func __Vectors[] __attribute__ ((used, section(".isr_vector"))) = {
(func)&_estack,
Reset_Handler,
NMI_Handler,
HardFault_Handler,
MemoryManagement_Handler,
BusFault_Handler,
UsageFault_Handler,
0,
0,
0,
0,
SVC_Handler,
DebugMon_Handler,
0,
PendSV_Handler,
SysTick_Handler,
/* External Interrupts */
POWER_CLOCK_IRQHandler,
RADIO_IRQHandler,
UARTE0_UART0_IRQHandler,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler,
NFCT_IRQHandler,
GPIOTE_IRQHandler,
SAADC_IRQHandler,
TIMER0_IRQHandler,
TIMER1_IRQHandler,
TIMER2_IRQHandler,
RTC0_IRQHandler,
TEMP_IRQHandler,
RNG_IRQHandler,
ECB_IRQHandler,
CCM_AAR_IRQHandler,
WDT_IRQHandler,
RTC1_IRQHandler,
QDEC_IRQHandler,
COMP_LPCOMP_IRQHandler,
SWI0_EGU0_IRQHandler,
SWI1_EGU1_IRQHandler,
SWI2_EGU2_IRQHandler,
SWI3_EGU3_IRQHandler,
SWI4_EGU4_IRQHandler,
SWI5_EGU5_IRQHandler,
TIMER3_IRQHandler,
TIMER4_IRQHandler,
PWM0_IRQHandler,
PDM_IRQHandler,
0,
0,
MWU_IRQHandler,
PWM1_IRQHandler,
PWM2_IRQHandler,
SPIM2_SPIS2_SPI2_IRQHandler,
RTC2_IRQHandler,
I2S_IRQHandler,
FPU_IRQHandler,
USBD_IRQHandler,
UARTE1_IRQHandler,
0,
0,
0,
0,
PWM3_IRQHandler,
0,
SPIM3_IRQHandler,
};

3
ports/nrf/ld_defines.c
View File

@ -9,6 +9,9 @@
// The next line is a marker to start looking for definitions. Lines above the next line are ignored. // The next line is a marker to start looking for definitions. Lines above the next line are ignored.
// START_LD_DEFINES // START_LD_DEFINES
/*FLASH_SIZE=*/ FLASH_SIZE;
/*RAM_SIZE=*/ RAM_SIZE;
/*MBR_START_ADDR=*/ MBR_START_ADDR; /*MBR_START_ADDR=*/ MBR_START_ADDR;
/*MBR_SIZE=*/ MBR_SIZE; /*MBR_SIZE=*/ MBR_SIZE;

27
ports/nrf/mpconfigport.h
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@ -36,16 +36,30 @@
// Max RAM used by SoftDevice. Can be changed when SoftDevice parameters are changed. // Max RAM used by SoftDevice. Can be changed when SoftDevice parameters are changed.
// See common.template.ld. // See common.template.ld.
#ifndef SOFTDEVICE_RAM_SIZE
#define SOFTDEVICE_RAM_SIZE (64*1024) #define SOFTDEVICE_RAM_SIZE (64*1024)
#endif
#ifdef NRF52840 #ifdef NRF52840
#define MICROPY_PY_SYS_PLATFORM "nRF52840" #define MICROPY_PY_SYS_PLATFORM "nRF52840"
#define FLASH_SIZE (0x100000) // 1MiB #define FLASH_SIZE (0x100000) // 1MiB
#define RAM_SIZE (0x40000) // 256 KiB
// Special RAM area for SPIM3 transmit buffer, to work around hardware bug. // Special RAM area for SPIM3 transmit buffer, to work around hardware bug.
// See common.template.ld. // See common.template.ld.
#define SPIM3_BUFFER_SIZE (8192) #define SPIM3_BUFFER_SIZE (8192)
#endif #endif
#ifdef NRF52833
#define MICROPY_PY_SYS_PLATFORM "nRF52833"
#define FLASH_SIZE (0x80000) // 512 KiB
#define RAM_SIZE (0x20000) // 128 KiB
// Special RAM area for SPIM3 transmit buffer, to work around hardware bug.
// See common.template.ld.
#ifndef SPIM3_BUFFER_SIZE
#define SPIM3_BUFFER_SIZE (8192)
#endif
#endif
#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1) #define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1)
#define MICROPY_PY_FUNCTION_ATTRS (1) #define MICROPY_PY_FUNCTION_ATTRS (1)
#define MICROPY_PY_IO (1) #define MICROPY_PY_IO (1)
@ -112,25 +126,30 @@
// Define these regions starting down from the bootloader: // Define these regions starting down from the bootloader:
// Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld // Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld
#define BOOTLOADER_START_ADDR (0x000F4000) #define BOOTLOADER_START_ADDR (FLASH_SIZE - BOOTLOADER_SIZE - BOOTLOADER_SETTINGS_SIZE - BOOTLOADER_MBR_SIZE)
#define BOOTLOADER_MBR_SIZE (0x1000) // 4kib
#ifndef BOOTLOADER_SIZE
#define BOOTLOADER_SIZE (0xA000) // 40kiB #define BOOTLOADER_SIZE (0xA000) // 40kiB
#define BOOTLOADER_SETTINGS_START_ADDR (0x000FF000) #endif
#define BOOTLOADER_SETTINGS_START_ADDR (FLASH_SIZE - BOOTLOADER_SETTINGS_SIZE)
#define BOOTLOADER_SETTINGS_SIZE (0x1000) // 4kiB #define BOOTLOADER_SETTINGS_SIZE (0x1000) // 4kiB
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR (BOOTLOADER_START_ADDR - CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE) #define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR (BOOTLOADER_START_ADDR - CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE)
#if CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE > 0 && CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR != (BOOTLOADER_START_ADDR - 256*1024) #if CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE > 0 && CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR != (BOOTLOADER_START_ADDR - CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE)
#warning Internal flash filesystem location has moved! #warning Internal flash filesystem location has moved!
#endif #endif
#define CIRCUITPY_INTERNAL_NVM_START_ADDR (CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR - CIRCUITPY_INTERNAL_NVM_SIZE) #define CIRCUITPY_INTERNAL_NVM_START_ADDR (CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR - CIRCUITPY_INTERNAL_NVM_SIZE)
// 32kiB for bonding, etc. // 32kiB for bonding, etc.
#ifndef CIRCUITPY_BLE_CONFIG_SIZE
#define CIRCUITPY_BLE_CONFIG_SIZE (32*1024) #define CIRCUITPY_BLE_CONFIG_SIZE (32*1024)
#endif
#define CIRCUITPY_BLE_CONFIG_START_ADDR (CIRCUITPY_INTERNAL_NVM_START_ADDR - CIRCUITPY_BLE_CONFIG_SIZE) #define CIRCUITPY_BLE_CONFIG_START_ADDR (CIRCUITPY_INTERNAL_NVM_START_ADDR - CIRCUITPY_BLE_CONFIG_SIZE)
// The firmware space is the space left over between the fixed lower and upper regions. // The firmware space is the space left over between the fixed lower and upper regions.
#define CIRCUITPY_FIRMWARE_SIZE (CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR - CIRCUITPY_FIRMWARE_START_ADDR) #define CIRCUITPY_FIRMWARE_SIZE (CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR - CIRCUITPY_FIRMWARE_START_ADDR - CIRCUITPY_BLE_CONFIG_SIZE)
#if BOOTLOADER_START_ADDR % FLASH_ERASE_SIZE != 0 #if BOOTLOADER_START_ADDR % FLASH_ERASE_SIZE != 0
#error BOOTLOADER_START_ADDR must be on a flash erase boundary. #error BOOTLOADER_START_ADDR must be on a flash erase boundary.

18
ports/nrf/mpconfigport.mk
View File

@ -51,8 +51,8 @@ endif
# frequencyio not yet implemented # frequencyio not yet implemented
CIRCUITPY_FREQUENCYIO = 0 CIRCUITPY_FREQUENCYIO = 0
CIRCUITPY_RGBMATRIX = 1 CIRCUITPY_RGBMATRIX ?= 1
CIRCUITPY_FRAMEBUFFERIO = 1 CIRCUITPY_FRAMEBUFFERIO ?= 1
# nRF52840-specific # nRF52840-specific
@ -73,4 +73,18 @@ NRF_DEFINES += -DNRF52840_XXAA -DNRF52840
CFLAGS += -DCONFIG_NFCT_PINS_AS_GPIOS CFLAGS += -DCONFIG_NFCT_PINS_AS_GPIOS
CIRCUITPY_ULAB = 1 CIRCUITPY_ULAB = 1
else
ifeq ($(MCU_CHIP),nrf52833)
MCU_SERIES = m4
MCU_VARIANT = nrf52
MCU_SUB_VARIANT = nrf52833
SD ?= s140
SOFTDEV_VERSION ?= 6.1.0
BOOT_SETTING_ADDR = 0x7F000
NRF_DEFINES += -DNRF52833_XXAA -DNRF52833
endif
endif endif

19
ports/nrf/nrfx_config.h
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@ -31,8 +31,8 @@
#define CIRCUITPY_NRF_NUM_I2C 2 #define CIRCUITPY_NRF_NUM_I2C 2
#endif #endif
#if CIRCUITPY_NRF_NUM_I2C != 1 && CIRCUITPY_NRF_NUM_I2C != 2 #if CIRCUITPY_NRF_NUM_I2C != 0 && CIRCUITPY_NRF_NUM_I2C != 1 && CIRCUITPY_NRF_NUM_I2C != 2
# error CIRCUITPY_NRF_NUM_I2C must be 1 or 2 # error CIRCUITPY_NRF_NUM_I2C must be 0, 1, or 2
#endif #endif
// Enable SPIM1, SPIM2 and SPIM3 (if available) // Enable SPIM1, SPIM2 and SPIM3 (if available)
@ -41,10 +41,10 @@
#define NRFX_SPIM1_ENABLED 1 #define NRFX_SPIM1_ENABLED 1
#endif #endif
#define NRFX_SPIM2_ENABLED 1 #define NRFX_SPIM2_ENABLED 1
#ifdef NRF52840_XXAA #if defined(NRF52840_XXAA) || defined(NRF52833_XXAA)
#define NRFX_SPIM_EXTENDED_ENABLED 1 #define NRFX_SPIM_EXTENDED_ENABLED 1
#define NRFX_SPIM3_ENABLED 1 #define NRFX_SPIM3_ENABLED 1
#else #elif CIRCUITPY_NRF_NUM_I2C == 2
#define NRFX_SPIM3_ENABLED 0 #define NRFX_SPIM3_ENABLED 0
#endif #endif
@ -53,20 +53,23 @@
#define NRFX_SPIM_MISO_PULL_CFG 1 #define NRFX_SPIM_MISO_PULL_CFG 1
// QSPI // QSPI
#if defined(NRF52840_XXAA)
#define NRFX_QSPI_ENABLED 1 #define NRFX_QSPI_ENABLED 1
#endif
// TWI aka. I2C; always enable TWIM0 (no conflict with SPIM1 and SPIM2) // TWI aka. I2C; always enable TWIM0 (no conflict with SPIM1 and SPIM2)
#if CIRCUITPY_NRF_NUM_I2C == 1 || CIRCUITPY_NRF_NUM_I2C == 2
#define NRFX_TWIM_ENABLED 1 #define NRFX_TWIM_ENABLED 1
#define NRFX_TWIM0_ENABLED 1 #define NRFX_TWIM0_ENABLED 1
#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY NRF_TWIM_FREQ_400K
#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
#endif
#if CIRCUITPY_NRF_NUM_I2C == 2 #if CIRCUITPY_NRF_NUM_I2C == 2
#define NRFX_TWIM1_ENABLED 1 #define NRFX_TWIM1_ENABLED 1
#endif #endif
#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY NRF_TWIM_FREQ_400K
#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
// UART // UART
#define NRFX_UARTE_ENABLED 1 #define NRFX_UARTE_ENABLED 1
#define NRFX_UARTE0_ENABLED 1 #define NRFX_UARTE0_ENABLED 1

72
ports/nrf/peripherals/nrf/nrf52833/pins.c Normal file
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@ -0,0 +1,72 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2018 Dan Halbert for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/obj.h"
#include "py/mphal.h"
#include "nrf/pins.h"
const mcu_pin_obj_t pin_P0_00 = PIN(P0_00, 0, 0, 0);
const mcu_pin_obj_t pin_P0_01 = PIN(P0_01, 0, 1, 0);
const mcu_pin_obj_t pin_P0_02 = PIN(P0_02, 0, 2, SAADC_CH_PSELP_PSELP_AnalogInput0);
const mcu_pin_obj_t pin_P0_03 = PIN(P0_03, 0, 3, SAADC_CH_PSELP_PSELP_AnalogInput1);
const mcu_pin_obj_t pin_P0_04 = PIN(P0_04, 0, 4, SAADC_CH_PSELP_PSELP_AnalogInput2);
const mcu_pin_obj_t pin_P0_05 = PIN(P0_05, 0, 5, SAADC_CH_PSELP_PSELP_AnalogInput3);
const mcu_pin_obj_t pin_P0_06 = PIN(P0_06, 0, 6, 0);
const mcu_pin_obj_t pin_P0_07 = PIN(P0_07, 0, 7, 0);
const mcu_pin_obj_t pin_P0_08 = PIN(P0_08, 0, 8, 0);
const mcu_pin_obj_t pin_P0_09 = PIN(P0_09, 0, 9, 0);
const mcu_pin_obj_t pin_P0_10 = PIN(P0_10, 0, 10, 0);
const mcu_pin_obj_t pin_P0_11 = PIN(P0_11, 0, 11, 0);
const mcu_pin_obj_t pin_P0_12 = PIN(P0_12, 0, 12, 0);
const mcu_pin_obj_t pin_P0_13 = PIN(P0_13, 0, 13, 0);
const mcu_pin_obj_t pin_P0_14 = PIN(P0_14, 0, 14, 0);
const mcu_pin_obj_t pin_P0_15 = PIN(P0_15, 0, 15, 0);
const mcu_pin_obj_t pin_P0_16 = PIN(P0_16, 0, 16, 0);
const mcu_pin_obj_t pin_P0_17 = PIN(P0_17, 0, 17, 0);
const mcu_pin_obj_t pin_P0_18 = PIN(P0_18, 0, 18, 0);
const mcu_pin_obj_t pin_P0_19 = PIN(P0_19, 0, 19, 0);
const mcu_pin_obj_t pin_P0_20 = PIN(P0_20, 0, 20, 0);
const mcu_pin_obj_t pin_P0_21 = PIN(P0_21, 0, 21, 0);
const mcu_pin_obj_t pin_P0_22 = PIN(P0_22, 0, 22, 0);
const mcu_pin_obj_t pin_P0_23 = PIN(P0_23, 0, 23, 0);
const mcu_pin_obj_t pin_P0_24 = PIN(P0_24, 0, 24, 0);
const mcu_pin_obj_t pin_P0_25 = PIN(P0_25, 0, 25, 0);
const mcu_pin_obj_t pin_P0_26 = PIN(P0_26, 0, 26, 0);
const mcu_pin_obj_t pin_P0_27 = PIN(P0_27, 0, 27, 0);
const mcu_pin_obj_t pin_P0_28 = PIN(P0_28, 0, 28, SAADC_CH_PSELP_PSELP_AnalogInput4);
const mcu_pin_obj_t pin_P0_29 = PIN(P0_29, 0, 29, SAADC_CH_PSELP_PSELP_AnalogInput5);
const mcu_pin_obj_t pin_P0_30 = PIN(P0_30, 0, 30, SAADC_CH_PSELP_PSELP_AnalogInput6);
const mcu_pin_obj_t pin_P0_31 = PIN(P0_31, 0, 31, SAADC_CH_PSELP_PSELP_AnalogInput7);
const mcu_pin_obj_t pin_P1_00 = PIN(P1_00, 1, 0, 0);
const mcu_pin_obj_t pin_P1_01 = PIN(P1_01, 1, 1, 0);
const mcu_pin_obj_t pin_P1_02 = PIN(P1_02, 1, 2, 0);
const mcu_pin_obj_t pin_P1_03 = PIN(P1_03, 1, 3, 0);
const mcu_pin_obj_t pin_P1_04 = PIN(P1_04, 1, 4, 0);
const mcu_pin_obj_t pin_P1_05 = PIN(P1_05, 1, 5, 0);
const mcu_pin_obj_t pin_P1_06 = PIN(P1_06, 1, 6, 0);
const mcu_pin_obj_t pin_P1_07 = PIN(P1_07, 1, 7, 0);
const mcu_pin_obj_t pin_P1_08 = PIN(P1_08, 1, 8, 0);
const mcu_pin_obj_t pin_P1_09 = PIN(P1_09, 1, 9, 0);

73
ports/nrf/peripherals/nrf/nrf52833/pins.h Normal file
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@ -0,0 +1,73 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2018 by Dan Halbert for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_NRF_PERIPHERALS_NRF52833_PINS_H
#define MICROPY_INCLUDED_NRF_PERIPHERALS_NRF52833_PINS_H
extern const mcu_pin_obj_t pin_P0_00;
extern const mcu_pin_obj_t pin_P0_01;
extern const mcu_pin_obj_t pin_P0_02;
extern const mcu_pin_obj_t pin_P0_03;
extern const mcu_pin_obj_t pin_P0_04;
extern const mcu_pin_obj_t pin_P0_05;
extern const mcu_pin_obj_t pin_P0_06;
extern const mcu_pin_obj_t pin_P0_07;
extern const mcu_pin_obj_t pin_P0_08;
extern const mcu_pin_obj_t pin_P0_09;
extern const mcu_pin_obj_t pin_P0_10;
extern const mcu_pin_obj_t pin_P0_11;
extern const mcu_pin_obj_t pin_P0_12;
extern const mcu_pin_obj_t pin_P0_13;
extern const mcu_pin_obj_t pin_P0_14;
extern const mcu_pin_obj_t pin_P0_15;
extern const mcu_pin_obj_t pin_P0_16;
extern const mcu_pin_obj_t pin_P0_17;
extern const mcu_pin_obj_t pin_P0_18;
extern const mcu_pin_obj_t pin_P0_19;
extern const mcu_pin_obj_t pin_P0_20;
extern const mcu_pin_obj_t pin_P0_21;
extern const mcu_pin_obj_t pin_P0_22;
extern const mcu_pin_obj_t pin_P0_23;
extern const mcu_pin_obj_t pin_P0_24;
extern const mcu_pin_obj_t pin_P0_25;
extern const mcu_pin_obj_t pin_P0_26;
extern const mcu_pin_obj_t pin_P0_27;
extern const mcu_pin_obj_t pin_P0_28;
extern const mcu_pin_obj_t pin_P0_29;
extern const mcu_pin_obj_t pin_P0_30;
extern const mcu_pin_obj_t pin_P0_31;
extern const mcu_pin_obj_t pin_P1_00;
extern const mcu_pin_obj_t pin_P1_01;
extern const mcu_pin_obj_t pin_P1_02;
extern const mcu_pin_obj_t pin_P1_03;
extern const mcu_pin_obj_t pin_P1_04;
extern const mcu_pin_obj_t pin_P1_05;
extern const mcu_pin_obj_t pin_P1_06;
extern const mcu_pin_obj_t pin_P1_07;
extern const mcu_pin_obj_t pin_P1_08;
extern const mcu_pin_obj_t pin_P1_09;
#endif // MICROPY_INCLUDED_NRF_PERIPHERALS_NRF52833_PINS_H

50
ports/nrf/peripherals/nrf/nrf52833/power.c Normal file
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@ -0,0 +1,50 @@
/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2018 Dan Halbert for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "nrfx.h"
#include "hal/nrf_nvmc.h"
void nrf_peripherals_power_init(void) {
// Set GPIO reference voltage to 3.3V if it isn't already. REGOUT0 will get reset to 0xfffffff
// if flash is erased, which sets the default to 1.8V
// This matters only when "high voltage mode" is enabled, which is true on the PCA10059,
// and might be true on other boards.
if (NRF_UICR->REGOUT0 == 0xffffffff && NRF_POWER->MAINREGSTATUS & 1) {
// Expand what nrf_nvmc_word_write() did.
// It's missing from nrfx V2.0.0, and nrfx_nvmc_word_write() does bounds
// checking which prevents writes to UICR.
// Reported: https://devzone.nordicsemi.com/f/nordic-q-a/57243/nrfx_nvmc-h-api-cannot-write-to-uicr
NRF_NVMC->CONFIG = NRF_NVMC_MODE_WRITE;
while (!(NRF_NVMC->READY & NVMC_READY_READY_Msk)) {}
NRF_UICR->REGOUT0 = UICR_REGOUT0_VOUT_3V3 << UICR_REGOUT0_VOUT_Pos;
__DMB();
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
NRF_NVMC->CONFIG = NRF_NVMC_MODE_READONLY;
// Must reset to enable change.
NVIC_SystemReset();
}
}

5
ports/nrf/peripherals/nrf/pins.h
View File

@ -61,4 +61,9 @@ extern const mp_obj_type_t mcu_pin_type;
#include "nrf52840/pins.h" #include "nrf52840/pins.h"
#endif #endif
// Choose based on chip, but not specifically revision (e.g., not NRF52840_XXAA)
#ifdef NRF52833
#include "nrf52833/pins.h"
#endif
#endif // __MICROPY_INCLUDED_NRF_PERIPHERALS_PINS_H__ #endif // __MICROPY_INCLUDED_NRF_PERIPHERALS_PINS_H__

5
ports/nrf/supervisor/port.c
View File

@ -101,10 +101,15 @@ void reset_port(void) {
gamepad_reset(); gamepad_reset();
#endif #endif
#if CIRCUITPY_BUSIO
i2c_reset(); i2c_reset();
spi_reset(); spi_reset();
uart_reset(); uart_reset();
#endif
#if CIRCUITPY_NEOPIXEL_WRITE
neopixel_write_reset(); neopixel_write_reset();
#endif
#if CIRCUITPY_AUDIOBUSIO #if CIRCUITPY_AUDIOBUSIO
i2s_reset(); i2s_reset();

19
supervisor/shared/external_flash/devices.h
View File

@ -481,6 +481,25 @@ typedef struct {
.single_status_byte = true, \ .single_status_byte = true, \
} }
// Settings for the Macronix MX25R1635F 8MiB SPI flash.
// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7595/MX25R1635F,%20Wide%20Range,%2016Mb,%20v1.6.pdf
// In low power mode, quad operations can only run at 8 MHz.
#define MX25R1635F {\
.total_size = (1 << 21), /* 2 MiB */ \
.start_up_time_us = 800, \
.manufacturer_id = 0xc2, \
.memory_type = 0x28, \
.capacity = 0x18, \
.max_clock_speed_mhz = 33, /* 8 mhz for dual/quad */ \
.quad_enable_bit_mask = 0x80, \
.has_sector_protection = false, \
.supports_fast_read = true, \
.supports_qspi = true, \
.supports_qspi_writes = true, \
.write_status_register_split = false, \
.single_status_byte = true, \
}
// Settings for the Macronix MX25L51245G 64MiB SPI flash. // Settings for the Macronix MX25L51245G 64MiB SPI flash.
// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7437/MX25L51245G,%203V,%20512Mb,%20v1.6.pdf // Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7437/MX25L51245G,%203V,%20512Mb,%20v1.6.pdf
#define MX25L51245G {\ #define MX25L51245G {\