Fix SWO/Analog overlap, style changes

This commit is contained in:
Lucian Copeland 2020-05-29 12:19:37 -04:00
parent 9ee278d2ac
commit fe75c7793c
7 changed files with 17 additions and 10 deletions

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@ -33,7 +33,6 @@ void board_init(void) {
// SWD Pins
common_hal_never_reset_pin(&pin_GPIO_AD_13); //SWDIO
common_hal_never_reset_pin(&pin_GPIO_AD_12); //SWCLK
common_hal_never_reset_pin(&pin_GPIO_AD_09); //SWO
// FLEX flash
common_hal_never_reset_pin(&pin_GPIO_SD_12);
common_hal_never_reset_pin(&pin_GPIO_SD_11);

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@ -7,6 +7,10 @@
#define BOARD_FLASH_SIZE (16 * 1024 * 1024)
#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_AD_06)
#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_AD_04)
#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_AD_03)
#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_02)
#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_01)

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@ -4,9 +4,7 @@
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_08) },
@ -20,9 +18,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_AD_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_AD_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_09) },
@ -31,6 +27,16 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO_AD_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO_AD_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO_AD_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USER_SW), MP_ROM_PTR(&pin_GPIO_SD_05) },

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@ -33,7 +33,6 @@ void board_init(void) {
// SWD Pins
common_hal_never_reset_pin(&pin_GPIO_AD_B0_00);//SWDIO
common_hal_never_reset_pin(&pin_GPIO_AD_B0_01);//SWCLK
common_hal_never_reset_pin(&pin_GPIO_AD_B0_04);//SWO
// FLEX flash
common_hal_never_reset_pin(&pin_GPIO_SD_B1_06);

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@ -33,7 +33,6 @@ void board_init(void) {
// SWD Pins
common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);//SWDIO
common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);//SWCLK
common_hal_never_reset_pin(&pin_GPIO_AD_B0_10);//SWO
// FLEX flash
common_hal_never_reset_pin(&pin_GPIO_SD_B1_00);

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@ -257,8 +257,8 @@ safe_mode_t port_init(void) {
// enabled. It won't occur very often so it'll be low overhead.
NVIC_EnableIRQ(SNVS_HP_WRAPPER_IRQn);
// Note that reset_port CANNOT GO HERE, unlike other ports, since we currently rely on it to
// protect never_reset pins per board.
// Note that `reset_port` CANNOT GO HERE, unlike other ports, because `board_init` hasn't been
// run yet, which uses `never_reset` to protect critical pins from being reset by `reset_port`.
if (board_requests_safe_mode()) {
return USER_SAFE_MODE;

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@ -122,7 +122,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
#if (CPY_STM32H7 || CPY_STM32F7)
self->handle.Init.Timing = 0x40604E73; //Taken from STCube examples
#else
self->handle.Init.ClockSpeed = 100000;
self->handle.Init.ClockSpeed = frequency;
self->handle.Init.DutyCycle = I2C_DUTYCYCLE_2;
#endif