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py/asmxtensa: Fix bug with order of regs in addi encoding.

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This commit is contained in:
Damien George 2018-08-17 01:11:06 +10:00
parent f774614110
commit fd10a11c6b
1 changed files with 1 additions and 1 deletions
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py/asmxtensa.h
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@ -118,7 +118,7 @@ static inline void asm_xtensa_op_add(asm_xtensa_t *as, uint reg_dest, uint reg_s
}
static inline void asm_xtensa_op_addi(asm_xtensa_t *as, uint reg_dest, uint reg_src, int imm8) {
asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 12, reg_dest, reg_src, imm8 & 0xff));
asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 12, reg_src, reg_dest, imm8 & 0xff));
}
static inline void asm_xtensa_op_and(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {