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This commit is contained in:
jgillick 2020-03-15 19:34:41 -07:00
parent 6f153804da
commit f884c2b9b6
10 changed files with 225 additions and 419 deletions
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189
ports/stm/boards/STM32F412CGUx_FLASH.ld
View File

@ -1,189 +0,0 @@
/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : Auto-generated by System Workbench for STM32
**
** Abstract : Linker script for STM32F412CGUx series
** 1024Kbytes FLASH and 256Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20040000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

8
ports/stm/boards/thunderpack/mpconfigboard.h
View File

@ -23,7 +23,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
//Micropython setup
#define BOARD_THUNDERPACK_STM32F412
#define MICROPY_HW_BOARD_NAME "THUNDERPACK"
#define MICROPY_HW_MCU_NAME "STM32F412xGU"
@ -33,5 +33,11 @@
#define BOARD_OSC_DIV (24)
#define BOARD_NO_VBUS_SENSE (1)
#define CP_RGB_STATUS_LED
#define CP_RGB_STATUS_R (&pin_PA00)
#define CP_RGB_STATUS_G (&pin_PA01)
#define CP_RGB_STATUS_B (&pin_PA02)
#define MICROPY_HW_LED_STATUS (&pin_PA03)
#define DEFAULT_I2C_BUS_SCL (&pin_PB06)
#define DEFAULT_I2C_BUS_SDA (&pin_PB07)

9
ports/stm/boards/thunderpack/mpconfigboard.mk
View File

@ -7,16 +7,11 @@ USB_DEVICES = "CDC,MSC,HID"
INTERNAL_FLASH_FILESYSTEM = 1
LONGINT_IMPL = NONE
# QSPI_FLASH_FILESYSTEM = 1
# EXTERNAL_FLASH_DEVICE_COUNT = 1
# EXTERNAL_FLASH_DEVICES = N25Q128A
# LONGINT_IMPL = MPZ
MCU_SERIES = m4
MCU_VARIANT = stm32f4
MCU_SUB_VARIANT = stm32f412cx_thunderpack
MCU_PACKAGE = 48
CMSIS_MCU = STM32F412Zx
LD_FILE = boards/STM32F412CGUx_FLASH.ld
CMSIS_MCU = STM32F412Cx
LD_FILE = boards/STM32F412ZGTx_FLASH.ld

2
ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h
View File

@ -70,7 +70,7 @@
#define HAL_PCD_MODULE_ENABLED
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
#define HAL_QSPI_MODULE_ENABLED
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_FMPI2C_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */

3
ports/stm/peripherals/stm32f4/pins.h
View File

@ -83,6 +83,9 @@ extern const mp_obj_type_t mcu_pin_type;
#ifdef STM32F411xE
#include "stm32f411xe/pins.h"
#endif
#ifdef BOARD_THUNDERPACK_STM32F412
#include "stm32f412cx_thunderpack/pins.h"
#endif
#ifdef STM32F412Zx
#include "stm32f412zx/pins.h"
#endif

14
ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c
View File

@ -47,8 +47,8 @@ void stm32f4_peripherals_clocks_init(void) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 100;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
RCC_OscInitStruct.PLL.PLLR = 2;
@ -57,18 +57,16 @@ void stm32f4_peripherals_clocks_init(void) {
/* Select PLLSAI output as USB clock source */
PeriphClkInitStruct.PLLI2S.PLLI2SM = 12;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 3;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 72;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
* clocks dividers */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;

43
ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c
View File

@ -184,19 +184,13 @@
void stm32f4_peripherals_gpio_init(void) {
//Enable all GPIO for now
GPIO_InitTypeDef GPIO_InitStruct = {0};
// __HAL_RCC_GPIOE_CLK_ENABLE();
// __HAL_RCC_GPIOC_CLK_ENABLE();
// __HAL_RCC_GPIOF_CLK_ENABLE();
// __HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
// __HAL_RCC_GPIOG_CLK_ENABLE();
// __HAL_RCC_GPIOD_CLK_ENABLE();
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET);
//HAL_GPIO_WritePin(USB_OTGFS_PPWR_EN_GPIO_Port, USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_SET);
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
//Configure LED pins
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
@ -205,35 +199,32 @@ void stm32f4_peripherals_gpio_init(void) {
//Status LED chain
stm32f4_peripherals_status_led(0,1);
stm32f4_peripherals_status_led(1,1);
stm32f4_peripherals_status_led(2,1);
stm32f4_peripherals_status_led(3,1);
stm32f4_peripherals_status_led(1,0);
stm32f4_peripherals_status_led(2,0);
stm32f4_peripherals_status_led(3,0);
//Never reset pins
// never_reset_pin_number(2,13); //PC13 anti tamp
// never_reset_pin_number(2,14); //PC14 OSC32_IN
// never_reset_pin_number(2,15); //PC15 OSC32_OUT
never_reset_pin_number(2,13); //PC13 anti tamp
never_reset_pin_number(2,14); //PC14 OSC32_IN
never_reset_pin_number(2,15); //PC15 OSC32_OUT
never_reset_pin_number(0,13); //PA13 SWDIO
never_reset_pin_number(0,14); //PA14 SWCLK
//never_reset_pin_number(0,15); //PA15 JTDI
//never_reset_pin_number(1,3); //PB3 JTDO
//never_reset_pin_number(1,4); //PB4 JTRST
// Port H is not included in GPIO port array
// never_reset_pin_number(5,0); //PH0 JTDO
// never_reset_pin_number(5,1); //PH1 JTRST
}
void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
switch(led)
{
case 0: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, state);
case 0:
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, state);
break;
case 1: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, state);
case 1:
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, state);
break;
case 2: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, state);
case 2:
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, state);
break;
case 3: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, state);
case 3:
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, state);
break;
default: break;
}

8
ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
View File

@ -228,13 +228,13 @@ void stm32f4_peripherals_gpio_init(void) {
void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
switch(led)
{
case 0: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, (state ^ 1));
case 0: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, (state ^ 1));
break;
case 1: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, (state ^ 1));
case 1: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, (state ^ 1));
break;
case 2: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, (state ^ 1));
case 2: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, (state ^ 1));
break;
case 3: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, (state ^ 1));
case 3: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, (state ^ 1));
break;
default: break;
}

2
ports/stm/supervisor/internal_flash.h
View File

@ -42,7 +42,7 @@
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#endif
#ifdef STM32F412Zx
#if (defined(STM32F412Zx) || defined(STM32F412Cx))
#define STM32_FLASH_SIZE 0x100000 //1MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#endif

10
ports/stm/system_stm32f4xx.c
View File

@ -117,10 +117,11 @@
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\
|| defined(STM32F412Cx)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */
STM32F412Zx || STM32F412Vx || STM32F412Zx*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@ -681,7 +682,8 @@ void SystemInit_ExtMemCtl(void)
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\
|| defined(STM32F412Cx)
#if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
@ -759,7 +761,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
|| defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Cx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
/* Configure and enable Bank1_SRAM2 */