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This commit is contained in:
jgillick 2020-03-15 19:34:41 -07:00
parent 6f153804da
commit f884c2b9b6
10 changed files with 225 additions and 419 deletions
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189
ports/stm/boards/STM32F412CGUx_FLASH.ld
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@ -1,189 +0,0 @@
/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : Auto-generated by System Workbench for STM32
**
** Abstract : Linker script for STM32F412CGUx series
** 1024Kbytes FLASH and 256Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20040000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

10
ports/stm/boards/thunderpack/mpconfigboard.h
View File

@ -23,7 +23,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE. * THE SOFTWARE.
*/ */
//Micropython setup #define BOARD_THUNDERPACK_STM32F412
#define MICROPY_HW_BOARD_NAME "THUNDERPACK" #define MICROPY_HW_BOARD_NAME "THUNDERPACK"
#define MICROPY_HW_MCU_NAME "STM32F412xGU" #define MICROPY_HW_MCU_NAME "STM32F412xGU"
@ -33,5 +33,11 @@
#define BOARD_OSC_DIV (24) #define BOARD_OSC_DIV (24)
#define BOARD_NO_VBUS_SENSE (1) #define BOARD_NO_VBUS_SENSE (1)
#define CP_RGB_STATUS_LED
#define CP_RGB_STATUS_R (&pin_PA00)
#define CP_RGB_STATUS_G (&pin_PA01)
#define CP_RGB_STATUS_B (&pin_PA02)
#define MICROPY_HW_LED_STATUS (&pin_PA03)
#define DEFAULT_I2C_BUS_SCL (&pin_PB06) #define DEFAULT_I2C_BUS_SCL (&pin_PB06)
#define DEFAULT_I2C_BUS_SDA (&pin_PB07) #define DEFAULT_I2C_BUS_SDA (&pin_PB07)

9
ports/stm/boards/thunderpack/mpconfigboard.mk
View File

@ -7,16 +7,11 @@ USB_DEVICES = "CDC,MSC,HID"
INTERNAL_FLASH_FILESYSTEM = 1 INTERNAL_FLASH_FILESYSTEM = 1
LONGINT_IMPL = NONE LONGINT_IMPL = NONE
# QSPI_FLASH_FILESYSTEM = 1
# EXTERNAL_FLASH_DEVICE_COUNT = 1
# EXTERNAL_FLASH_DEVICES = N25Q128A
# LONGINT_IMPL = MPZ
MCU_SERIES = m4 MCU_SERIES = m4
MCU_VARIANT = stm32f4 MCU_VARIANT = stm32f4
MCU_SUB_VARIANT = stm32f412cx_thunderpack MCU_SUB_VARIANT = stm32f412cx_thunderpack
MCU_PACKAGE = 48 MCU_PACKAGE = 48
CMSIS_MCU = STM32F412Zx CMSIS_MCU = STM32F412Cx
LD_FILE = boards/STM32F412CGUx_FLASH.ld LD_FILE = boards/STM32F412ZGTx_FLASH.ld

2
ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h
View File

@ -70,7 +70,7 @@
#define HAL_PCD_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED
/* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */
#define HAL_QSPI_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_FMPI2C_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */

11
ports/stm/peripherals/stm32f4/pins.h
View File

@ -40,7 +40,7 @@ typedef struct {
mp_obj_base_t base; mp_obj_base_t base;
uint8_t port:4; uint8_t port:4;
uint8_t number:4; uint8_t number:4;
uint8_t adc_unit:3; uint8_t adc_unit:3;
uint8_t adc_channel:5; uint8_t adc_channel:5;
} mcu_pin_obj_t; } mcu_pin_obj_t;
@ -51,8 +51,8 @@ typedef struct {
#define ADC_3 4 #define ADC_3 4
//STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin, //STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin,
//but all 3 ADCs will share the same input number per pin. //but all 3 ADCs will share the same input number per pin.
//F4 family has 3 ADC max, 24 channels max. //F4 family has 3 ADC max, 24 channels max.
#define ADC_INPUT(mask, number) \ #define ADC_INPUT(mask, number) \
.adc_unit = mask, \ .adc_unit = mask, \
.adc_channel = number, .adc_channel = number,
@ -64,7 +64,7 @@ typedef struct {
extern const mp_obj_type_t mcu_pin_type; extern const mp_obj_type_t mcu_pin_type;
// STM32 can have up to 9 ports, each restricted to 16 pins // STM32 can have up to 9 ports, each restricted to 16 pins
// We split the pin/port evenly, in contrast to nrf. // We split the pin/port evenly, in contrast to nrf.
#define PIN(p_port, p_number, p_adc) \ #define PIN(p_port, p_number, p_adc) \
{ \ { \
{ &mcu_pin_type }, \ { &mcu_pin_type }, \
@ -83,6 +83,9 @@ extern const mp_obj_type_t mcu_pin_type;
#ifdef STM32F411xE #ifdef STM32F411xE
#include "stm32f411xe/pins.h" #include "stm32f411xe/pins.h"
#endif #endif
#ifdef BOARD_THUNDERPACK_STM32F412
#include "stm32f412cx_thunderpack/pins.h"
#endif
#ifdef STM32F412Zx #ifdef STM32F412Zx
#include "stm32f412zx/pins.h" #include "stm32f412zx/pins.h"
#endif #endif

14
ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c
View File

@ -47,8 +47,8 @@ void stm32f4_peripherals_clocks_init(void) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 200; RCC_OscInitStruct.PLL.PLLN = 100;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7; RCC_OscInitStruct.PLL.PLLQ = 7;
RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLR = 2;
@ -57,18 +57,16 @@ void stm32f4_peripherals_clocks_init(void) {
/* Select PLLSAI output as USB clock source */ /* Select PLLSAI output as USB clock source */
PeriphClkInitStruct.PLLI2S.PLLI2SM = 12; PeriphClkInitStruct.PLLI2S.PLLI2SM = 12;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 3; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 3;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 72; PeriphClkInitStruct.PLLI2S.PLLI2SN = 72;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
* clocks dividers */ * clocks dividers */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;

89
ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c
View File

@ -182,61 +182,52 @@
#include "common-hal/microcontroller/Pin.h" #include "common-hal/microcontroller/Pin.h"
void stm32f4_peripherals_gpio_init(void) { void stm32f4_peripherals_gpio_init(void) {
//Enable all GPIO for now //Enable all GPIO for now
GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitTypeDef GPIO_InitStruct = {0};
// __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();
// __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE();
// __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE();
// __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
// __HAL_RCC_GPIOG_CLK_ENABLE();
// __HAL_RCC_GPIOD_CLK_ENABLE();
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET); //Configure LED pins
//HAL_GPIO_WritePin(USB_OTGFS_PPWR_EN_GPIO_Port, USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
//Configure LED pins //Status LED chain
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; stm32f4_peripherals_status_led(0,1);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; stm32f4_peripherals_status_led(1,0);
GPIO_InitStruct.Pull = GPIO_NOPULL; stm32f4_peripherals_status_led(2,0);
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; stm32f4_peripherals_status_led(3,0);
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
//Status LED chain //Never reset pins
stm32f4_peripherals_status_led(0,1); never_reset_pin_number(2,13); //PC13 anti tamp
stm32f4_peripherals_status_led(1,1); never_reset_pin_number(2,14); //PC14 OSC32_IN
stm32f4_peripherals_status_led(2,1); never_reset_pin_number(2,15); //PC15 OSC32_OUT
stm32f4_peripherals_status_led(3,1); never_reset_pin_number(0,13); //PA13 SWDIO
never_reset_pin_number(0,14); //PA14 SWCLK
//Never reset pins
// never_reset_pin_number(2,13); //PC13 anti tamp
// never_reset_pin_number(2,14); //PC14 OSC32_IN
// never_reset_pin_number(2,15); //PC15 OSC32_OUT
never_reset_pin_number(0,13); //PA13 SWDIO
never_reset_pin_number(0,14); //PA14 SWCLK
//never_reset_pin_number(0,15); //PA15 JTDI
//never_reset_pin_number(1,3); //PB3 JTDO
//never_reset_pin_number(1,4); //PB4 JTRST
// Port H is not included in GPIO port array
// never_reset_pin_number(5,0); //PH0 JTDO
// never_reset_pin_number(5,1); //PH1 JTRST
} }
void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
switch(led) switch(led)
{ {
case 0: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, state); case 0:
break; HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, state);
case 1: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, state); break;
break; case 1:
case 2: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, state); HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, state);
break; break;
case 3: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, state); case 2:
break; HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, state);
default: break; break;
} case 3:
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, state);
break;
default: break;
}
} }

10
ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
View File

@ -220,7 +220,7 @@ void stm32f4_peripherals_gpio_init(void) {
//never_reset_pin_number(1,4); //PB4 JTRST //never_reset_pin_number(1,4); //PB4 JTRST
// Port H is not included in GPIO port array // Port H is not included in GPIO port array
// never_reset_pin_number(5,0); //PH0 JTDO // never_reset_pin_number(5,0); //PH0 JTDO
// never_reset_pin_number(5,1); //PH1 JTRST // never_reset_pin_number(5,1); //PH1 JTRST
} }
@ -228,13 +228,13 @@ void stm32f4_peripherals_gpio_init(void) {
void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
switch(led) switch(led)
{ {
case 0: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, (state ^ 1)); case 0: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, (state ^ 1));
break; break;
case 1: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, (state ^ 1)); case 1: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, (state ^ 1));
break; break;
case 2: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, (state ^ 1)); case 2: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, (state ^ 1));
break; break;
case 3: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, (state ^ 1)); case 3: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, (state ^ 1));
break; break;
default: break; default: break;
} }

2
ports/stm/supervisor/internal_flash.h
View File

@ -42,7 +42,7 @@
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#endif #endif
#ifdef STM32F412Zx #if (defined(STM32F412Zx) || defined(STM32F412Cx))
#define STM32_FLASH_SIZE 0x100000 //1MB #define STM32_FLASH_SIZE 0x100000 //1MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#endif #endif

308
ports/stm/system_stm32f4xx.c
View File

@ -1,6 +1,6 @@
/* /*
* Taken from ST Cube library and modified. See below for original header. * Taken from ST Cube library and modified. See below for original header.
* *
* Modifications copyright (c) 2019 Lucian Copeland for Adafruit Industries * Modifications copyright (c) 2019 Lucian Copeland for Adafruit Industries
* *
* Permission is hereby granted, free of charge, to any person obtaining a copy * Permission is hereby granted, free of charge, to any person obtaining a copy
@ -28,16 +28,16 @@
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
* user application: * user application:
* - SystemInit(): This function is called at startup just after reset and * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside * before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file. * the "startup_stm32f4xx.s" file.
* *
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed * be called whenever the core clock is changed
* during program execution. * during program execution.
@ -79,8 +79,8 @@
/** @addtogroup stm32f4xx_system /** @addtogroup stm32f4xx_system
* @{ * @{
*/ */
/** @addtogroup STM32F4xx_System_Private_Includes /** @addtogroup STM32F4xx_System_Private_Includes
* @{ * @{
*/ */
@ -89,7 +89,7 @@
#include "stm32f4xx.h" #include "stm32f4xx.h"
#include "py/mpconfig.h" #include "py/mpconfig.h"
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
@ -117,11 +117,12 @@
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\
|| defined(STM32F412Cx)
/* #define DATA_IN_ExtSRAM */ /* #define DATA_IN_ExtSRAM */
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */ STM32F412Zx || STM32F412Vx || STM32F412Zx*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */ /* #define DATA_IN_ExtSDRAM */
@ -131,7 +132,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
/******************************************************************************/ /******************************************************************************/
@ -153,7 +154,7 @@
/* This variable is updated in three ways: /* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate() 1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq() 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
@ -170,7 +171,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
*/ */
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void); static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/** /**
@ -183,7 +184,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory * Initialize the FPU setting, vector table location and External memory
* configuration. * configuration.
* @param None * @param None
* @retval None * @retval None
@ -214,7 +215,7 @@ void SystemInit(void)
RCC->CIR = 0x00000000; RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl(); SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/ /* Configure the Vector Table location add offset address ------------------*/
@ -232,41 +233,41 @@ void SystemInit(void)
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* *
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations * 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE * depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function * is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result. * may have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* *
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemCoreClockUpdate(void) void SystemCoreClockUpdate(void)
{ {
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
@ -282,10 +283,10 @@ void SystemCoreClockUpdate(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P SYSCLK = PLL_VCO / PLL_P
*/ */
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0) if (pllsource != 0)
{ {
/* HSE used as PLL clock source */ /* HSE used as PLL clock source */
@ -334,79 +335,79 @@ void SystemInit_ExtMemCtl(void)
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
/* Connect PDx pins to FMC Alternate function */ /* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC; GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */ /* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A; GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */ /* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF; GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */ /* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000; GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */ /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000; GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */ /* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC; GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */ /* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A; GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */ /* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF; GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */ /* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000; GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */ /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000; GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */ /* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */ /* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA; GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */ /* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA; GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */ /* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000; GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */ /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000; GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */ /* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */ /* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA; GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */ /* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA; GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */ /* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000; GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */ /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000; GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */ /* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC; GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */ /* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0; GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */ /* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0; GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */ /* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000; GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */ /* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000; GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */ /* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0; GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */ /* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA; GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */ /* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA; GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */ /* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000; GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */ /* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000; GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration -------------------------------------------------------*/ /*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */ /* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001; RCC->AHB3ENR |= 0x00000001;
@ -414,50 +415,50 @@ void SystemInit_ExtMemCtl(void)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4; FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351; FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */ /* SDRAM initialization sequence */
/* Clock enable command */ /* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011; FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Delay */ /* Delay */
for (index = 0; index<1000; index++); for (index = 0; index<1000; index++);
/* PALL command */ /* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012; FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Auto refresh command */ /* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073; FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* MRD register program */ /* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014; FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Set refresh count */ /* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR; tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */ /* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0]; tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
@ -465,7 +466,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff; FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx) #if defined(STM32F469xx) || defined(STM32F479xx)
/* Configure and enable Bank1_SRAM2 */ /* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091; FMC_Bank1->BTCR[2] = 0x00001091;
@ -473,7 +474,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1E->BWTR[2] = 0x0fffffff; FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */ #endif /* STM32F469xx || STM32F479xx */
(void)(tmp); (void)(tmp);
} }
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
@ -499,13 +500,13 @@ void SystemInit_ExtMemCtl(void)
clock */ clock */
RCC->AHB1ENR |= 0x0000007D; RCC->AHB1ENR |= 0x0000007D;
#else #else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */ clock */
RCC->AHB1ENR |= 0x000001F8; RCC->AHB1ENR |= 0x000001F8;
#endif /* STM32F446xx */ #endif /* STM32F446xx */
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx) #if defined(STM32F446xx)
/* Connect PAx pins to FMC Alternate function */ /* Connect PAx pins to FMC Alternate function */
GPIOA->AFR[0] |= 0xC0000000; GPIOA->AFR[0] |= 0xC0000000;
@ -535,78 +536,78 @@ void SystemInit_ExtMemCtl(void)
/* Connect PDx pins to FMC Alternate function */ /* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC; GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */ /* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A; GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */ /* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A; GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */ /* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000; GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */ /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000; GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */ /* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC; GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */ /* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A; GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */ /* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A; GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */ /* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000; GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */ /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000; GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */ /* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */ /* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA; GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */ /* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA; GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */ /* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000; GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */ /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000; GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */ /* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */ /* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA; GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */ /* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA; GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */ /* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000; GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */ /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000; GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */ /* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC; GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */ /* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0; GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */ /* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0; GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */ /* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000; GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */ /* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000; GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */ /* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0; GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */ /* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA; GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */ /* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA; GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */ /* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000; GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */ /* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000; GPIOI->PUPDR = 0x00000000;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*-- FMC Configuration -------------------------------------------------------*/ /*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */ /* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001; RCC->AHB3ENR |= 0x00000001;
@ -616,72 +617,73 @@ void SystemInit_ExtMemCtl(void)
/* Configure and enable SDRAM bank1 */ /* Configure and enable SDRAM bank1 */
#if defined(STM32F446xx) #if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954; FMC_Bank5_6->SDCR[0] = 0x00001954;
#else #else
FMC_Bank5_6->SDCR[0] = 0x000019E4; FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif /* STM32F446xx */ #endif /* STM32F446xx */
FMC_Bank5_6->SDTR[0] = 0x01115351; FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */ /* SDRAM initialization sequence */
/* Clock enable command */ /* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011; FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Delay */ /* Delay */
for (index = 0; index<1000; index++); for (index = 0; index<1000; index++);
/* PALL command */ /* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012; FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Auto refresh command */ /* Auto refresh command */
#if defined(STM32F446xx) #if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3; FMC_Bank5_6->SDCMR = 0x000000F3;
#else #else
FMC_Bank5_6->SDCMR = 0x00000073; FMC_Bank5_6->SDCMR = 0x00000073;
#endif /* STM32F446xx */ #endif /* STM32F446xx */
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* MRD register program */ /* MRD register program */
#if defined(STM32F446xx) #if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014; FMC_Bank5_6->SDCMR = 0x00044014;
#else #else
FMC_Bank5_6->SDCMR = 0x00046014; FMC_Bank5_6->SDCMR = 0x00046014;
#endif /* STM32F446xx */ #endif /* STM32F446xx */
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Set refresh count */ /* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR; tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx) #if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else #else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif /* STM32F446xx */ #endif /* STM32F446xx */
/* Disable write protection */ /* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0]; tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\
|| defined(STM32F412Cx)
#if defined(DATA_IN_ExtSRAM) #if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/ /*-- GPIOs Configuration -----------------------------------------------------*/
@ -689,55 +691,55 @@ void SystemInit_ExtMemCtl(void)
RCC->AHB1ENR |= 0x00000078; RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
/* Connect PDx pins to FMC Alternate function */ /* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC; GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */ /* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A; GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */ /* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF; GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */ /* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000; GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */ /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000; GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */ /* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC; GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */ /* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A; GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */ /* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF; GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */ /* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000; GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */ /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000; GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */ /* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC; GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000; GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */ /* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA; GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */ /* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF; GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */ /* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000; GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */ /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000; GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */ /* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC; GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0; GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */ /* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA; GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */ /* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF; GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */ /* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000; GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */ /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000; GPIOG->PUPDR = 0x00000000;
/*-- FMC/FSMC Configuration --------------------------------------------------*/ /*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */ /* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001; RCC->AHB3ENR |= 0x00000001;
@ -749,7 +751,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff; FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx) #if defined(STM32F469xx) || defined(STM32F479xx)
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
@ -759,7 +761,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1E->BWTR[2] = 0x0fffffff; FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */ #endif /* STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Cx)
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
/* Configure and enable Bank1_SRAM2 */ /* Configure and enable Bank1_SRAM2 */
@ -770,8 +772,8 @@ void SystemInit_ExtMemCtl(void)
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(void)(tmp); (void)(tmp);
} }
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/** /**