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Changed the order of SPI configuration and activation.

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SPI should be configured while chip select pin is disabled.
Tested with external flash on STM32 F4VE board.
This commit is contained in:
EmergReanimator 2022-01-29 18:29:50 +01:00
parent 80611954f4
commit f610b6b190
1 changed files with 2 additions and 2 deletions
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4
supervisor/shared/external_flash/spi_flash.c
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@ -105,12 +105,12 @@ bool spi_flash_sector_command(uint8_t command, uint32_t address) {
bool spi_flash_write_data(uint32_t address, uint8_t *data, uint32_t data_length) {
uint8_t request[4] = {CMD_PAGE_PROGRAM, 0x00, 0x00, 0x00};
common_hal_busio_spi_configure(&supervisor_flash_spi_bus, spi_flash_baudrate, 0, 0, 8);
// Write the SPI flash write address into the bytes following the command byte.
address_to_bytes(address, request + 1);
if (!flash_enable()) {
return false;
}
common_hal_busio_spi_configure(&supervisor_flash_spi_bus, spi_flash_baudrate, 0, 0, 8);
bool status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, request, 4);
if (status) {
status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, data, data_length);
@ -126,12 +126,12 @@ bool spi_flash_read_data(uint32_t address, uint8_t *data, uint32_t data_length)
request[0] = CMD_FAST_READ_DATA;
command_length = 5;
}
common_hal_busio_spi_configure(&supervisor_flash_spi_bus, spi_flash_baudrate, 0, 0, 8);
// Write the SPI flash read address into the bytes following the command byte.
address_to_bytes(address, request + 1);
if (!flash_enable()) {
return false;
}
common_hal_busio_spi_configure(&supervisor_flash_spi_bus, spi_flash_baudrate, 0, 0, 8);
bool status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, request, command_length);
if (status) {
status = common_hal_busio_spi_read(&supervisor_flash_spi_bus, data, data_length, 0xff);