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Merge pull request #2286 from hierophect/stm32-speedy-405 

STM32: Raise clock speed of F405
This commit is contained in:
Dan Halbert 2019-11-15 11:25:29 -05:00 committed by GitHub
parent 4c55431bb3 6e96b1945e
commit f3038e53d1
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 3 deletions
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6
ports/stm32f4/peripherals/stm32f4/stm32f405xx/clocks.c
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@ -48,7 +48,7 @@ void stm32f4_peripherals_clocks_init(void) {
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
@ -57,7 +57,7 @@ void stm32f4_peripherals_clocks_init(void) {
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
}