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spresense: empty rx uart fifo after initialization

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This commit is contained in:
Kamil Tomaszewski 2021-03-15 16:13:39 +01:00
parent 22ed0abf6c
commit ed3f636be5
1 changed files with 11 additions and 0 deletions
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11
ports/cxd56/common-hal/busio/UART.c
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@ -59,6 +59,9 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop,
mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer,
bool sigint_enabled) {
int i;
int count;
char tmp;
struct termios tio;
if ((rts != NULL) || (cts != NULL) || (rs485_dir != NULL) || (rs485_invert)) {
@ -96,6 +99,14 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
if (busio_uart_dev[self->number].fd < 0) {
mp_raise_ValueError(translate("Could not initialize UART"));
}
// Wait to make sure the UART is ready
usleep(1000);
// Clear RX FIFO
ioctl(busio_uart_dev[self->number].fd, FIONREAD, (long unsigned int)&count);
for (i = 0; i < count; i++) {
read(busio_uart_dev[self->number].fd, &tmp, 1);
}
}
ioctl(busio_uart_dev[self->number].fd, TCGETS, (long unsigned int)&tio);