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stm32/boards/STM32F769DISC: Enable lwIP and Ethernet peripheral.

This commit is contained in:
Damien George 2019-02-22 22:27:48 +11:00
parent b3513f54d3
commit ed0a530614
2 changed files with 22 additions and 0 deletions
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13
ports/stm32/boards/STM32F769DISC/mpconfigboard.h
View File

@ -5,6 +5,8 @@
#define MICROPY_HW_BOARD_NAME "F769DISC"
#define MICROPY_HW_MCU_NAME "STM32F769"
#define MICROPY_PY_LWIP (1)
#define MICROPY_HW_HAS_SWITCH (1)
#define MICROPY_HW_HAS_FLASH (1)
#define MICROPY_HW_HAS_SDCARD (1)
@ -76,6 +78,17 @@
// USB config (CN15 - USB OTG HS with external PHY)
#define MICROPY_HW_USB_HS (1)
// Ethernet via RMII
#define MICROPY_HW_ETH_MDC (pin_C1)
#define MICROPY_HW_ETH_MDIO (pin_A2)
#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1)
#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7)
#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4)
#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5)
#define MICROPY_HW_ETH_RMII_TX_EN (pin_G11)
#define MICROPY_HW_ETH_RMII_TXD0 (pin_G13)
#define MICROPY_HW_ETH_RMII_TXD1 (pin_G14)
#if 0
// Optional SDRAM configuration; requires SYSCLK <= 200MHz
#define MICROPY_HW_SDRAM_SIZE (128 * 1024 * 1024 / 8) // 128 Mbit

9
ports/stm32/boards/STM32F769DISC/pins.csv
View File

@ -69,6 +69,15 @@ UART5_TX,PC12
UART5_RX,PD2
CAN2_TX,PB13
CAN2_RX,PB12
ETH_REF_CLK,PA1
ETH_MDIO,PA2
ETH_CRS_DV,PA7
ETH_MDC,PC1
ETH_RXD0,PC4
ETH_RXD1,PC5
ETH_TX_EN,PG11
ETH_TXD0,PG13
ETH_TXD1,PG14
FMC_SDCKE0,PH2
FMC_SDNE0,PH3
FMC_SDCLK,PG8

1 A0 PA0
69 UART5_RX PD2
70 CAN2_TX PB13
71 CAN2_RX PB12
72 ETH_REF_CLK PA1
73 ETH_MDIO PA2
74 ETH_CRS_DV PA7
75 ETH_MDC PC1
76 ETH_RXD0 PC4
77 ETH_RXD1 PC5
78 ETH_TX_EN PG11
79 ETH_TXD0 PG13
80 ETH_TXD1 PG14
81 FMC_SDCKE0 PH2
82 FMC_SDNE0 PH3
83 FMC_SDCLK PG8