From eca4115f666f8b5e1e0155ce930353b698dcd7ef Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 3 Jul 2019 00:48:19 +1000 Subject: [PATCH] stm32/sdram: Use MPU helper functions to configure MPU for SDRAM use. --- ports/stm32/mpu.h | 14 ++++++++++++++ ports/stm32/sdram.c | 41 +++++------------------------------------ 2 files changed, 19 insertions(+), 36 deletions(-) diff --git a/ports/stm32/mpu.h b/ports/stm32/mpu.h index c0cd2108c1..c5881d8fde 100644 --- a/ports/stm32/mpu.h +++ b/ports/stm32/mpu.h @@ -29,6 +29,8 @@ #if defined(STM32F7) || defined(STM32H7) #define MPU_REGION_ETH (MPU_REGION_NUMBER0) +#define MPU_REGION_SDRAM1 (MPU_REGION_NUMBER4) +#define MPU_REGION_SDRAM2 (MPU_REGION_NUMBER5) #define MPU_CONFIG_DISABLE(srd, size) ( \ MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \ @@ -54,6 +56,18 @@ | MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \ ) +#define MPU_CONFIG_SDRAM(size) ( \ + MPU_INSTRUCTION_ACCESS_ENABLE << MPU_RASR_XN_Pos \ + | MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos \ + | MPU_TEX_LEVEL1 << MPU_RASR_TEX_Pos \ + | MPU_ACCESS_NOT_SHAREABLE << MPU_RASR_S_Pos \ + | MPU_ACCESS_CACHEABLE << MPU_RASR_C_Pos \ + | MPU_ACCESS_BUFFERABLE << MPU_RASR_B_Pos \ + | 0x00 << MPU_RASR_SRD_Pos \ + | (size) << MPU_RASR_SIZE_Pos \ + | MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \ + ) + static inline void mpu_init(void) { MPU->CTRL = MPU_PRIVILEGED_DEFAULT | MPU_CTRL_ENABLE_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; diff --git a/ports/stm32/sdram.c b/ports/stm32/sdram.c index b3c5bbeeed..5d54dc2cb3 100644 --- a/ports/stm32/sdram.c +++ b/ports/stm32/sdram.c @@ -13,6 +13,7 @@ #include "py/mphal.h" #include "pin.h" #include "pin_static_af.h" +#include "mpu.h" #include "systick.h" #include "sdram.h" @@ -244,45 +245,13 @@ static void sdram_init_seq(SDRAM_HandleTypeDef #if defined(STM32F7) /* Enable MPU for the SDRAM Memory Region to allow non-aligned accesses (hard-fault otherwise) - */ - - MPU_Region_InitTypeDef MPU_InitStruct; - - /* Disable the MPU */ - HAL_MPU_Disable(); - - /* Configure the MPU attributes for External SDRAM Initially disable all access for the entire SDRAM memory space, then enable access/caching for the size used */ - MPU_InitStruct.Enable = MPU_REGION_ENABLE; - MPU_InitStruct.Number = MPU_REGION_NUMBER4; - MPU_InitStruct.BaseAddress = SDRAM_START_ADDRESS; - MPU_InitStruct.Size = MPU_REGION_SIZE_512MB; - MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; - MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; - MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; - MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; - MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; - MPU_InitStruct.SubRegionDisable = 0x00; - MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; - HAL_MPU_ConfigRegion(&MPU_InitStruct); - - MPU_InitStruct.Enable = MPU_REGION_ENABLE; - MPU_InitStruct.Number = MPU_REGION_NUMBER5; - MPU_InitStruct.BaseAddress = SDRAM_START_ADDRESS; - MPU_InitStruct.Size = SDRAM_MPU_REGION_SIZE; - MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; - MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; - MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; - MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; - MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; - MPU_InitStruct.SubRegionDisable = 0x00; - MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; - HAL_MPU_ConfigRegion(&MPU_InitStruct); - - /* Enable the MPU */ - HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + mpu_config_start(); + mpu_config_region(MPU_REGION_SDRAM1, SDRAM_START_ADDRESS, MPU_CONFIG_DISABLE(0x00, MPU_REGION_SIZE_512MB)); + mpu_config_region(MPU_REGION_SDRAM2, SDRAM_START_ADDRESS, MPU_CONFIG_SDRAM(SDRAM_MPU_REGION_SIZE)); + mpu_config_end(); #endif }