djsundog
/
circuitpython
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Support cached internal flash on the H743

This commit is contained in:
Lucian Copeland 2020-03-28 18:30:46 -04:00
parent 7995bcac40
commit e2be069686
13 changed files with 483 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
ports/stm/Makefile
View File

@ -187,10 +187,7 @@ SRC_STM32 = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_,\
ll_rcc.c \
ll_utils.c \
ll_exti.c \
)
#removed:
# hal_flash_ramfunc.c \
# ll_fsmc.c \
)
SRC_STM32 += system_stm32$(MCU_SERIES_LOWER)xx.c

0
ports/stm/boards/stm32h743zi_discovery/board.c → ports/stm/boards/stm32h743zi2_discovery/board.c
View File

0
ports/stm/boards/stm32h743zi_discovery/mpconfigboard.h → ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.h
View File

4
ports/stm/boards/stm32h743zi_discovery/mpconfigboard.mk → ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.mk
View File

@ -2,9 +2,9 @@ USB_VID = 0x239A #REPLACE
USB_PID = 0x808A #REPLACE
USB_PRODUCT = "STM32H743ZI Discovery Board - CPy"
USB_MANUFACTURER = "STMicroelectronics"
USB_DEVICES = "CDC,HID"
USB_DEVICES = "CDC,MSC"
DISABLE_FILESYSTEM = 1
INTERNAL_FLASH_FILESYSTEM = 1
MCU_SERIES = H7
MCU_VARIANT = STM32H743xx

2
ports/stm/boards/stm32h743zi_discovery/pins.c → ports/stm/boards/stm32h743zi2_discovery/pins.c
View File

@ -86,7 +86,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
{ MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) },
{ MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) },
{ MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) },
{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) },
{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PE01) },
{ MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) },
{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) },
{ MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) },

0
ports/stm/boards/stm32h743zi_discovery/stm32h7xx_hal_conf.h → ports/stm/boards/stm32h743zi2_discovery/stm32h7xx_hal_conf.h
View File

11
ports/stm/peripherals/periph.h
View File

@ -33,12 +33,12 @@
#include STM32_HAL_H
#include "pins.h"
// PERIPH
// Comm Peripherals
typedef struct {
uint8_t periph_index:4; // Index of the I2C unit (1 to 3)
uint8_t altfn_index:4; //Index of the altfn for this pin (0 to 15)
const mcu_pin_obj_t * pin;
uint8_t periph_index:4; // Index of the peripheral instance
uint8_t altfn_index:4; // Index of the altfn for this pin (0 to 15)
const mcu_pin_obj_t * pin; // Pin Object
} mcu_periph_obj_t;
#define PERIPH(index, alt, p_pin) \
@ -48,7 +48,8 @@ typedef struct {
.pin = p_pin, \
}
//Timers
// Timer Peripheral
typedef struct {
uint8_t tim_index:4;
uint8_t altfn_index:4;

237
ports/stm/supervisor/internal_flash.c
View File

@ -4,7 +4,7 @@
* The MIT License (MIT)
*
* Copyright (c) 2013, 2014 Damien P. George
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -35,6 +35,7 @@
#include "py/obj.h"
#include "py/runtime.h"
#include "lib/oofatfs/ff.h"
#include "supervisor/shared/safe_mode.h"
typedef struct {
uint32_t base_address;
@ -46,7 +47,9 @@ typedef struct {
/* Internal Flash API
*------------------------------------------------------------------*/
static const flash_layout_t flash_layout[] = {
#if defined(STM32F4)
STATIC const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x04000, 4 },
{ 0x08010000, 0x10000, 1 },
{ 0x08020000, 0x20000, 3 },
@ -59,12 +62,45 @@ static const flash_layout_t flash_layout[] = {
{ 0x08120000, 0x20000, 7 },
#endif
};
STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4)));
#elif defined(STM32H7)
STATIC const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x20000, 16 },
};
STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4)));
#else
#error Unsupported processor
#endif
#define NO_CACHE 0xffffffff
#define MAX_CACHE 0x4000
static uint8_t _flash_cache[0x4000] __attribute__((aligned(4)));
static uint32_t _cache_flash_addr = NO_CACHE;
STATIC uint32_t _cache_flash_addr = NO_CACHE;
#if defined(STM32H7)
// get the bank of a given flash address
STATIC uint32_t get_bank(uint32_t addr) {
if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK) == 0) {
// no bank swap
if (addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
return FLASH_BANK_1;
} else {
return FLASH_BANK_2;
}
} else {
// bank swap
if (addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
return FLASH_BANK_2;
} else {
return FLASH_BANK_1;
}
}
}
#endif
//Return the sector of a given flash address.
uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) {
@ -105,51 +141,99 @@ uint32_t supervisor_flash_get_block_count(void) {
void supervisor_flash_flush(void) {
if (_cache_flash_addr == NO_CACHE) return;
#if defined(STM32H7)
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK2);
#else
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
#endif
// set up for erase
FLASH_EraseInitTypeDef EraseInitStruct;
EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V
// get the sector information
uint32_t sector_size;
uint32_t sector_start_addr;
#if defined(STM32H7)
EraseInitStruct.Banks = get_bank(_cache_flash_addr);
#endif
EraseInitStruct.Sector = flash_get_sector_info(_cache_flash_addr, &sector_start_addr, &sector_size);
EraseInitStruct.NbSectors = 1;
if (sector_size > sizeof(_flash_cache)) {
__ASM volatile ("bkpt");
mp_printf(&mp_plat_print, "FLASH ERR: invalid sector\n");
reset_into_safe_mode(FLASH_WRITE_FAIL);
}
// Skip if data is the same
if (memcmp(_flash_cache, (void *)_flash_page_addr, FLASH_PAGE_SIZE) != 0) {
if (memcmp(_flash_cache, (void *)_cache_flash_addr, sector_size) != 0) {
// unlock flash
HAL_FLASH_Unlock();
// set up for erase
FLASH_EraseInitTypeDef EraseInitStruct;
EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V
// get the sector information
uint32_t sector_size;
uint32_t sector_start_addr;
EraseInitStruct.Sector = flash_get_sector_info(_cache_flash_addr, &sector_start_addr, &sector_size);
EraseInitStruct.NbSectors = 1;
if (sector_size>0x4000) return false;
// erase the sector
uint32_t SectorError = 0;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) {
// error occurred during sector erase
HAL_FLASH_Lock(); // lock the flash
mp_printf(&mp_plat_print, "FLASH SECTOR ERASE ERROR");
return false;
__ASM volatile ("bkpt");
mp_printf(&mp_plat_print, "FLASH ERR: erase failure\n");
reset_into_safe_mode(FLASH_WRITE_FAIL);
}
__HAL_FLASH_DATA_CACHE_DISABLE();
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
// __HAL_FLASH_DATA_CACHE_DISABLE();
// __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
__HAL_FLASH_DATA_CACHE_RESET();
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
// __HAL_FLASH_DATA_CACHE_RESET();
// __HAL_FLASH_INSTRUCTION_CACHE_RESET();
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
__HAL_FLASH_DATA_CACHE_ENABLE();
// __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
// __HAL_FLASH_DATA_CACHE_ENABLE();
// reprogram the sector
for (uint32_t i = 0; i < sector_size; i++) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)_flash_cache[i]) != HAL_OK) {
// // reprogram the sector
// for (uint32_t i = 0; i < sector_size; i++) {
// if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)_flash_cache[i]) != HAL_OK) {
// // error occurred during flash write
// HAL_FLASH_Lock(); // lock the flash
// mp_printf(&mp_plat_print, "FLASH WRITE ERROR");
// }
// sector_start_addr += 1;
// }
uint32_t * cache_addr = (uint32_t*)_flash_cache;
#if defined(STM32H7)
for (uint32_t i = 0; i < (sector_size / 32); i++) {
// Note that the STM32H7 HAL interface differs by taking an address, not 64 bit data
// This is because ST's code is written by a large room of chimpanzees
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, sector_start_addr,
(uint32_t)cache_addr) != HAL_OK) {
// error occurred during flash write
HAL_FLASH_Lock(); // lock the flash
mp_printf(&mp_plat_print, "FLASH WRITE ERROR");
return false;
__ASM volatile ("bkpt");
reset_into_safe_mode(FLASH_WRITE_FAIL);
}
sector_start_addr += 1;
// RAM memory is by word (4 byte), but flash memory is by byte
cache_addr += 8;
sector_start_addr += 32;
}
#else // STM32F4
// program the flash word by word
for (uint32_t i = 0; i < sector_size / 4; i++) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, sector_start_addr,
(uint64_t)*cache_addr) != HAL_OK) {
// error occurred during flash write
HAL_FLASH_Lock(); // lock the flash
__ASM volatile ("bkpt");
reset_into_safe_mode(FLASH_WRITE_FAIL);
}
// RAM memory is by word (4 byte), but flash memory is by byte
cache_addr += 1;
sector_start_addr += 4;
}
#endif
// lock the flash
HAL_FLASH_Lock();
}
@ -165,6 +249,9 @@ static int32_t convert_block_to_flash_addr(uint32_t block) {
}
mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) {
// Must write out anything in cache before trying to read.
supervisor_flash_flush();
int32_t src = convert_block_to_flash_addr(block);
if (src == -1) {
// bad block number
@ -174,88 +261,12 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n
return 0; // success
}
bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) {
int32_t dest = convert_block_to_flash_addr(block);
if (dest == -1) {
// bad block number
mp_printf(&mp_plat_print, "BAD FLASH BLOCK ERROR");
return false;
}
// unlock flash
HAL_FLASH_Unlock();
// set up for erase
FLASH_EraseInitTypeDef EraseInitStruct;
EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V
// get the sector information
uint32_t sector_size;
uint32_t sector_start_addr;
EraseInitStruct.Sector = flash_get_sector_info(dest, &sector_start_addr, &sector_size);
EraseInitStruct.NbSectors = 1;
if (sector_size>0x4000) return false;
// copy the sector
memcpy(sector_copy,(void *)sector_start_addr,sector_size);
// // overwrite sector data
memcpy(sector_copy+(dest-sector_start_addr),src,FILESYSTEM_BLOCK_SIZE);
// find end address, subtract for number of sectors
// Shouldn't be required since blocks will always fit in a single sector, they should never overlap
//EraseInitStruct.NbSectors = flash_get_sector_info(dest + FILESYSTEM_BLOCK_SIZE - 1, NULL, NULL) - EraseInitStruct.Sector + 1;
// erase the sector
uint32_t SectorError = 0;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) {
// error occurred during sector erase
HAL_FLASH_Lock(); // lock the flash
mp_printf(&mp_plat_print, "FLASH SECTOR ERASE ERROR");
return false;
}
__HAL_FLASH_DATA_CACHE_DISABLE();
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
__HAL_FLASH_DATA_CACHE_RESET();
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
__HAL_FLASH_DATA_CACHE_ENABLE();
// reprogram the sector
for (uint32_t i = 0; i < sector_size; i++) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)sector_copy[i]) != HAL_OK) {
// error occurred during flash write
HAL_FLASH_Lock(); // lock the flash
mp_printf(&mp_plat_print, "FLASH WRITE ERROR");
return false;
}
sector_start_addr += 1;
}
// lock the flash
HAL_FLASH_Lock();
return true;
}
// mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) {
// for (size_t i = 0; i < num_blocks; i++) {
// if (!supervisor_flash_write_block(src + i * FILESYSTEM_BLOCK_SIZE, block_num + i)) {
// return 1; // error
// }
// }
// return 0; // success
// }
mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) {
while (num_blocks) {
int32_t dest = convert_block_to_flash_addr(block);
int32_t dest = convert_block_to_flash_addr(block_num);
if (dest == -1) {
// bad block number
__ASM volatile ("bkpt");
mp_printf(&mp_plat_print, "BAD FLASH BLOCK ERROR");
return false;
}
@ -263,14 +274,20 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num,
// unlock flash
HAL_FLASH_Unlock();
uint32_t sector_size;
uint32_t sector_start_addr;
flash_get_sector_info(dest, &sector_start_addr, &sector_size);
// Fail for any sector outside the 16k ones for now
if (sector_size > 0x4000) return false;
if (sector_size > sizeof(_flash_cache)) {
__ASM volatile ("bkpt");
mp_printf(&mp_plat_print, "FLASH ERR: invalid sector\n");
reset_into_safe_mode(FLASH_WRITE_FAIL);
}
// Find how many blocks are left in the sector
uint32_t count = (sector_size - (dest - sector_start_addr))/FILESYSTEM_BLOCK_SIZE;
count = MIN(num_blocks, count); `
count = MIN(num_blocks, count);
if (_cache_flash_addr != sector_start_addr) {
// Write out anything in cache before overwriting it.

28
ports/stm/supervisor/internal_flash.h
View File

@ -4,7 +4,7 @@
* The MIT License (MIT)
*
* Copyright (c) 2013, 2014 Damien P. George
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
* Copyright (c) 2020 Lucian Copeland for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -24,8 +24,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_STM32F4_INTERNAL_FLASH_H
#define MICROPY_INCLUDED_STM32F4_INTERNAL_FLASH_H
#ifndef MICROPY_INCLUDED_STM32_INTERNAL_FLASH_H
#define MICROPY_INCLUDED_STM32_INTERNAL_FLASH_H
#include <stdbool.h>
#include <stdint.h>
@ -35,6 +35,8 @@
#ifdef STM32F401xE
#define STM32_FLASH_SIZE 0x80000 //512KiB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)
#endif
#ifdef STM32F411xE
@ -43,30 +45,42 @@
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x8000 //32KiB
#else
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)
#endif
#endif
#ifdef STM32F412Zx
#define STM32_FLASH_SIZE 0x100000 //1MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)
#endif
#ifdef STM32F405xx
#define STM32_FLASH_SIZE 0x100000 //1MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)
#endif
#ifdef STM32F407xx
#define STM32_FLASH_SIZE 0x100000 //1MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)
#endif
#ifdef STM32H743xx
#define STM32_FLASH_SIZE 0x200000 //2MB
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x20000 //128KiB
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08020000
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)
#endif
#define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)
#define INTERNAL_FLASH_SYSTICK_MASK (0x1ff) // 512ms
#define INTERNAL_FLASH_IDLE_TICK(tick) (((tick) & INTERNAL_FLASH_SYSTICK_MASK) == 2)
#endif // MICROPY_INCLUDED_STM32F4_INTERNAL_FLASH_H
#endif // MICROPY_INCLUDED_STM32_INTERNAL_FLASH_H

130
ports/stm/tools/examples/nucleo_h743.csv Normal file
View File

@ -0,0 +1,130 @@
A0,PA3
A1,PC0
A2,PC3
A3,PB1
A4,PC2
A5,PF10
A6,PF4
A7,PF5
A8,PF6
D0,PB7
D1,PB6
D2,PG14
D3,PE13
D4,PE14
D5,PE11
D6,PE9
D7,PG12
D8,PF3
D9,PD15
D10,PD14
D11,PB5
D12,PA6
D13,PA7
D14,PB9
D15,PB8
D16,PC6
D17,PB15
D18,PB13
D19,PB12
D20,PA15
D21,PC7
D22,PB5
D23,PB3
D24,PA4
D25,PB4
D26,PG6
D27,PB2
D28,PD13
D29,PD12
D30,PD11
D31,PE2
D32,PA0
D33,PB0
D34,PE0
D35,PB11
D36,PB10
D37,PE15
D38,PE6
D39,PE12
D40,PE10
D41,PE7
D42,PE8
D43,PC8
D44,PC9
D45,PC10
D46,PC11
D47,PC12
D48,PD2
D49,PG2
D50,PG3
D51,PD7
D52,PD6
D53,PD5
D54,PD4
D55,PD3
D56,PE2
D57,PE4
D58,PE5
D59,PE6
D60,PE3
D61,PF8
D62,PF7
D63,PF9
D64,PG1
D65,PG0
D66,PD1
D67,PD0
D68,PF0
D69,PF1
D70,PF2
D71,PE9
D72,PB2
DAC1,PA4
DAC2,PA5
LED1,PB0
LED2,PB7
LED3,PB14
SW,PC13
I2C1_SDA,PB9
I2C1_SCL,PB8
I2C2_SDA,PF0
I2C2_SCL,PF1
I2C4_SCL,PF14
I2C4_SDA,PF15
SD_D0,PC8
SD_D1,PC9
SD_D2,PC10
SD_D3,PC11
SD_CMD,PD2
SD_CK,PC12
SD_SW,PG2
OTG_FS_POWER,PG6
OTG_FS_OVER_CURRENT,PG7
USB_VBUS,PA9
USB_ID,PA10
USB_DM,PA11
USB_DP,PA12
UART2_TX,PD5
UART2_RX,PD6
UART2_RTS,PD4
UART2_CTS,PD3
UART3_TX,PD8
UART3_RX,PD9
UART5_TX,PB6
UART5_RX,PB12
UART6_TX,PC6
UART6_RX,PC7
UART7_TX,PF7
UART7_RX,PF6
UART8_TX,PE1
UART8_RX,PE0
ETH_MDC,PC1
ETH_MDIO,PA2
ETH_RMII_REF_CLK,PA1
ETH_RMII_CRS_DV,PA7
ETH_RMII_RXD0,PC4
ETH_RMII_RXD1,PC5
ETH_RMII_TX_EN,PG11
ETH_RMII_TXD0,PG13
ETH_RMII_TXD1,PB13
1 A0 PA3
2 A1 PC0
3 A2 PC3
4 A3 PB1
5 A4 PC2
6 A5 PF10
7 A6 PF4
8 A7 PF5
9 A8 PF6
10 D0 PB7
11 D1 PB6
12 D2 PG14
13 D3 PE13
14 D4 PE14
15 D5 PE11
16 D6 PE9
17 D7 PG12
18 D8 PF3
19 D9 PD15
20 D10 PD14
21 D11 PB5
22 D12 PA6
23 D13 PA7
24 D14 PB9
25 D15 PB8
26 D16 PC6
27 D17 PB15
28 D18 PB13
29 D19 PB12
30 D20 PA15
31 D21 PC7
32 D22 PB5
33 D23 PB3
34 D24 PA4
35 D25 PB4
36 D26 PG6
37 D27 PB2
38 D28 PD13
39 D29 PD12
40 D30 PD11
41 D31 PE2
42 D32 PA0
43 D33 PB0
44 D34 PE0
45 D35 PB11
46 D36 PB10
47 D37 PE15
48 D38 PE6
49 D39 PE12
50 D40 PE10
51 D41 PE7
52 D42 PE8
53 D43 PC8
54 D44 PC9
55 D45 PC10
56 D46 PC11
57 D47 PC12
58 D48 PD2
59 D49 PG2
60 D50 PG3
61 D51 PD7
62 D52 PD6
63 D53 PD5
64 D54 PD4
65 D55 PD3
66 D56 PE2
67 D57 PE4
68 D58 PE5
69 D59 PE6
70 D60 PE3
71 D61 PF8
72 D62 PF7
73 D63 PF9
74 D64 PG1
75 D65 PG0
76 D66 PD1
77 D67 PD0
78 D68 PF0
79 D69 PF1
80 D70 PF2
81 D71 PE9
82 D72 PB2
83 DAC1 PA4
84 DAC2 PA5
85 LED1 PB0
86 LED2 PB7
87 LED3 PB14
88 SW PC13
89 I2C1_SDA PB9
90 I2C1_SCL PB8
91 I2C2_SDA PF0
92 I2C2_SCL PF1
93 I2C4_SCL PF14
94 I2C4_SDA PF15
95 SD_D0 PC8
96 SD_D1 PC9
97 SD_D2 PC10
98 SD_D3 PC11
99 SD_CMD PD2
100 SD_CK PC12
101 SD_SW PG2
102 OTG_FS_POWER PG6
103 OTG_FS_OVER_CURRENT PG7
104 USB_VBUS PA9
105 USB_ID PA10
106 USB_DM PA11
107 USB_DP PA12
108 UART2_TX PD5
109 UART2_RX PD6
110 UART2_RTS PD4
111 UART2_CTS PD3
112 UART3_TX PD8
113 UART3_RX PD9
114 UART5_TX PB6
115 UART5_RX PB12
116 UART6_TX PC6
117 UART6_RX PC7
118 UART7_TX PF7
119 UART7_RX PF6
120 UART8_TX PE1
121 UART8_RX PE0
122 ETH_MDC PC1
123 ETH_MDIO PA2
124 ETH_RMII_REF_CLK PA1
125 ETH_RMII_CRS_DV PA7
126 ETH_RMII_RXD0 PC4
127 ETH_RMII_RXD1 PC5
128 ETH_RMII_TX_EN PG11
129 ETH_RMII_TXD0 PG13
130 ETH_RMII_TXD1 PB13

142
ports/stm/tools/examples/stm32f405.csv Normal file
View File

@ -0,0 +1,142 @@
Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
,,SYS,TIM1/2,TIM3/4/5,TIM8/9/10/11,I2C1/2/3,SPI1/SPI2/I2S2/I2S2ext,SPI3/I2Sext/I2S3,USART1/2/3/I2S3ext,UART4/5/USART6,CAN1/CAN2/TIM12/13/14,OTG_FS/OTG_HS,ETH,FSMC/SDIO/OTG_FS,DCMI,,,ADC
PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,ETH_MII_CRS,,,,EVENTOUT,ADC123_IN0
PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,,,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,,EVENTOUT,ADC123_IN1
PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,ETH_MDIO,,,,EVENTOUT,ADC123_IN2
PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUT,ADC123_IN3
PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT,ADC12_IN4
PortA,PA5,,TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT,ADC12_IN5
PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCK,,EVENTOUT,ADC12_IN6
PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,,,,EVENTOUT,ADC12_IN7
PortA,PA8,MCO1,TIM1_CH1,,,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT,
PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT,
PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT,
PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT,
PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT,
PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT,
PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT,
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,,,,,EVENTOUT,
PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT,ADC12_IN8
PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT,ADC12_IN9
PortB,PB2,,,,,,,,,,,,,,,,EVENTOUT,
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT,
PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,I2S3ext_SD,,,,,,,,EVENTOUT,
PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,,DCMI_D10,,EVENTOUT,
PortB,PB6,,,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,CAN2_TX,,,,DCMI_D5,,EVENTOUT,
PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FSMC_NL,DCMI_VSYNC,,EVENTOUT,
PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,ETH_MII_TXD3,SDIO_D4,DCMI_D6,,EVENTOUT,
PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDIO_D5,DCMI_D7,,EVENTOUT,
PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,,EVENTOUT,
PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,,EVENTOUT,
PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT,
PortB,PB13,,TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT,
PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,I2S2ext_SD,USART3_RTS,,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT,
PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT,
PortC,PC0,,,,,,,,,,,OTG_HS_ULPI_STP,,,,,EVENTOUT,ADC123_IN10
PortC,PC1,,,,,,,,,,,,ETH_MDC,,,,EVENTOUT,ADC123_IN11
PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,,,,EVENTOUT,ADC123_IN12
PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,,,,EVENTOUT,ADC123_IN13
PortC,PC4,,,,,,,,,,,,ETH_MII_RXD0/ETH_RMII_RXD0,,,,EVENTOUT,ADC123_IN14
PortC,PC5,,,,,,,,,,,,ETH_MII_RXD1/ETH_RMII_RXD1,,,,EVENTOUT,ADC123_IN15
PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDIO_D6,DCMI_D0,,EVENTOUT,
PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDIO_D7,DCMI_D1,,EVENTOUT,
PortC,PC8,,,TIM3_CH3,TIM8_CH3,,,,,USART6_CK,,,,SDIO_D0,DCMI_D2,,EVENTOUT,
PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,,,,,,SDIO_D1,DCMI_D3,,EVENTOUT,
PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,,SDIO_D2,DCMI_D8,,EVENTOUT,
PortC,PC11,,,,,,I2S3ext_SD,SPI3_MISO,USART3_RX,UART4_RX,,,,SDIO_D3,DCMI_D4,,EVENTOUT,
PortC,PC12,,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDIO_CK,DCMI_D9,,EVENTOUT,
PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD0,,,,,,,,,,CAN1_RX,,,FSMC_D2,,,EVENTOUT,
PortD,PD1,,,,,,,,,,CAN1_TX,,,FSMC_D3,,,EVENTOUT,
PortD,PD2,,,TIM3_ETR,,,,,,UART5_RX,,,,SDIO_CMD,DCMI_D11,,EVENTOUT,
PortD,PD3,,,,,,,,USART2_CTS,,,,,FSMC_CLK,,,EVENTOUT,
PortD,PD4,,,,,,,,USART2_RTS,,,,,FSMC_NOE,,,EVENTOUT,
PortD,PD5,,,,,,,,USART2_TX,,,,,FSMC_NWE,,,EVENTOUT,
PortD,PD6,,,,,,,,USART2_RX,,,,,FSMC_NWAIT,,,EVENTOUT,
PortD,PD7,,,,,,,,USART2_CK,,,,,FSMC_NE1/FSMC_NCE2,,,EVENTOUT,
PortD,PD8,,,,,,,,USART3_TX,,,,,FSMC_D13,,,EVENTOUT,
PortD,PD9,,,,,,,,USART3_RX,,,,,FSMC_D14,,,EVENTOUT,
PortD,PD10,,,,,,,,USART3_CK,,,,,FSMC_D15,,,EVENTOUT,
PortD,PD11,,,,,,,,USART3_CTS,,,,,FSMC_A16,,,EVENTOUT,
PortD,PD12,,,TIM4_CH1,,,,,USART3_RTS,,,,,FSMC_A17,,,EVENTOUT,
PortD,PD13,,,TIM4_CH2,,,,,,,,,,FSMC_A18,,,EVENTOUT,
PortD,PD14,,,TIM4_CH3,,,,,,,,,,FSMC_D0,,,EVENTOUT,
PortD,PD15,,,TIM4_CH4,,,,,,,,,,FSMC_D1,,,EVENTOUT,
PortE,PE0,,,TIM4_ETR,,,,,,,,,,FSMC_NBL0,DCMI_D2,,EVENTOUT,
PortE,PE1,,,,,,,,,,,,,FSMC_NBL1,DCMI_D3,,EVENTOUT,
PortE,PE2,TRACECLK,,,,,,,,,,,ETH_MII_TXD3,FSMC_A23,,,EVENTOUT,
PortE,PE3,TRACED0,,,,,,,,,,,,FSMC_A19,,,EVENTOUT,
PortE,PE4,TRACED1,,,,,,,,,,,,FSMC_A20,DCMI_D4,,EVENTOUT,
PortE,PE5,TRACED2,,,TIM9_CH1,,,,,,,,,FSMC_A21,DCMI_D6,,EVENTOUT,
PortE,PE6,TRACED3,,,TIM9_CH2,,,,,,,,,FSMC_A22,DCMI_D7,,EVENTOUT,
PortE,PE7,,TIM1_ETR,,,,,,,,,,,FSMC_D4,,,EVENTOUT,
PortE,PE8,,TIM1_CH1N,,,,,,,,,,,FSMC_D5,,,EVENTOUT,
PortE,PE9,,TIM1_CH1,,,,,,,,,,,FSMC_D6,,,EVENTOUT,
PortE,PE10,,TIM1_CH2N,,,,,,,,,,,FSMC_D7,,,EVENTOUT,
PortE,PE11,,TIM1_CH2,,,,,,,,,,,FSMC_D8,,,EVENTOUT,
PortE,PE12,,TIM1_CH3N,,,,,,,,,,,FSMC_D9,,,EVENTOUT,
PortE,PE13,,TIM1_CH3,,,,,,,,,,,FSMC_D10,,,EVENTOUT,
PortE,PE14,,TIM1_CH4,,,,,,,,,,,FSMC_D11,,,EVENTOUT,
PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FSMC_D12,,,EVENTOUT,
PortF,PF0,,,,,I2C2_SDA,,,,,,,,FSMC_A0,,,EVENTOUT,
PortF,PF1,,,,,I2C2_SCL,,,,,,,,FSMC_A1,,,EVENTOUT,
PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FSMC_A2,,,EVENTOUT,
PortF,PF3,,,,,,,,,,,,,FSMC_A3,,,EVENTOUT,ADC3_IN9
PortF,PF4,,,,,,,,,,,,,FSMC_A4,,,EVENTOUT,ADC3_IN14
PortF,PF5,,,,,,,,,,,,,FSMC_A5,,,EVENTOUT,ADC3_IN15
PortF,PF6,,,,TIM10_CH1,,,,,,,,,FSMC_NIORD,,,EVENTOUT,ADC3_IN4
PortF,PF7,,,,TIM11_CH1,,,,,,,,,FSMC_NREG,,,EVENTOUT,ADC3_IN5
PortF,PF8,,,,,,,,,,TIM13_CH1,,,FSMC_NIOWR,,,EVENTOUT,ADC3_IN6
PortF,PF9,,,,,,,,,,TIM14_CH1,,,FSMC_CD,,,EVENTOUT,ADC3_IN7
PortF,PF10,,,,,,,,,,,,,FSMC_INTR,,,EVENTOUT,ADC3_IN8
PortF,PF11,,,,,,,,,,,,,,DCMI_D12,,EVENTOUT,
PortF,PF12,,,,,,,,,,,,,FSMC_A6,,,EVENTOUT,
PortF,PF13,,,,,,,,,,,,,FSMC_A7,,,EVENTOUT,
PortF,PF14,,,,,,,,,,,,,FSMC_A8,,,EVENTOUT,
PortF,PF15,,,,,,,,,,,,,FSMC_A9,,,EVENTOUT,
PortG,PG0,,,,,,,,,,,,,FSMC_A10,,,EVENTOUT,
PortG,PG1,,,,,,,,,,,,,FSMC_A11,,,EVENTOUT,
PortG,PG2,,,,,,,,,,,,,FSMC_A12,,,EVENTOUT,
PortG,PG3,,,,,,,,,,,,,FSMC_A13,,,EVENTOUT,
PortG,PG4,,,,,,,,,,,,,FSMC_A14,,,EVENTOUT,
PortG,PG5,,,,,,,,,,,,,FSMC_A15,,,EVENTOUT,
PortG,PG6,,,,,,,,,,,,,FSMC_INT2,,,EVENTOUT,
PortG,PG7,,,,,,,,,USART6_CK,,,,FSMC_INT3,,,EVENTOUT,
PortG,PG8,,,,,,,,,USART6_RTS,,,ETH_PPS_OUT,,,,EVENTOUT,
PortG,PG9,,,,,,,,,USART6_RX,,,,FSMC_NE2/FSMC_NCE3,,,EVENTOUT,
PortG,PG10,,,,,,,,,,,,,FSMC_NCE4_1/FSMC_NE3,,,EVENTOUT,
PortG,PG11,,,,,,,,,,,,ETH_MII_TX_EN/ETH_RMII_TX_EN,FSMC_NCE4_2,,,EVENTOUT,
PortG,PG12,,,,,,,,,USART6_RTS,,,,FSMC_NE4,,,EVENTOUT,
PortG,PG13,,,,,,,,,USART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FSMC_A24,,,EVENTOUT,
PortG,PG14,,,,,,,,,USART6_TX,,,ETH_MII_TXD1/ETH_RMII_TXD1,FSMC_A25,,,EVENTOUT,
PortG,PG15,,,,,,,,,USART6_CTS,,,,,DCMI_D13,,EVENTOUT,
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH2,,,,,,,,,,,,ETH_MII_CRS,,,,EVENTOUT,
PortH,PH3,,,,,,,,,,,,ETH_MII_COL,,,,EVENTOUT,
PortH,PH4,,,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT,
PortH,PH5,,,,,I2C2_SDA,,,,,,,,,,,EVENTOUT,
PortH,PH6,,,,,I2C2_SMBA,,,,,TIM12_CH1,,ETH_MII_RXD2,,,,EVENTOUT,
PortH,PH7,,,,,I2C3_SCL,,,,,,,ETH_MII_RXD3,,,,EVENTOUT,
PortH,PH8,,,,,I2C3_SDA,,,,,,,,,DCMI_HSYNC,,EVENTOUT,
PortH,PH9,,,,,I2C3_SMBA,,,,,TIM12_CH2,,,,DCMI_D0,,EVENTOUT,
PortH,PH10,,,TIM5_CH1,,,,,,,,,,,DCMI_D1,,EVENTOUT,
PortH,PH11,,,TIM5_CH2,,,,,,,,,,,DCMI_D2,,EVENTOUT,
PortH,PH12,,,TIM5_CH3,,,,,,,,,,,DCMI_D3,,EVENTOUT,
PortH,PH13,,,,TIM8_CH1N,,,,,,CAN1_TX,,,,,,EVENTOUT,
PortH,PH14,,,,TIM8_CH2N,,,,,,,,,,DCMI_D4,,EVENTOUT,
PortH,PH15,,,,TIM8_CH3N,,,,,,,,,,DCMI_D11,,EVENTOUT,
PortI,PI0,,,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,,DCMI_D13,,EVENTOUT,
PortI,PI1,,,,,,SPI2_SCK/I2S2_CK,,,,,,,,DCMI_D8,,EVENTOUT,
PortI,PI2,,,,TIM8_CH4,,SPI2_MISO,I2S2ext_SD,,,,,,,DCMI_D9,,EVENTOUT,
PortI,PI3,,,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,,DCMI_D10,,EVENTOUT,
PortI,PI4,,,,TIM8_BKIN,,,,,,,,,,DCMI_D5,,EVENTOUT,
PortI,PI5,,,,TIM8_CH1,,,,,,,,,,DCMI_VSYNC,,EVENTOUT,
PortI,PI6,,,,TIM8_CH2,,,,,,,,,,DCMI_D6,,EVENTOUT,
PortI,PI7,,,,TIM8_CH3,,,,,,,,,,DCMI_D7,,EVENTOUT,
PortI,PI8,,,,,,,,,,,,,,,,EVENTOUT,
PortI,PI9,,,,,,,,,,CAN1_RX,,,,,,EVENTOUT,
PortI,PI10,,,,,,,,,,,,ETH_MII_RX_ER,,,,EVENTOUT,
PortI,PI11,,,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT,
1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
2 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/2/3 SPI1/SPI2/I2S2/I2S2ext SPI3/I2Sext/I2S3 USART1/2/3/I2S3ext UART4/5/USART6 CAN1/CAN2/TIM12/13/14 OTG_FS/OTG_HS ETH FSMC/SDIO/OTG_FS DCMI ADC
3 PortA PA0 TIM2_CH1/TIM2_ETR TIM5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT ADC123_IN0
4 PortA PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII_RX_CLK/ETH_RMII_REF_CLK EVENTOUT ADC123_IN1
5 PortA PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX ETH_MDIO EVENTOUT ADC123_IN2
6 PortA PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_D0 ETH_MII_COL EVENTOUT ADC123_IN3
7 PortA PA4 SPI1_NSS SPI3_NSS/I2S3_WS USART2_CK OTG_HS_SOF DCMI_HSYNC EVENTOUT ADC12_IN4
8 PortA PA5 TIM2_CH1/TIM2_ETR TIM8_CH1N SPI1_SCK OTG_HS_ULPI_CK EVENTOUT ADC12_IN5
9 PortA PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCK EVENTOUT ADC12_IN6
10 PortA PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 ETH_MII_RX_DV/ETH_RMII_CRS_DV EVENTOUT ADC12_IN7
11 PortA PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT
12 PortA PA9 TIM1_CH2 I2C3_SMBA USART1_TX DCMI_D0 EVENTOUT
13 PortA PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT
14 PortA PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT
15 PortA PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT
16 PortA PA13 JTMS/SWDIO EVENTOUT
17 PortA PA14 JTCK/SWCLK EVENTOUT
18 PortA PA15 JTDI TIM2_CH1/TIM2_ETR SPI1_NSS SPI3_NSS/I2S3_WS EVENTOUT
19 PortB PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_D1 ETH_MII_RXD2 EVENTOUT ADC12_IN8
20 PortB PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_D2 ETH_MII_RXD3 EVENTOUT ADC12_IN9
21 PortB PB2 EVENTOUT
22 PortB PB3 JTDO/TRACESWO TIM2_CH2 SPI1_SCK SPI3_SCK/I2S3_CK EVENTOUT
23 PortB PB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO I2S3ext_SD EVENTOUT
24 PortB PB5 TIM3_CH2 I2C1_SMBA SPI1_MOSI SPI3_MOSI/I2S3_SD CAN2_RX OTG_HS_ULPI_D7 ETH_PPS_OUT DCMI_D10 EVENTOUT
25 PortB PB6 TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX DCMI_D5 EVENTOUT
26 PortB PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYNC EVENTOUT
27 PortB PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX ETH_MII_TXD3 SDIO_D4 DCMI_D6 EVENTOUT
28 PortB PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS/I2S2_WS CAN1_TX SDIO_D5 DCMI_D7 EVENTOUT
29 PortB PB10 TIM2_CH3 I2C2_SCL SPI2_SCK/I2S2_CK USART3_TX OTG_HS_ULPI_D3 ETH_MII_RX_ER EVENTOUT
30 PortB PB11 TIM2_CH4 I2C2_SDA USART3_RX OTG_HS_ULPI_D4 ETH_MII_TX_EN/ETH_RMII_TX_EN EVENTOUT
31 PortB PB12 TIM1_BKIN I2C2_SMBA SPI2_NSS/I2S2_WS USART3_CK CAN2_RX OTG_HS_ULPI_D5 ETH_MII_TXD0/ETH_RMII_TXD0 OTG_HS_ID EVENTOUT
32 PortB PB13 TIM1_CH1N SPI2_SCK/I2S2_CK USART3_CTS CAN2_TX OTG_HS_ULPI_D6 ETH_MII_TXD1/ETH_RMII_TXD1 EVENTOUT
33 PortB PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO I2S2ext_SD USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT
34 PortB PB15 RTC_REFIN TIM1_CH3N TIM8_CH3N SPI2_MOSI/I2S2_SD TIM12_CH2 OTG_HS_DP EVENTOUT
35 PortC PC0 OTG_HS_ULPI_STP EVENTOUT ADC123_IN10
36 PortC PC1 ETH_MDC EVENTOUT ADC123_IN11
37 PortC PC2 SPI2_MISO I2S2ext_SD OTG_HS_ULPI_DIR ETH_MII_TXD2 EVENTOUT ADC123_IN12
38 PortC PC3 SPI2_MOSI/I2S2_SD OTG_HS_ULPI_NXT ETH_MII_TX_CLK EVENTOUT ADC123_IN13
39 PortC PC4 ETH_MII_RXD0/ETH_RMII_RXD0 EVENTOUT ADC123_IN14
40 PortC PC5 ETH_MII_RXD1/ETH_RMII_RXD1 EVENTOUT ADC123_IN15
41 PortC PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 DCMI_D0 EVENTOUT
42 PortC PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDIO_D7 DCMI_D1 EVENTOUT
43 PortC PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT
44 PortC PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN SDIO_D1 DCMI_D3 EVENTOUT
45 PortC PC10 SPI3_SCK/I2S3_CK USART3_TX UART4_TX SDIO_D2 DCMI_D8 EVENTOUT
46 PortC PC11 I2S3ext_SD SPI3_MISO USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT
47 PortC PC12 SPI3_MOSI/I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT
48 PortC PC13 EVENTOUT
49 PortC PC14 EVENTOUT
50 PortC PC15 EVENTOUT
51 PortD PD0 CAN1_RX FSMC_D2 EVENTOUT
52 PortD PD1 CAN1_TX FSMC_D3 EVENTOUT
53 PortD PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT
54 PortD PD3 USART2_CTS FSMC_CLK EVENTOUT
55 PortD PD4 USART2_RTS FSMC_NOE EVENTOUT
56 PortD PD5 USART2_TX FSMC_NWE EVENTOUT
57 PortD PD6 USART2_RX FSMC_NWAIT EVENTOUT
58 PortD PD7 USART2_CK FSMC_NE1/FSMC_NCE2 EVENTOUT
59 PortD PD8 USART3_TX FSMC_D13 EVENTOUT
60 PortD PD9 USART3_RX FSMC_D14 EVENTOUT
61 PortD PD10 USART3_CK FSMC_D15 EVENTOUT
62 PortD PD11 USART3_CTS FSMC_A16 EVENTOUT
63 PortD PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT
64 PortD PD13 TIM4_CH2 FSMC_A18 EVENTOUT
65 PortD PD14 TIM4_CH3 FSMC_D0 EVENTOUT
66 PortD PD15 TIM4_CH4 FSMC_D1 EVENTOUT
67 PortE PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT
68 PortE PE1 FSMC_NBL1 DCMI_D3 EVENTOUT
69 PortE PE2 TRACECLK ETH_MII_TXD3 FSMC_A23 EVENTOUT
70 PortE PE3 TRACED0 FSMC_A19 EVENTOUT
71 PortE PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT
72 PortE PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT
73 PortE PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT
74 PortE PE7 TIM1_ETR FSMC_D4 EVENTOUT
75 PortE PE8 TIM1_CH1N FSMC_D5 EVENTOUT
76 PortE PE9 TIM1_CH1 FSMC_D6 EVENTOUT
77 PortE PE10 TIM1_CH2N FSMC_D7 EVENTOUT
78 PortE PE11 TIM1_CH2 FSMC_D8 EVENTOUT
79 PortE PE12 TIM1_CH3N FSMC_D9 EVENTOUT
80 PortE PE13 TIM1_CH3 FSMC_D10 EVENTOUT
81 PortE PE14 TIM1_CH4 FSMC_D11 EVENTOUT
82 PortE PE15 TIM1_BKIN FSMC_D12 EVENTOUT
83 PortF PF0 I2C2_SDA FSMC_A0 EVENTOUT
84 PortF PF1 I2C2_SCL FSMC_A1 EVENTOUT
85 PortF PF2 I2C2_SMBA FSMC_A2 EVENTOUT
86 PortF PF3 FSMC_A3 EVENTOUT ADC3_IN9
87 PortF PF4 FSMC_A4 EVENTOUT ADC3_IN14
88 PortF PF5 FSMC_A5 EVENTOUT ADC3_IN15
89 PortF PF6 TIM10_CH1 FSMC_NIORD EVENTOUT ADC3_IN4
90 PortF PF7 TIM11_CH1 FSMC_NREG EVENTOUT ADC3_IN5
91 PortF PF8 TIM13_CH1 FSMC_NIOWR EVENTOUT ADC3_IN6
92 PortF PF9 TIM14_CH1 FSMC_CD EVENTOUT ADC3_IN7
93 PortF PF10 FSMC_INTR EVENTOUT ADC3_IN8
94 PortF PF11 DCMI_D12 EVENTOUT
95 PortF PF12 FSMC_A6 EVENTOUT
96 PortF PF13 FSMC_A7 EVENTOUT
97 PortF PF14 FSMC_A8 EVENTOUT
98 PortF PF15 FSMC_A9 EVENTOUT
99 PortG PG0 FSMC_A10 EVENTOUT
100 PortG PG1 FSMC_A11 EVENTOUT
101 PortG PG2 FSMC_A12 EVENTOUT
102 PortG PG3 FSMC_A13 EVENTOUT
103 PortG PG4 FSMC_A14 EVENTOUT
104 PortG PG5 FSMC_A15 EVENTOUT
105 PortG PG6 FSMC_INT2 EVENTOUT
106 PortG PG7 USART6_CK FSMC_INT3 EVENTOUT
107 PortG PG8 USART6_RTS ETH_PPS_OUT EVENTOUT
108 PortG PG9 USART6_RX FSMC_NE2/FSMC_NCE3 EVENTOUT
109 PortG PG10 FSMC_NCE4_1/FSMC_NE3 EVENTOUT
110 PortG PG11 ETH_MII_TX_EN/ETH_RMII_TX_EN FSMC_NCE4_2 EVENTOUT
111 PortG PG12 USART6_RTS FSMC_NE4 EVENTOUT
112 PortG PG13 USART6_CTS ETH_MII_TXD0/ETH_RMII_TXD0 FSMC_A24 EVENTOUT
113 PortG PG14 USART6_TX ETH_MII_TXD1/ETH_RMII_TXD1 FSMC_A25 EVENTOUT
114 PortG PG15 USART6_CTS DCMI_D13 EVENTOUT
115 PortH PH0 EVENTOUT
116 PortH PH1 EVENTOUT
117 PortH PH2 ETH_MII_CRS EVENTOUT
118 PortH PH3 ETH_MII_COL EVENTOUT
119 PortH PH4 I2C2_SCL OTG_HS_ULPI_NXT EVENTOUT
120 PortH PH5 I2C2_SDA EVENTOUT
121 PortH PH6 I2C2_SMBA TIM12_CH1 ETH_MII_RXD2 EVENTOUT
122 PortH PH7 I2C3_SCL ETH_MII_RXD3 EVENTOUT
123 PortH PH8 I2C3_SDA DCMI_HSYNC EVENTOUT
124 PortH PH9 I2C3_SMBA TIM12_CH2 DCMI_D0 EVENTOUT
125 PortH PH10 TIM5_CH1 DCMI_D1 EVENTOUT
126 PortH PH11 TIM5_CH2 DCMI_D2 EVENTOUT
127 PortH PH12 TIM5_CH3 DCMI_D3 EVENTOUT
128 PortH PH13 TIM8_CH1N CAN1_TX EVENTOUT
129 PortH PH14 TIM8_CH2N DCMI_D4 EVENTOUT
130 PortH PH15 TIM8_CH3N DCMI_D11 EVENTOUT
131 PortI PI0 TIM5_CH4 SPI2_NSS/I2S2_WS DCMI_D13 EVENTOUT
132 PortI PI1 SPI2_SCK/I2S2_CK DCMI_D8 EVENTOUT
133 PortI PI2 TIM8_CH4 SPI2_MISO I2S2ext_SD DCMI_D9 EVENTOUT
134 PortI PI3 TIM8_ETR SPI2_MOSI/I2S2_SD DCMI_D10 EVENTOUT
135 PortI PI4 TIM8_BKIN DCMI_D5 EVENTOUT
136 PortI PI5 TIM8_CH1 DCMI_VSYNC EVENTOUT
137 PortI PI6 TIM8_CH2 DCMI_D6 EVENTOUT
138 PortI PI7 TIM8_CH3 DCMI_D7 EVENTOUT
139 PortI PI8 EVENTOUT
140 PortI PI9 CAN1_RX EVENTOUT
141 PortI PI10 ETH_MII_RX_ER EVENTOUT
142 PortI PI11 OTG_HS_ULPI_DIR EVENTOUT

8
ports/stm/tools/parse_af_csv.py
View File

@ -26,6 +26,10 @@ import csv
import sys
# Use: parse_af_csf.py Filename.csv -pins-only
# Designed for use with .csv files from Micropython, or in identical format
# created via Datasheet peripheral tables with a Sheets program.
#
# See examples/stm32f405.csv for example formatting.
# Most peripherals (SPI, I2C) output 3 values:
# peripheral index, alt function, pin string
@ -130,8 +134,4 @@ with open(sys.argv[1]) as csv_file:
for line in outlist:
print("extern const mcu_pin_obj_t pin_" + line[0] + ";")
print(f'Processed {line_count} lines.')

49
ports/stm/tools/parse_pins_csv.py Normal file
View File

@ -0,0 +1,49 @@
# This file is part of the MicroPython project, http://micropython.org/
#
# The MIT License (MIT)
#
# Copyright (c) 2020 Lucian Copeland for Adafruit Industries
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.
import csv
import sys
# Use: parse_pins_csv.py Filename.csv
# Designed for use with .csv files from Micropython, or in identical format
# created via Datasheet peripheral tables with a Sheets program.
#
# See examples/nucleo_h743.csv for example formatting.
# Open target file
with open(sys.argv[1]) as csv_file:
csv_reader = csv.reader(csv_file, delimiter=',')
line_count = 0
print("STATIC const mp_rom_map_elem_t board_module_globals_table[] = {")
for row in csv_reader:
label = row[0]
pin = row[1]
if len(pin) < 4:
pin = pin[:2] + '0' + pin[2:]
print("{ MP_ROM_QSTR(MP_QSTR_" + label + "), MP_ROM_PTR(&pin_" + pin + ") },")
line_count += 1
print(f'Processed {line_count} lines.')