From 9c3c0555ddfcfc3bca779d5fb779f35cdc86e9a2 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Tue, 21 Mar 2023 16:21:57 -0700 Subject: [PATCH] Switch iMX RT sdk to NXP repo Fixes #7645 --- .gitmodules | 2 +- ports/mimxrt10xx/Makefile | 45 ++++++------- ports/mimxrt10xx/board.h | 1 - ports/mimxrt10xx/boards/board.h | 29 ++++++++ .../boards/feather_m7_1011/flash_config.c | 62 +++++------------ .../boards/feather_mimxrt1011/flash_config.c | 62 +++++------------ .../boards/feather_mimxrt1062/flash_config.c | 63 +++++------------ ports/mimxrt10xx/boards/flash_config.h | 36 +++++++++- .../boards/imxrt1010_evk/flash_config.c | 63 +++++------------ .../boards/imxrt1020_evk/flash_config.c | 63 +++++------------ .../boards/imxrt1060_evk/flash_config.c | 63 +++++------------ .../boards/metro_m7_1011/flash_config.c | 65 ++++++------------ .../sparkfun_teensy_micromod/flash_config.c | 65 +++++------------- .../mimxrt10xx/boards/teensy40/flash_config.c | 67 ++++++------------- .../mimxrt10xx/boards/teensy41/flash_config.c | 65 +++++------------- .../mimxrt10xx/common-hal/analogio/AnalogIn.c | 2 +- ports/mimxrt10xx/common-hal/busio/I2C.c | 4 +- ports/mimxrt10xx/common-hal/busio/SPI.c | 2 +- ports/mimxrt10xx/common-hal/busio/UART.c | 4 +- ports/mimxrt10xx/common-hal/busio/UART.h | 2 +- .../common-hal/digitalio/DigitalInOut.c | 2 +- .../common-hal/microcontroller/Processor.c | 4 +- ports/mimxrt10xx/common-hal/os/__init__.c | 2 +- ports/mimxrt10xx/common-hal/pwmio/PWMOut.c | 3 +- ports/mimxrt10xx/common-hal/rtc/RTC.c | 4 +- ports/mimxrt10xx/linking/common.ld | 2 + ports/mimxrt10xx/mphalport.c | 4 -- .../mimxrt10xx/peripherals/mimxrt10xx/pins.h | 2 +- ports/mimxrt10xx/sdk | 2 +- .../supervisor/flexspi_nor_flash_ops.c | 2 +- ports/mimxrt10xx/supervisor/internal_flash.c | 4 +- ports/mimxrt10xx/supervisor/port.c | 34 +++++++++- 32 files changed, 322 insertions(+), 508 deletions(-) delete mode 100644 ports/mimxrt10xx/board.h create mode 100644 ports/mimxrt10xx/boards/board.h diff --git a/.gitmodules b/.gitmodules index 023892218a..9c8d3b4b68 100644 --- a/.gitmodules +++ b/.gitmodules @@ -100,7 +100,7 @@ url = https://github.com/adafruit/Adafruit_MP3 [submodule "ports/mimxrt10xx/sdk"] path = ports/mimxrt10xx/sdk - url = https://github.com/adafruit/MIMXRT10xx_SDK + url = https://github.com/nxp-mcuxpresso/mcux-sdk.git [submodule "frozen/Adafruit_CircuitPython_Register"] path = frozen/Adafruit_CircuitPython_Register url = https://github.com/adafruit/Adafruit_CircuitPython_Register.git diff --git a/ports/mimxrt10xx/Makefile b/ports/mimxrt10xx/Makefile index d3db4c44e3..d8d12b74da 100644 --- a/ports/mimxrt10xx/Makefile +++ b/ports/mimxrt10xx/Makefile @@ -30,8 +30,7 @@ CROSS_COMPILE = arm-none-eabi- INC += \ -I. \ -I../.. \ - -I../lib/mp-readline \ - -I../shared/timeutils \ + -I../../lib/cmsis/inc \ -I../../lib/tinyusb/src \ -I../../supervisor/shared/usb \ -I$(BUILD) \ @@ -42,7 +41,7 @@ INC += \ -Isdk/CMSIS/Include \ -Isdk/devices/$(CHIP_FAMILY) \ -Isdk/devices/$(CHIP_FAMILY)/drivers \ - -Isdk/devices/$(CHIP_FAMILY)/xip \ + -Isdk/drivers/common # NDEBUG disables assert() statements. This reduces code size pretty dramatically, per tannewt. @@ -106,25 +105,26 @@ LDFLAGS += -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-sp-d16 -mthumb -mapcs BOOTLOADER_SIZE := 0x6000C000 SRC_SDK := \ - drivers/fsl_adc.c \ - drivers/fsl_cache.c \ - drivers/fsl_clock.c \ - drivers/fsl_common.c \ - drivers/fsl_flexspi.c \ - drivers/fsl_gpio.c \ - drivers/fsl_lpi2c.c \ - drivers/fsl_lpspi.c \ - drivers/fsl_lpuart.c \ - drivers/fsl_ocotp.c \ - drivers/fsl_pwm.c \ - drivers/fsl_snvs_hp.c \ - drivers/fsl_snvs_lp.c \ - drivers/fsl_tempmon.c \ - drivers/fsl_trng.c \ - system_$(CHIP_FAMILY).c \ + devices/$(CHIP_FAMILY)/drivers/fsl_clock.c \ + devices/$(CHIP_FAMILY)/system_$(CHIP_FAMILY).c \ + devices/$(CHIP_FAMILY)/xip/fsl_flexspi_nor_boot.c \ + drivers/adc_12b1msps_sar/fsl_adc.c \ + drivers/cache/armv7-m7/fsl_cache.c \ + drivers/common/fsl_common_arm.c \ + drivers/common/fsl_common.c \ + drivers/flexspi/fsl_flexspi.c \ + drivers/igpio/fsl_gpio.c \ + drivers/lpi2c/fsl_lpi2c.c \ + drivers/lpspi/fsl_lpspi.c \ + drivers/lpuart/fsl_lpuart.c \ + drivers/ocotp/fsl_ocotp.c \ + drivers/pwm/fsl_pwm.c \ + drivers/snvs_hp/fsl_snvs_hp.c \ + drivers/snvs_lp/fsl_snvs_lp.c \ + drivers/tempmon/fsl_tempmon.c \ + drivers/trng/fsl_trng.c \ -SRC_SDK := $(addprefix sdk/devices/$(CHIP_FAMILY)/, $(SRC_SDK)) -$(addprefix $(BUILD)/, $(SRC_SDK:.c=.o)): CFLAGS += -Wno-undef -Wno-missing-prototypes -Wno-cast-align +SRC_SDK := $(addprefix sdk/, $(SRC_SDK)) SRC_C += \ background.c \ @@ -191,8 +191,7 @@ $(BUILD)/firmware.uf2: $(BUILD)/firmware.elf $(STEPECHO) "Create $@" $(Q)$(OBJCOPY) -O binary -R .stack -R .dtcm_bss -R .ivt -R .flash_config $^ $@-binpart $(Q)$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -b $(BOOTLOADER_SIZE) -f MIMXRT10XX -c -o $@ $@-binpart - -# $(Q)rm $@-binpart + $(Q)rm $@-binpart $(BUILD)/firmware.hex: $(BUILD)/firmware.elf $(Q)$(OBJCOPY) -O ihex -R .stack -R .dtcm_bss $< $@ diff --git a/ports/mimxrt10xx/board.h b/ports/mimxrt10xx/board.h deleted file mode 100644 index 1c9596e7d2..0000000000 --- a/ports/mimxrt10xx/board.h +++ /dev/null @@ -1 +0,0 @@ -// Empty but needed for the SDK diff --git a/ports/mimxrt10xx/boards/board.h b/ports/mimxrt10xx/boards/board.h new file mode 100644 index 0000000000..e6736806ed --- /dev/null +++ b/ports/mimxrt10xx/boards/board.h @@ -0,0 +1,29 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mpconfigboard.h" + +#define XIP_BOOT_HEADER_ENABLE (1) diff --git a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c index 5871dda963..4e189590d0 100644 --- a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c @@ -7,47 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for W25Q32JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -61,13 +35,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqNum = 1u, }, .deviceModeArg = 0x02, // Bit pattern for setting Quad Enable. - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, + .serialClkFreq = kFLEXSPISerialClk_133MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -78,20 +52,20 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -101,21 +75,21 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status -2 - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01 /* number of bytes to write */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -128,17 +102,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -147,7 +121,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c index 7460615c4c..2c6fa962aa 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c @@ -7,47 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -61,13 +35,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqNum = 1u, }, .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, + .serialClkFreq = kFLEXSPISerialClk_133MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -78,20 +52,20 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -101,21 +75,21 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -128,17 +102,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -147,7 +121,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c index d6cfc07e62..2c6fa962aa 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c @@ -7,48 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -62,13 +35,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqNum = 1u, }, .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, + .serialClkFreq = kFLEXSPISerialClk_133MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -79,20 +52,20 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -102,21 +75,21 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -129,17 +102,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -148,7 +121,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/flash_config.h b/ports/mimxrt10xx/boards/flash_config.h index 25f1550ae8..b0be0a93c0 100644 --- a/ports/mimxrt10xx/boards/flash_config.h +++ b/ports/mimxrt10xx/boards/flash_config.h @@ -34,7 +34,41 @@ #include "mpconfigboard.h" // For flash size settings #include "fsl_common.h" -#include "fsl_flexspi_nor_config.h" +#ifdef CPU_MIMXRT1011DAE5A +// TODO: Remove this when the 1011 has a romapi header that matches the others. +#include "sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.h" +typedef enum _flexspi_serial_clk_freq_caps +{ + kFLEXSPISerialClk_NoChange = 0U, + kFLEXSPISerialClk_30MHz = 1U, + kFLEXSPISerialClk_50MHz = 2U, + kFLEXSPISerialClk_60MHz = 3U, + kFLEXSPISerialClk_75MHz = 4U, + kFLEXSPISerialClk_80MHz = 5U, + kFLEXSPISerialClk_100MHz = 6U, + kFLEXSPISerialClk_133MHz = 7U, + kFLEXSPISerialClk_166MHz = 8U, + kFLEXSPISerialClk_200MHz = 9U, +} caps_flexspi_serial_clk_freq_t; + +/*! @brief FLEXSPI Read Sample Clock Source definition */ +typedef enum _flexspi_read_sample_clk_caps +{ + kFLEXSPIReadSampleClk_LoopbackInternally = 0U, + kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U, + kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U, + kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U, +} caps_flexspi_read_sample_clk_t; + +enum +{ + kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */ +}; + +#define FSL_ROM_FLEXSPI_LUT_SEQ FLEXSPI_LUT_SEQ +#else +#include "fsl_romapi.h" +#endif #define SEQUENCE(first, second, third, fourth) first, second, third, fourth #define TWO_EMPTY_STEPS 0x00000000 diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c index 9c88f689d8..f15a3f3459 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c @@ -7,48 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for AT25SF128A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -62,13 +35,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqNum = 1u, }, .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, + .serialClkFreq = kFLEXSPISerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -79,20 +52,20 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -102,21 +75,21 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -129,17 +102,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -148,7 +121,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c index 6589ad9c48..2ae8ae9b76 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c @@ -7,48 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for IS25LP064A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -62,13 +35,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqNum = 1u, }, .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_30MHz, + .serialClkFreq = kFLEXSPISerialClk_30MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -79,20 +52,20 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + // SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, // RADDR_SDR, FLEXSPI_4PAD, 24 bits to transmit ), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, // READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -102,21 +75,21 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -129,17 +102,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -148,7 +121,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c index 40db33444f..c75174d1c4 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c @@ -7,48 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for IS25WP064A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -62,13 +35,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqNum = 1u, }, .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, + .serialClkFreq = kFLEXSPISerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -79,20 +52,20 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -102,21 +75,21 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -129,17 +102,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -148,7 +121,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c index 3477de9e34..e4562c1965 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c +++ b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c @@ -7,48 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - - -__attribute__((section(".boot_hdr.ivt"),used)) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"),used)) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for W25Q32JV with QSPI routed. (compatible with GD25Q32) __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -68,13 +41,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqId = 2u, .seqNum = 1u, }, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, + .serialClkFreq = kFLEXSPISerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -85,48 +58,48 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 2: Empty - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, DUMMY_SDR, FLEXSPI_1PAD, 8), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x02), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -139,17 +112,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -158,7 +131,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/sparkfun_teensy_micromod/flash_config.c b/ports/mimxrt10xx/boards/sparkfun_teensy_micromod/flash_config.c index e0f5a5bd7d..abc26a2bcd 100644 --- a/ports/mimxrt10xx/boards/sparkfun_teensy_micromod/flash_config.c +++ b/ports/mimxrt10xx/boards/sparkfun_teensy_micromod/flash_config.c @@ -7,50 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - 0x432000D1, /* Teensy bootloader looks for this value*/ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -extern unsigned long _flashimagelen; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - (uint32_t)&_flashimagelen, /* actual size of image */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -64,13 +35,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqNum = 1u, }, .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, + .serialClkFreq = kFLEXSPISerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -81,20 +52,20 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -104,21 +75,21 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -131,17 +102,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -150,7 +121,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/teensy40/flash_config.c b/ports/mimxrt10xx/boards/teensy40/flash_config.c index d878124b40..30d40d7c84 100644 --- a/ports/mimxrt10xx/boards/teensy40/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy40/flash_config.c @@ -7,50 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - 0x432000D1, /* Teensy bootloader looks for this value*/ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -extern unsigned long _flashimagelen; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - (uint32_t)&_flashimagelen, /* actual size of image */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for W25Q16JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -70,13 +41,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqId = 2u, .seqNum = 1u, }, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, + .serialClkFreq = kFLEXSPISerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -87,48 +58,48 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 2: Empty - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, DUMMY_SDR, FLEXSPI_1PAD, 8), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x02), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -141,17 +112,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -160,7 +131,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/boards/teensy41/flash_config.c b/ports/mimxrt10xx/boards/teensy41/flash_config.c index e0f5a5bd7d..abc26a2bcd 100644 --- a/ports/mimxrt10xx/boards/teensy41/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy41/flash_config.c @@ -7,50 +7,21 @@ #include "boards/flash_config.h" -#include "fsl_flexspi_nor_boot.h" - - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - 0x432000D1, /* Teensy bootloader looks for this value*/ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -extern unsigned long _flashimagelen; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - (uint32_t)&_flashimagelen, /* actual size of image */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; +#include "xip/fsl_flexspi_nor_boot.h" // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz, .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, @@ -64,13 +35,13 @@ const flexspi_nor_config_t qspiflash_config = { .seqNum = 1u, }, .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, + .deviceType = kFLEXSPIDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, + .serialClkFreq = kFLEXSPISerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) // The high 16 bits is command 1 and the low are command 0. // Within a command, the top 6 bits are the opcode, the next two are the number // of pads and then last byte is the operand. The operand's meaning changes @@ -81,20 +52,20 @@ const flexspi_nor_config_t qspiflash_config = { // 0: ROM: Read LUTs // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, FLEXSPI_4PAD, 0x04), // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, // READ_SDR, FLEXSPI_1PAD, 0x04), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -104,21 +75,21 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, @@ -131,17 +102,17 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), @@ -150,7 +121,7 @@ const flexspi_nor_config_t qspiflash_config = { EMPTY_SEQUENCE, // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + SEQUENCE(FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, diff --git a/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c b/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c index f5d2e7f42e..237566b1f0 100644 --- a/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c +++ b/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c @@ -33,7 +33,7 @@ #include "py/runtime.h" -#include "fsl_adc.h" +#include "sdk/drivers/adc_12b1msps_sar/fsl_adc.h" #define ADC_CHANNEL_GROUP 0 diff --git a/ports/mimxrt10xx/common-hal/busio/I2C.c b/ports/mimxrt10xx/common-hal/busio/I2C.c index 50aae54aba..6c5bbea416 100644 --- a/ports/mimxrt10xx/common-hal/busio/I2C.c +++ b/ports/mimxrt10xx/common-hal/busio/I2C.c @@ -34,8 +34,8 @@ #include "py/runtime.h" #include "periph.h" -#include "fsl_lpi2c.h" -#include "fsl_gpio.h" +#include "sdk/drivers/lpi2c/fsl_lpi2c.h" +#include "sdk/drivers/igpio/fsl_gpio.h" #define I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (1 + CLOCK_GetDiv(kCLOCK_Lpi2cDiv))) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5 5U diff --git a/ports/mimxrt10xx/common-hal/busio/SPI.c b/ports/mimxrt10xx/common-hal/busio/SPI.c index 0048c2aeb2..d88b71a403 100644 --- a/ports/mimxrt10xx/common-hal/busio/SPI.c +++ b/ports/mimxrt10xx/common-hal/busio/SPI.c @@ -32,7 +32,7 @@ #include "py/runtime.h" #include "periph.h" -#include "fsl_lpspi.h" +#include "sdk/drivers/lpspi/fsl_lpspi.h" #include diff --git a/ports/mimxrt10xx/common-hal/busio/UART.c b/ports/mimxrt10xx/common-hal/busio/UART.c index 086b8dee87..088b2aefc6 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.c +++ b/ports/mimxrt10xx/common-hal/busio/UART.c @@ -38,8 +38,8 @@ #include "py/stream.h" #include "periph.h" -#include "fsl_lpuart.h" -#include "fsl_gpio.h" +#include "sdk/drivers/lpuart/fsl_lpuart.h" +#include "sdk/drivers/igpio/fsl_gpio.h" // ========================================================== // Debug code // ========================================================== diff --git a/ports/mimxrt10xx/common-hal/busio/UART.h b/ports/mimxrt10xx/common-hal/busio/UART.h index bc8374aabb..f09de935c2 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.h +++ b/ports/mimxrt10xx/common-hal/busio/UART.h @@ -34,7 +34,7 @@ #include "py/obj.h" #include "periph.h" -#include "fsl_lpuart.h" +#include "sdk/drivers/lpuart/fsl_lpuart.h" typedef struct { mp_obj_base_t base; diff --git a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c index d800de15de..3445cf42a0 100644 --- a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c +++ b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c @@ -32,7 +32,7 @@ #include "py/runtime.h" #include "py/mphal.h" -#include "fsl_gpio.h" +#include "sdk/drivers/igpio/fsl_gpio.h" #include "shared-bindings/microcontroller/Pin.h" #include "shared-bindings/digitalio/DigitalInOut.h" diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c index 17ced78910..9277f81d47 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c @@ -33,8 +33,8 @@ #include "shared-bindings/microcontroller/Processor.h" #include "shared-bindings/microcontroller/ResetReason.h" -#include "fsl_tempmon.h" -#include "fsl_ocotp.h" +#include "sdk/drivers/tempmon/fsl_tempmon.h" +#include "sdk/drivers/ocotp/fsl_ocotp.h" #include "clocks.h" float common_hal_mcu_processor_get_temperature(void) { diff --git a/ports/mimxrt10xx/common-hal/os/__init__.c b/ports/mimxrt10xx/common-hal/os/__init__.c index e2c43e43fa..9219242685 100644 --- a/ports/mimxrt10xx/common-hal/os/__init__.c +++ b/ports/mimxrt10xx/common-hal/os/__init__.c @@ -33,7 +33,7 @@ #include "shared-bindings/os/__init__.h" -#include "fsl_trng.h" +#include "sdk/drivers/trng/fsl_trng.h" STATIC const qstr os_uname_info_fields[] = { MP_QSTR_sysname, MP_QSTR_nodename, diff --git a/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c b/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c index c2afb38664..0bf11403d2 100644 --- a/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c +++ b/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c @@ -33,7 +33,7 @@ #include "shared-bindings/pwmio/PWMOut.h" #include "shared-bindings/microcontroller/Pin.h" -#include "fsl_pwm.h" +#include "sdk/drivers/pwm/fsl_pwm.h" #include "supervisor/shared/translate/translate.h" #include "periph.h" @@ -240,7 +240,6 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, // Disable all fault inputs flexpwm->SM[submodule].DISMAP[0] = 0; - flexpwm->SM[submodule].DISMAP[1] = 0; PWM_SetPwmLdok(flexpwm, sm_mask, false); flexpwm->SM[submodule].CTRL = PWM_CTRL_FULL_MASK | PWM_CTRL_PRSC(self->prescaler); diff --git a/ports/mimxrt10xx/common-hal/rtc/RTC.c b/ports/mimxrt10xx/common-hal/rtc/RTC.c index 0cf5fe7713..386b6a3ac5 100644 --- a/ports/mimxrt10xx/common-hal/rtc/RTC.c +++ b/ports/mimxrt10xx/common-hal/rtc/RTC.c @@ -35,8 +35,8 @@ #include "common-hal/rtc/RTC.h" #include "supervisor/shared/translate/translate.h" -#include "fsl_snvs_hp.h" -#include "fsl_snvs_lp.h" +#include "sdk/drivers/snvs_hp/fsl_snvs_hp.h" +#include "sdk/drivers/snvs_lp/fsl_snvs_lp.h" void rtc_init(void) { snvs_hp_rtc_config_t hpconfig; diff --git a/ports/mimxrt10xx/linking/common.ld b/ports/mimxrt10xx/linking/common.ld index 461a9d89eb..76c11c8d6f 100644 --- a/ports/mimxrt10xx/linking/common.ld +++ b/ports/mimxrt10xx/linking/common.ld @@ -195,6 +195,8 @@ SECTIONS . += _ld_default_stack_size; } > DTCM _ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM); + /* For the SDK's isr vector table */ + __StackTop = ORIGIN(DTCM) + LENGTH(DTCM); .ARM.attributes 0 : { *(.ARM.attributes) } } diff --git a/ports/mimxrt10xx/mphalport.c b/ports/mimxrt10xx/mphalport.c index ad0fb4d9ba..f160cf1365 100644 --- a/ports/mimxrt10xx/mphalport.c +++ b/ports/mimxrt10xx/mphalport.c @@ -35,11 +35,7 @@ #include "fsl_common.h" void mp_hal_delay_us(mp_uint_t delay) { - #if defined(MIMXRT1011_SERIES) || defined(MIMXRT1021_SERIES) SDK_DelayAtLeastUs(delay, SystemCoreClock); - #else - SDK_DelayAtLeastUs(delay); - #endif } void mp_hal_disable_all_interrupts(void) { diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h index d6d12771c5..82cb0dc69e 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h @@ -35,7 +35,7 @@ #include #include "fsl_iomuxc.h" -#include "fsl_pwm.h" +#include "sdk/drivers/pwm/fsl_pwm.h" #include "py/obj.h" extern const mp_obj_type_t mcu_pin_type; diff --git a/ports/mimxrt10xx/sdk b/ports/mimxrt10xx/sdk index 8363ff7bed..2b9354539e 160000 --- a/ports/mimxrt10xx/sdk +++ b/ports/mimxrt10xx/sdk @@ -1 +1 @@ -Subproject commit 8363ff7bed7533b9e7e6a6239aace3d6da14f349 +Subproject commit 2b9354539e6e4f722749e87b0bdc22966dc080d9 diff --git a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c index 7563f386f9..e32eaf8832 100644 --- a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c +++ b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c @@ -7,7 +7,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "fsl_flexspi.h" +#include "sdk/drivers/flexspi/fsl_flexspi.h" #include "internal_flash.h" #include "boards/flash_config.h" #include "supervisor/internal_flash.h" diff --git a/ports/mimxrt10xx/supervisor/internal_flash.c b/ports/mimxrt10xx/supervisor/internal_flash.c index 30a033a183..bacb62854a 100644 --- a/ports/mimxrt10xx/supervisor/internal_flash.c +++ b/ports/mimxrt10xx/supervisor/internal_flash.c @@ -38,8 +38,8 @@ #include "py/runtime.h" #include "lib/oofatfs/ff.h" -#include "fsl_cache.h" -#include "fsl_flexspi.h" +#include "sdk/drivers/cache/armv7-m7/fsl_cache.h" +#include "sdk/drivers/flexspi/fsl_flexspi.h" #include "fsl_iomuxc.h" // defined in linker diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c index a27ab3ea58..55bf72352d 100644 --- a/ports/mimxrt10xx/supervisor/port.c +++ b/ports/mimxrt10xx/supervisor/port.c @@ -54,8 +54,8 @@ #include "clocks.h" -#include "fsl_gpio.h" -#include "fsl_lpuart.h" +#include "sdk/drivers/igpio/fsl_gpio.h" +#include "sdk/drivers/lpuart/fsl_lpuart.h" // Device memories must be accessed in order. #define DEVICE 2 @@ -102,6 +102,36 @@ extern uint32_t _ld_isr_destination; extern uint32_t _ld_isr_size; extern uint32_t _ld_isr_flash_copy; +// Remove these once the SDK re-includes them. +// https://github.com/nxp-mcuxpresso/mcux-sdk/issues/110 +/*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +/*! CM7_CFGITCMSZ + * 0b0000..0 KB (No ITCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +/*! CM7_CFGDTCMSZ + * 0b0000..0 KB (No DTCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ + extern void main(void); // This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c.