From e1c6ed634f4387a6c9d7e132ed7d0bb245a9618a Mon Sep 17 00:00:00 2001 From: Rami Ali Date: Tue, 6 Dec 2016 10:56:06 +1100 Subject: [PATCH] stmhal: Port of f4 hal commit c568a2b to updated f7 hal. --- stmhal/hal/f7/src/stm32f7xx_hal_rcc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c index f8f51d01f8..4dd70c7fc5 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c @@ -901,7 +901,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + // dpgeorge: Adjust the way the arithmetic is done so it retains + // precision for the case that pllm doesn't evenly divide HSE_VALUE. + // Must be sure not to overflow, so divide by 4 first. HSE_VALUE + // should be a multiple of 4 (being a multiple of 100 is enough). + pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4; } else {