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atmel-samd/samd51: Use crystal for RTC 

This uses the crystal to clock the RTC on boards which have a crystal.

Disable clock generator 2 which was enabled in commit
8e2080411f ("atmel-samd: Add rtc module support").
samd51 differs from samd21 when it comes to the RTC clock. samd51 doesn't
have an explicit clock peripheral so no need for a clock generator.

The same commit didn't even setup XOSC32K correctly, it missed EN1K and XTALEN.

The RTC uses the 1k clock output, so enable it on the OSCULP32K even if it works without it.
This commit is contained in:
Noralf Trønnes 2018-06-01 16:12:48 +02:00
parent ab7ddfddd5
commit e158702a68
3 changed files with 13 additions and 4 deletions
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2
ports/atmel-samd/boards/feather_m4_express/mpconfigboard.h
View File

@ -32,6 +32,8 @@
#include "external_flash/external_flash.h" #include "external_flash/external_flash.h"
#define BOARD_HAS_CRYSTAL 1
#define DEFAULT_I2C_BUS_SCL (&pin_PA13) #define DEFAULT_I2C_BUS_SCL (&pin_PA13)
#define DEFAULT_I2C_BUS_SDA (&pin_PA12) #define DEFAULT_I2C_BUS_SDA (&pin_PA12)

2
ports/atmel-samd/boards/metro_m4_express/mpconfigboard.h
View File

@ -33,6 +33,8 @@
#include "external_flash/external_flash.h" #include "external_flash/external_flash.h"
#define BOARD_HAS_CRYSTAL 1
#define DEFAULT_I2C_BUS_SCL (&pin_PB03) #define DEFAULT_I2C_BUS_SCL (&pin_PB03)
#define DEFAULT_I2C_BUS_SDA (&pin_PB02) #define DEFAULT_I2C_BUS_SDA (&pin_PB02)

13
ports/atmel-samd/samd51_clocks.c
View File

@ -81,12 +81,14 @@ void disable_clock_generator(uint8_t gclk) {
static void init_clock_source_osculp32k(void) { static void init_clock_source_osculp32k(void) {
// Calibration value is loaded at startup // Calibration value is loaded at startup
OSC32KCTRL->OSCULP32K.bit.EN1K = 0; OSC32KCTRL->OSCULP32K.bit.EN1K = 1;
OSC32KCTRL->OSCULP32K.bit.EN32K = 0; OSC32KCTRL->OSCULP32K.bit.EN32K = 0;
} }
static void init_clock_source_xosc32k(void) { static void init_clock_source_xosc32k(void) {
OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ONDEMAND | OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ONDEMAND |
OSC32KCTRL_XOSC32K_EN1K |
OSC32KCTRL_XOSC32K_XTALEN |
OSC32KCTRL_XOSC32K_ENABLE | OSC32KCTRL_XOSC32K_ENABLE |
OSC32KCTRL_XOSC32K_CGM(1); OSC32KCTRL_XOSC32K_CGM(1);
} }
@ -105,15 +107,18 @@ void clock_init(void) {
// DFLL48M is enabled by default // DFLL48M is enabled by default
init_clock_source_osculp32k(); init_clock_source_osculp32k();
init_clock_source_xosc32k();
OSC32KCTRL->RTCCTRL.bit.RTCSEL = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val; if (board_has_crystal()) {
init_clock_source_xosc32k();
OSC32KCTRL->RTCCTRL.bit.RTCSEL = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val;
} else {
OSC32KCTRL->RTCCTRL.bit.RTCSEL = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val;
}
MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV(1); MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV(1);
enable_clock_generator_sync(0, GCLK_GENCTRL_SRC_DPLL0_Val, 1, false); enable_clock_generator_sync(0, GCLK_GENCTRL_SRC_DPLL0_Val, 1, false);
enable_clock_generator_sync(1, GCLK_GENCTRL_SRC_DFLL_Val, 1, false); enable_clock_generator_sync(1, GCLK_GENCTRL_SRC_DFLL_Val, 1, false);
enable_clock_generator_sync(2, GCLK_GENCTRL_SRC_OSCULP32K_Val, 32, false);
enable_clock_generator_sync(4, GCLK_GENCTRL_SRC_DPLL0_Val, 1, false); enable_clock_generator_sync(4, GCLK_GENCTRL_SRC_DPLL0_Val, 1, false);
enable_clock_generator_sync(5, GCLK_GENCTRL_SRC_DFLL_Val, 24, false); enable_clock_generator_sync(5, GCLK_GENCTRL_SRC_DFLL_Val, 24, false);