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nrf5/hal: Updating clock frequency enums and lookup table for quad spi.

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This commit is contained in:
Glenn Ruben Bakke 2017-01-22 19:15:24 +01:00
parent a7f3217c95
commit e02c90dca5
2 changed files with 29 additions and 0 deletions
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9
nrf5/hal/hal_qspie.c
View File

@ -32,4 +32,13 @@
#define QSPI_IRQ_NUM QSPI_IRQn
#define QSPI_BASE ((NRF_QSPI_Type *)NRF_QSPI_BASE)
// frequency, 32 MHz / (SCKFREQ + 1)
static const uint32_t hal_qspi_frequency_lookup[] = {
QSPI_FREQUENCY_FREQUENCY_M2 = (15 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 2 Mbps
QSPI_FREQUENCY_FREQUENCY_M4 = (7 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 4 Mbps
QSPI_FREQUENCY_FREQUENCY_M8 = (3 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 8 Mbps
QSPI_FREQUENCY_FREQUENCY_M16 = (1 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 16 Mbps
QSPI_FREQUENCY_FREQUENCY_M32 = (0 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps
};
#endif // HAL_QSPIE_MODULE_ENABLED

20
nrf5/hal/hal_qspie.h
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@ -35,4 +35,24 @@
#error "Device not supported."
#endif
/**
* @brief Quad SPI clock frequency type definition
*/
typedef enum {
HAL_FREQ_2_Mbps,
HAL_FREQ_4_Mbps,
HAL_FREQ_8_Mbps,
HAL_FREQ_16_Mbps,
HAL_FREQ_32_Mbps
} hal_qspi_clk_freq_t;
/**
* @brief Quad SPI mode configuration type definition
*/
typedef enum {
HAL_QSPI_MODE_SINGLE_LINE,
HAL_QSPI_MODE_DUAL_LINE,
HAL_QSPI_MODE_QUAL_LINE
} hal_qspi_mode_t;
#endif // HAL_QSPIE_H__