stm32/eth: Add support for H7 processors.
This commit is contained in:
parent
cd61fc8e44
commit
d986b20122
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@ -61,7 +61,19 @@
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#define PHY_SCSR_SPEED_100FULL (6 << PHY_SCSR_SPEED_Pos)
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// ETH DMA RX and TX descriptor definitions
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#if defined(STM32H7)
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#define RX_DESCR_3_OWN_Pos (31)
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#define RX_DESCR_3_IOC_Pos (30)
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#define RX_DESCR_3_BUF1V_Pos (24)
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#define RX_DESCR_3_PL_Msk (0x7fff)
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#define TX_DESCR_3_OWN_Pos (31)
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#define TX_DESCR_3_LD_Pos (29)
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#define TX_DESCR_3_FD_Pos (28)
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#define TX_DESCR_3_CIC_Pos (16)
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#define TX_DESCR_2_B1L_Pos (0)
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#define TX_DESCR_2_B1L_Msk (0x3fff << TX_DESCR_2_B1L_Pos)
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#else
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#define RX_DESCR_0_OWN_Pos (31)
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#define RX_DESCR_0_FL_Pos (16)
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#define RX_DESCR_0_FL_Msk (0x3fff << RX_DESCR_0_FL_Pos)
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@ -78,6 +90,7 @@
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#define TX_DESCR_0_TER_Pos (21)
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#define TX_DESCR_0_TCH_Pos (20)
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#define TX_DESCR_1_TBS1_Pos (0)
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#endif
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// Configuration values
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@ -121,6 +134,20 @@ STATIC void eth_mac_deinit(eth_t *self);
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STATIC void eth_process_frame(eth_t *self, size_t len, const uint8_t *buf);
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STATIC void eth_phy_write(uint32_t reg, uint32_t val) {
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#if defined(STM32H7)
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while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
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}
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uint32_t ar = ETH->MACMDIOAR;
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ar &= ~ETH_MACMDIOAR_RDA_Msk;
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ar |= reg << ETH_MACMDIOAR_RDA_Pos;
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ar &= ~ETH_MACMDIOAR_MOC_Msk;
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ar |= ETH_MACMDIOAR_MOC_WR;
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ar |= ETH_MACMDIOAR_MB;
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ETH->MACMDIODR = val;
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ETH->MACMDIOAR = ar;
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while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
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}
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#else
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while (ETH->MACMIIAR & ETH_MACMIIAR_MB) {
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}
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ETH->MACMIIDR = val;
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@ -129,9 +156,24 @@ STATIC void eth_phy_write(uint32_t reg, uint32_t val) {
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ETH->MACMIIAR = ar;
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while (ETH->MACMIIAR & ETH_MACMIIAR_MB) {
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}
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#endif
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}
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STATIC uint32_t eth_phy_read(uint32_t reg) {
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#if defined(STM32H7)
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while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
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}
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uint32_t ar = ETH->MACMDIOAR;
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ar &= ~ETH_MACMDIOAR_RDA_Msk;
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ar |= reg << ETH_MACMDIOAR_RDA_Pos;
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ar &= ~ETH_MACMDIOAR_MOC_Msk;
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ar |= ETH_MACMDIOAR_MOC_RD;
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ar |= ETH_MACMDIOAR_MB;
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ETH->MACMDIOAR = ar;
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while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
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}
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return ETH->MACMDIODR;
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#else
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while (ETH->MACMIIAR & ETH_MACMIIAR_MB) {
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}
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uint32_t ar = ETH->MACMIIAR;
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@ -140,6 +182,7 @@ STATIC uint32_t eth_phy_read(uint32_t reg) {
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while (ETH->MACMIIAR & ETH_MACMIIAR_MB) {
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}
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return ETH->MACMIIDR;
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#endif
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}
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void eth_init(eth_t *self, int mac_idx) {
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@ -160,7 +203,7 @@ STATIC int eth_mac_init(eth_t *self) {
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// Configure GPIO
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_MDC, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_MDC);
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_MDIO, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_MDIO);
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_REF_CLK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_RMII_REF_CLK);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_ETH_RMII_REF_CLK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_MEDIUM, STATIC_AF_ETH_RMII_REF_CLK);
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_CRS_DV, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_RMII_CRS_DV);
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_RXD0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_RMII_RXD0);
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_RXD1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_RMII_RXD1);
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@ -168,26 +211,53 @@ STATIC int eth_mac_init(eth_t *self) {
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_TXD0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_RMII_TXD0);
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_TXD1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_RMII_TXD1);
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#if defined(STM32H7)
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__HAL_RCC_ETH1MAC_CLK_ENABLE();
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__HAL_RCC_ETH1TX_CLK_ENABLE();
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__HAL_RCC_ETH1RX_CLK_ENABLE();
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__HAL_RCC_ETH1MAC_FORCE_RESET();
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#else
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__HAL_RCC_ETH_CLK_ENABLE();
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__HAL_RCC_ETHMAC_FORCE_RESET();
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#endif
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// Select RMII interface
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#if defined(STM32H7)
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SYSCFG->PMCR = (SYSCFG->PMCR & ~SYSCFG_PMCR_EPIS_SEL_Msk) | SYSCFG_PMCR_EPIS_SEL_2;
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#else
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
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#endif
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#if defined(STM32H7)
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__HAL_RCC_ETH1MAC_RELEASE_RESET();
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__HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE();
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__HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE();
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__HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE();
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#else
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__HAL_RCC_ETHMAC_RELEASE_RESET();
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__HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE();
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__HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE();
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__HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE();
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#endif
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// Do a soft reset of the MAC core
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ETH->DMABMR = ETH_DMABMR_SR;
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#if defined(STM32H7)
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#define ETH_SOFT_RESET(eth) do { eth->DMAMR = ETH_DMAMR_SWR; } while (0)
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#define ETH_IS_RESET(eth) (eth->DMAMR & ETH_DMAMR_SWR)
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#else
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#define ETH_SOFT_RESET(eth) do { eth->DMABMR = ETH_DMABMR_SR; } while (0)
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#define ETH_IS_RESET(eth) (eth->DMABMR & ETH_DMABMR_SR)
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#endif
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ETH_SOFT_RESET(ETH);
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mp_hal_delay_ms(2);
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// Wait for soft reset to finish
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uint32_t t0 = mp_hal_ticks_ms();
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while (ETH->DMABMR & ETH_DMABMR_SR) {
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while (ETH_IS_RESET(ETH)) {
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if (mp_hal_ticks_ms() - t0 > 1000) {
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return -MP_ETIMEDOUT;
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}
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@ -196,6 +266,21 @@ STATIC int eth_mac_init(eth_t *self) {
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// Set MII clock range
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uint32_t hclk = HAL_RCC_GetHCLKFreq();
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uint32_t cr_div;
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#if defined(STM32H7)
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cr_div = ETH->MACMDIOAR & ~ETH_MACMDIOAR_CR;
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if (hclk < 35000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV16;
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} else if (hclk < 60000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV26;
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} else if (hclk < 100000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV42;
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} else if (hclk < 150000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV62;
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} else {
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cr_div |= ETH_MACMDIOAR_CR_DIV102;
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}
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ETH->MACMDIOAR = cr_div;
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#else
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if (hclk < 35000000) {
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cr_div = ETH_MACMIIAR_CR_Div16;
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} else if (hclk < 60000000) {
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@ -208,6 +293,12 @@ STATIC int eth_mac_init(eth_t *self) {
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cr_div = ETH_MACMIIAR_CR_Div102;
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}
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ETH->MACMIIAR = cr_div;
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#endif
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#if defined(STM32H7)
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// don't skip 32bit words since our desriptors are continuous in memory
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ETH->DMACCR &= ~(ETH_DMACCR_DSL_Msk);
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#endif
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// Reset the PHY
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eth_phy_write(PHY_BCR, PHY_BCR_SOFT_RESET);
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@ -249,17 +340,36 @@ STATIC int eth_mac_init(eth_t *self) {
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uint16_t phy_scsr = eth_phy_read(PHY_SCSR);
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// Burst mode configuration
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#if defined(STM32H7)
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ETH->DMASBMR = ETH->DMASBMR & ~ETH_DMASBMR_AAL & ~ETH_DMASBMR_FB;
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#else
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ETH->DMABMR = 0;
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#endif
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mp_hal_delay_ms(2);
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// Select DMA interrupts
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#if defined(STM32H7)
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ETH->DMACIER = ETH->DMACIER
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| ETH_DMACIER_NIE // enable normal interrupts
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| ETH_DMACIER_RIE // enable RX interrupt
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;
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#else
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ETH->DMAIER =
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ETH_DMAIER_NISE // enable normal interrupts
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| ETH_DMAIER_RIE // enable RX interrupt
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;
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#endif
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// Configure RX descriptor lists
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for (size_t i = 0; i < RX_BUF_NUM; ++i) {
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#if defined(STM32H7)
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eth_dma.rx_descr[i].rdes3 =
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1 << RX_DESCR_3_OWN_Pos
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| (1 << RX_DESCR_3_BUF1V_Pos) // buf1 address valid
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| (1 << RX_DESCR_3_IOC_Pos) // Interrupt Enabled on Completion
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;
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eth_dma.rx_descr[i].rdes0 = (uint32_t)ð_dma.rx_buf[i * RX_BUF_SIZE]; // buf 1 address
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#else
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eth_dma.rx_descr[i].rdes0 = 1 << RX_DESCR_0_OWN_Pos;
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eth_dma.rx_descr[i].rdes1 =
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1 << RX_DESCR_1_RCH_Pos // chained
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@ -267,31 +377,64 @@ STATIC int eth_mac_init(eth_t *self) {
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;
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eth_dma.rx_descr[i].rdes2 = (uint32_t)ð_dma.rx_buf[i * RX_BUF_SIZE];
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eth_dma.rx_descr[i].rdes3 = (uint32_t)ð_dma.rx_descr[(i + 1) % RX_BUF_NUM];
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#endif
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}
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#if defined(STM32H7)
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ETH->DMACRDLAR = (uint32_t)ð_dma.rx_descr[0];
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#else
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ETH->DMARDLAR = (uint32_t)ð_dma.rx_descr[0];
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#endif
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eth_dma.rx_descr_idx = 0;
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// Configure TX descriptor lists
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for (size_t i = 0; i < TX_BUF_NUM; ++i) {
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#if defined(STM32H7)
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eth_dma.tx_descr[i].tdes0 = 0;
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eth_dma.tx_descr[i].tdes1 = 0;
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eth_dma.tx_descr[i].tdes2 = TX_BUF_SIZE & TX_DESCR_2_B1L_Msk;
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eth_dma.tx_descr[i].tdes3 = 0;
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#else
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eth_dma.tx_descr[i].tdes0 = 1 << TX_DESCR_0_TCH_Pos;
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eth_dma.tx_descr[i].tdes1 = 0;
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eth_dma.tx_descr[i].tdes2 = 0;
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eth_dma.tx_descr[i].tdes3 = (uint32_t)ð_dma.tx_descr[(i + 1) % TX_BUF_NUM];
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#endif
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}
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#if defined(STM32H7)
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// set number of descriptors and buffers
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ETH->DMACTDRLR = TX_BUF_NUM - 1;
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ETH->DMACRDRLR = RX_BUF_NUM - 1;
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ETH->DMACTDLAR = (uint32_t)ð_dma.tx_descr[0];
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#else
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ETH->DMATDLAR = (uint32_t)ð_dma.tx_descr[0];
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#endif
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eth_dma.tx_descr_idx = 0;
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// Configure DMA
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#if defined(STM32H7)
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// read from RX FIFO only after a full frame is written
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ETH->MTLRQOMR = ETH_MTLRQOMR_RSF;
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// transmission starts when a full packet resides in the Tx queue
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ETH->MTLTQOMR = ETH_MTLTQOMR_TSF;
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#else
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ETH->DMAOMR =
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ETH_DMAOMR_RSF // read from RX FIFO after a full frame is written
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| ETH_DMAOMR_TSF // transmit when a full frame is in TX FIFO (needed by errata)
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;
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#endif
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mp_hal_delay_ms(2);
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// Select MAC filtering options
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#if defined(STM32H7)
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ETH->MACPFR = ETH_MACPFR_RA; // pass all frames up
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#else
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ETH->MACFFR =
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ETH_MACFFR_RA // pass all frames up
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;
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#endif
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mp_hal_delay_ms(2);
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// Set MAC address
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@ -318,10 +461,15 @@ STATIC int eth_mac_init(eth_t *self) {
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mp_hal_delay_ms(2);
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// Start DMA layer
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#if defined(STM32H7)
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ETH->DMACRCR |= ETH_DMACRCR_SR; // start RX
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ETH->DMACTCR |= ETH_DMACTCR_ST; // start TX
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#else
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ETH->DMAOMR |=
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ETH_DMAOMR_ST // start TX
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| ETH_DMAOMR_SR // start RX
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;
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#endif
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mp_hal_delay_ms(2);
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// Enable interrupts
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@ -334,9 +482,15 @@ STATIC int eth_mac_init(eth_t *self) {
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STATIC void eth_mac_deinit(eth_t *self) {
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(void)self;
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HAL_NVIC_DisableIRQ(ETH_IRQn);
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#if defined(STM32H7)
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__HAL_RCC_ETH1MAC_FORCE_RESET();
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__HAL_RCC_ETH1MAC_RELEASE_RESET();
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__HAL_RCC_ETH1MAC_CLK_DISABLE();
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#else
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__HAL_RCC_ETHMAC_FORCE_RESET();
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__HAL_RCC_ETHMAC_RELEASE_RESET();
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__HAL_RCC_ETH_CLK_DISABLE();
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#endif
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}
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STATIC int eth_tx_buf_get(size_t len, uint8_t **buf) {
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@ -348,19 +502,32 @@ STATIC int eth_tx_buf_get(size_t len, uint8_t **buf) {
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eth_dma_tx_descr_t *tx_descr = ð_dma.tx_descr[eth_dma.tx_descr_idx];
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uint32_t t0 = mp_hal_ticks_ms();
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for (;;) {
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#if defined(STM32H7)
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if (!(tx_descr->tdes3 & (1 << TX_DESCR_3_OWN_Pos))) {
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break;
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}
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#else
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if (!(tx_descr->tdes0 & (1 << TX_DESCR_0_OWN_Pos))) {
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break;
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}
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#endif
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if (mp_hal_ticks_ms() - t0 > 1000) {
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return -MP_ETIMEDOUT;
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}
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}
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#if defined(STM32H7)
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// Update TX descriptor with length and buffer pointer
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*buf = ð_dma.tx_buf[eth_dma.tx_descr_idx * TX_BUF_SIZE];
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tx_descr->tdes2 = len & TX_DESCR_2_B1L_Msk;
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tx_descr->tdes0 = (uint32_t)*buf;
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#else
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// Update TX descriptor with length, buffer pointer and linked list pointer
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*buf = ð_dma.tx_buf[eth_dma.tx_descr_idx * TX_BUF_SIZE];
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tx_descr->tdes1 = len << TX_DESCR_1_TBS1_Pos;
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tx_descr->tdes2 = (uint32_t)*buf;
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tx_descr->tdes3 = (uint32_t)ð_dma.tx_descr[(eth_dma.tx_descr_idx + 1) % TX_BUF_NUM];
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#endif
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return 0;
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}
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@ -371,6 +538,14 @@ STATIC int eth_tx_buf_send(void) {
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eth_dma.tx_descr_idx = (eth_dma.tx_descr_idx + 1) % TX_BUF_NUM;
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// Schedule to send next outgoing frame
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#if defined(STM32H7)
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tx_descr->tdes3 =
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1 << TX_DESCR_3_OWN_Pos // owned by DMA
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| 1 << TX_DESCR_3_LD_Pos // last segment
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| 1 << TX_DESCR_3_FD_Pos // first segment
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| 3 << TX_DESCR_3_CIC_Pos // enable all checksums inserted by hardware
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;
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#else
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tx_descr->tdes0 =
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1 << TX_DESCR_0_OWN_Pos // owned by DMA
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| 1 << TX_DESCR_0_LS_Pos // last segment
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@ -378,13 +553,21 @@ STATIC int eth_tx_buf_send(void) {
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| 3 << TX_DESCR_0_CIC_Pos // enable all checksums inserted by hardware
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| 1 << TX_DESCR_0_TCH_Pos // TX descriptor is chained
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;
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#endif
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// Notify ETH DMA that there is a new TX descriptor for sending
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__DMB();
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#if defined(STM32H7)
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if (ETH->DMACSR & ETH_DMACSR_TBU) {
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ETH->DMACSR = ETH_DMACSR_TBU;
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}
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ETH->DMACTDTPR = (uint32_t)ð_dma.tx_descr[eth_dma.tx_descr_idx];
|
||||
#else
|
||||
if (ETH->DMASR & ETH_DMASR_TBUS) {
|
||||
ETH->DMASR = ETH_DMASR_TBUS;
|
||||
ETH->DMATPDR = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -396,6 +579,12 @@ STATIC void eth_dma_rx_free(void) {
|
|||
eth_dma.rx_descr_idx = (eth_dma.rx_descr_idx + 1) % RX_BUF_NUM;
|
||||
|
||||
// Schedule to get next incoming frame
|
||||
#if defined(STM32H7)
|
||||
rx_descr->rdes0 = (uint32_t)buf;
|
||||
rx_descr->rdes3 = 1 << RX_DESCR_3_OWN_Pos; // owned by DMA
|
||||
rx_descr->rdes3 |= 1 << RX_DESCR_3_BUF1V_Pos; // buf 1 address valid
|
||||
rx_descr->rdes3 |= 1 << RX_DESCR_3_IOC_Pos; // Interrupt Enabled on Completion
|
||||
#else
|
||||
rx_descr->rdes1 =
|
||||
1 << RX_DESCR_1_RCH_Pos // RX descriptor is chained
|
||||
| RX_BUF_SIZE << RX_DESCR_1_RBS1_Pos // maximum buffer length
|
||||
|
@ -403,28 +592,60 @@ STATIC void eth_dma_rx_free(void) {
|
|||
rx_descr->rdes2 = (uint32_t)buf;
|
||||
rx_descr->rdes3 = (uint32_t)ð_dma.rx_descr[eth_dma.rx_descr_idx];
|
||||
rx_descr->rdes0 = 1 << RX_DESCR_0_OWN_Pos; // owned by DMA
|
||||
#endif
|
||||
|
||||
// Notify ETH DMA that there is a new RX descriptor available
|
||||
__DMB();
|
||||
#if defined(STM32H7)
|
||||
ETH->DMACRDTPR = (uint32_t)&rx_descr[eth_dma.rx_descr_idx];
|
||||
#else
|
||||
ETH->DMARPDR = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
void ETH_IRQHandler(void) {
|
||||
#if defined(STM32H7)
|
||||
uint32_t sr = ETH->DMACSR;
|
||||
ETH->DMACSR = ETH_DMACSR_NIS;
|
||||
uint32_t rx_interrupt = sr & ETH_DMACSR_RI;
|
||||
#else
|
||||
uint32_t sr = ETH->DMASR;
|
||||
ETH->DMASR = ETH_DMASR_NIS;
|
||||
if (sr & ETH_DMASR_RS) {
|
||||
uint32_t rx_interrupt = sr & ETH_DMASR_RS;
|
||||
#endif
|
||||
if (rx_interrupt) {
|
||||
#if defined(STM32H7)
|
||||
ETH->DMACSR = ETH_DMACSR_RI;
|
||||
#else
|
||||
ETH->DMASR = ETH_DMASR_RS;
|
||||
#endif
|
||||
for (;;) {
|
||||
#if defined(STM32H7)
|
||||
eth_dma_rx_descr_t *rx_descr_l = ð_dma.rx_descr[eth_dma.rx_descr_idx];
|
||||
if (rx_descr_l->rdes3 & (1 << RX_DESCR_3_OWN_Pos)) {
|
||||
// No more RX descriptors ready to read
|
||||
break;
|
||||
}
|
||||
#else
|
||||
eth_dma_rx_descr_t *rx_descr = ð_dma.rx_descr[eth_dma.rx_descr_idx];
|
||||
if (rx_descr->rdes0 & (1 << RX_DESCR_0_OWN_Pos)) {
|
||||
// No more RX descriptors ready to read
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
// Get RX buffer containing new frame
|
||||
#if defined(STM32H7)
|
||||
size_t len = (rx_descr_l->rdes3 & RX_DESCR_3_PL_Msk);
|
||||
#else
|
||||
size_t len = (rx_descr->rdes0 & RX_DESCR_0_FL_Msk) >> RX_DESCR_0_FL_Pos;
|
||||
#endif
|
||||
len -= 4; // discard CRC at end
|
||||
#if defined(STM32H7)
|
||||
uint8_t *buf = ð_dma.rx_buf[eth_dma.rx_descr_idx * RX_BUF_SIZE];
|
||||
#else
|
||||
uint8_t *buf = (uint8_t *)rx_descr->rdes2;
|
||||
#endif
|
||||
|
||||
// Process frame
|
||||
eth_process_frame(ð_instance, len, buf);
|
||||
|
|
Loading…
Reference in New Issue