mimxrt/boards: Add the Seeed ARCH MIX board.
The ARCH MIX board exposes the Ethernet Pins at it's connectors. Therefore the software is configured for using a LAN8720 PHY device. Breakout boards with the LAN8720 are easily available.
This commit is contained in:
robert-hh
Damien George
parent
c3dceb1c32
commit
d72d699dad
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/*
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* Copyright 2019 NXP.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// Based on tinyusb/hw/bsp/teensy_40/evkmimxrt1020_flexspi_nor_config.h
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#ifndef __SEEED_ARCH_MIX_FLEXSPI_NOR_CONFIG__
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#define __SEEED_ARCH_MIX_FLEXSPI_NOR_CONFIG__
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#include <stdint.h>
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#include <stdbool.h>
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#include "fsl_common.h"
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/*! @name Driver version */
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/*@{*/
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/*! @brief XIP_BOARD driver version 2.0.0. */
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#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/* FLEXSPI memory config block related defintions */
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#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
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#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
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#define FLEXSPI_CFG_BLK_SIZE (512)
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/* FLEXSPI Feature related definitions */
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#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
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/* Lookup table related defintions */
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#define CMD_INDEX_READ 0
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#define CMD_INDEX_READSTATUS 1
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#define CMD_INDEX_WRITEENABLE 2
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#define CMD_INDEX_WRITE 4
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#define CMD_LUT_SEQ_IDX_READ 0
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#define CMD_LUT_SEQ_IDX_READSTATUS 1
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#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define CMD_LUT_SEQ_IDX_WRITE 9
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#define CMD_SDR 0x01
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#define CMD_DDR 0x21
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#define RADDR_SDR 0x02
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#define RADDR_DDR 0x22
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#define CADDR_SDR 0x03
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#define CADDR_DDR 0x23
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#define MODE1_SDR 0x04
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#define MODE1_DDR 0x24
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#define MODE2_SDR 0x05
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#define MODE2_DDR 0x25
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#define MODE4_SDR 0x06
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#define MODE4_DDR 0x26
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#define MODE8_SDR 0x07
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#define MODE8_DDR 0x27
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#define WRITE_SDR 0x08
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#define WRITE_DDR 0x28
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#define READ_SDR 0x09
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#define READ_DDR 0x29
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#define LEARN_SDR 0x0A
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#define LEARN_DDR 0x2A
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#define DATSZ_SDR 0x0B
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#define DATSZ_DDR 0x2B
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#define DUMMY_SDR 0x0C
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#define DUMMY_DDR 0x2C
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#define DUMMY_RWDS_SDR 0x0D
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#define DUMMY_RWDS_DDR 0x2D
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#define JMP_ON_CS 0x1F
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#define STOP 0
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#define FLEXSPI_1PAD 0
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#define FLEXSPI_2PAD 1
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#define FLEXSPI_4PAD 2
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#define FLEXSPI_8PAD 3
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#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
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FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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// !@brief Definitions for FlexSPI Serial Clock Frequency
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typedef enum _FlexSpiSerialClockFreq
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{
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_133MHz = 7,
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kFlexSpiSerialClk_166MHz = 8,
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kFlexSpiSerialClk_200MHz = 9,
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} flexspi_serial_clk_freq_t;
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// !@brief FlexSPI clock configuration type
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enum
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{
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kFlexSpiClk_SDR, // !< Clock configure for SDR mode
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kFlexSpiClk_DDR, // !< Clock configurat for DDR mode
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};
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// !@brief FlexSPI Read Sample Clock Source definition
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typedef enum _FlashReadSampleClkSource
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{
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kFlexSPIReadSampleClk_LoopbackInternally = 0,
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kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
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kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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} flexspi_read_sample_clk_t;
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// !@brief Misc feature bit definitions
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enum
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{
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kFlexSpiMiscOffset_DiffClkEnable = 0, // !< Bit for Differential clock enable
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kFlexSpiMiscOffset_Ck2Enable = 1, // !< Bit for CK2 enable
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kFlexSpiMiscOffset_ParallelEnable = 2, // !< Bit for Parallel mode enable
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kFlexSpiMiscOffset_WordAddressableEnable = 3, // !< Bit for Word Addressable enable
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, // !< Bit for Safe Configuration Frequency enable
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, // !< Bit for Pad setting override enable
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kFlexSpiMiscOffset_DdrModeEnable = 6, // !< Bit for DDR clock confiuration indication.
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};
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// !@brief Flash Type Definition
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enum
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{
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kFlexSpiDeviceType_SerialNOR = 1, // !< Flash devices are Serial NOR
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kFlexSpiDeviceType_SerialNAND = 2, // !< Flash devices are Serial NAND
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kFlexSpiDeviceType_SerialRAM = 3, // !< Flash devices are Serial RAM/HyperFLASH
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kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, // !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, // !< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
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};
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// !@brief Flash Pad Definitions
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enum
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{
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kSerialFlash_1Pad = 1,
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kSerialFlash_2Pads = 2,
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kSerialFlash_4Pads = 4,
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kSerialFlash_8Pads = 8,
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};
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// !@brief FlexSPI LUT Sequence structure
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typedef struct _lut_sequence
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{
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uint8_t seqNum; // !< Sequence Number, valid number: 1-16
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uint8_t seqId; // !< Sequence Index, valid number: 0-15
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uint16_t reserved;
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} flexspi_lut_seq_t;
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// !@brief Flash Configuration Command Type
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enum
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{
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kDeviceConfigCmdType_Generic, // !< Generic command, for example: configure dummy cycles, drive strength, etc
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kDeviceConfigCmdType_QuadEnable, // !< Quad Enable command
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kDeviceConfigCmdType_Spi2Xpi, // !< Switch from SPI to DPI/QPI/OPI mode
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kDeviceConfigCmdType_Xpi2Spi, // !< Switch from DPI/QPI/OPI to SPI mode
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kDeviceConfigCmdType_Spi2NoCmd, // !< Switch to 0-4-4/0-8-8 mode
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kDeviceConfigCmdType_Reset, // !< Reset device command
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};
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// !@brief FlexSPI Memory Configuration Block
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typedef struct _FlexSPIConfig
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{
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uint32_t tag; // !< [0x000-0x003] Tag, fixed value 0x42464346UL
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uint32_t version; // !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
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uint32_t reserved0; // !< [0x008-0x00b] Reserved for future use
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uint8_t readSampleClkSrc; // !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
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uint8_t csHoldTime; // !< [0x00d-0x00d] CS hold time, default value: 3
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uint8_t csSetupTime; // !< [0x00e-0x00e] CS setup time, default value: 3
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uint8_t columnAddressWidth; // !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
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// ! Serial NAND, need to refer to datasheet
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uint8_t deviceModeCfgEnable; // !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
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uint8_t deviceModeType; // !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
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// ! Generic configuration, etc.
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uint16_t waitTimeCfgCommands; // !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
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// ! DPI/QPI/OPI switch or reset command
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flexspi_lut_seq_t deviceModeSeq; // !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
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// ! sequence number, [31:16] Reserved
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uint32_t deviceModeArg; // !< [0x018-0x01b] Argument/Parameter for device configuration
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uint8_t configCmdEnable; // !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
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uint8_t configModeType[3]; // !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
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flexspi_lut_seq_t
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configCmdSeqs[3]; // !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
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uint32_t reserved1; // !< [0x02c-0x02f] Reserved for future use
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uint32_t configCmdArgs[3]; // !< [0x030-0x03b] Arguments/Parameters for device Configuration commands
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uint32_t reserved2; // !< [0x03c-0x03f] Reserved for future use
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uint32_t controllerMiscOption; // !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
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// ! details
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uint8_t deviceType; // !< [0x044-0x044] Device Type: See Flash Type Definition for more details
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uint8_t sflashPadType; // !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
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uint8_t serialClkFreq; // !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
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// ! Chapter for more details
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uint8_t lutCustomSeqEnable; // !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
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// ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
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uint32_t reserved3[2]; // !< [0x048-0x04f] Reserved for future use
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uint32_t sflashA1Size; // !< [0x050-0x053] Size of Flash connected to A1
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uint32_t sflashA2Size; // !< [0x054-0x057] Size of Flash connected to A2
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uint32_t sflashB1Size; // !< [0x058-0x05b] Size of Flash connected to B1
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uint32_t sflashB2Size; // !< [0x05c-0x05f] Size of Flash connected to B2
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uint32_t csPadSettingOverride; // !< [0x060-0x063] CS pad setting override value
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uint32_t sclkPadSettingOverride; // !< [0x064-0x067] SCK pad setting override value
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uint32_t dataPadSettingOverride; // !< [0x068-0x06b] data pad setting override value
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uint32_t dqsPadSettingOverride; // !< [0x06c-0x06f] DQS pad setting override value
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uint32_t timeoutInMs; // !< [0x070-0x073] Timeout threshold for read status command
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uint32_t commandInterval; // !< [0x074-0x077] CS deselect interval between two commands
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uint16_t dataValidTime[2]; // !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
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uint16_t busyOffset; // !< [0x07c-0x07d] Busy offset, valid value: 0-31
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uint16_t busyBitPolarity; // !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
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// ! busy flag is 0 when flash device is busy
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uint32_t lookupTable[64]; // !< [0x080-0x17f] Lookup table holds Flash command sequences
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flexspi_lut_seq_t lutCustomSeq[12]; // !< [0x180-0x1af] Customizable LUT Sequences
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uint32_t reserved4[4]; // !< [0x1b0-0x1bf] Reserved for future use
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} flexspi_mem_config_t;
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/* */
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#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
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#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
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#define NOR_CMD_LUT_SEQ_IDX_READID 8
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
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#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
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#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
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#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
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/*
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* Serial NOR configuration block
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*/
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typedef struct _flexspi_nor_config
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{
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flexspi_mem_config_t memConfig; // !< Common memory configuration info via FlexSPI
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uint32_t pageSize; // !< Page size of Serial NOR
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uint32_t sectorSize; // !< Sector size of Serial NOR
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uint8_t ipcmdSerialClkFreq; // !< Clock frequency for IP command
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uint8_t isUniformBlockSize; // !< Sector/Block size is the same
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uint8_t reserved0[2]; // !< Reserved for future use
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uint8_t serialNorType; // !< Serial NOR Flash type: 0/1/2/3
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uint8_t needExitNoCmdMode; // !< Need to exit NoCmd mode before other IP command
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uint8_t halfClkForNonReadCmd; // !< Half the Serial Clock for non-read command: true/false
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uint8_t needRestoreNoCmdMode; // !< Need to Restore NoCmd mode after IP commmand execution
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uint32_t blockSize; // !< Block size
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uint32_t reserve2[11]; // !< Reserved for future use
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} flexspi_nor_config_t;
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#define FLASH_BUSY_STATUS_POL 0
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#define FLASH_BUSY_STATUS_OFFSET 0
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SEEED_ARCH_MIX_FLEXSPI_NOR_CONFIG__ */
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20
ports/mimxrt/boards/SEEED_ARCH_MIX/board.json
Normal file
20
ports/mimxrt/boards/SEEED_ARCH_MIX/board.json
Normal file
@ -0,0 +1,20 @@
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{
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"deploy": [
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"deploy.md"
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],
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"docs": "",
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"features": [
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"MicroSD",
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"MicroUSB",
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"SDRAM",
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"RGB LED"
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],
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"images": [
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"main1.jpg"
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],
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"mcu": "mimxrt",
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"product": "Arch Mix",
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"thumbnail": "",
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"url": "https://wiki.seeedstudio.com/Arch_Mix/",
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"vendor": "Seeed Technology Co.,Ltd."
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}
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119
ports/mimxrt/boards/SEEED_ARCH_MIX/clock_config.h
Normal file
119
ports/mimxrt/boards/SEEED_ARCH_MIX/clock_config.h
Normal file
@ -0,0 +1,119 @@
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/*
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* Copyright 2017-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _CLOCK_CONFIG_H_
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#define _CLOCK_CONFIG_H_
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#include "fsl_common.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes default configuration of clocks.
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*
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*/
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void BOARD_InitBootClocks(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockRUN configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
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/* Clock outputs (values are in Hz): */
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#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
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#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
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#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
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#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
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#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
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#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
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#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
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#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
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#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
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#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
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#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
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#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
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#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
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#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
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#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
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#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
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#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
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#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
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#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
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#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
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#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
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#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
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#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
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#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
|
||||
|
||||
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
6
ports/mimxrt/boards/SEEED_ARCH_MIX/deploy.md
Normal file
6
ports/mimxrt/boards/SEEED_ARCH_MIX/deploy.md
Normal file
@ -0,0 +1,6 @@
|
||||
Firmware upload to the Seed ARCH MIX board can be done using the J-Link interface
|
||||
For that, follow the instructions given by Seed in their Wiki at
|
||||
https://wiki.seeedstudio.com/Arch_Mix/#flashing-arduino-bootloader-to-arch-mix.
|
||||
You will need a J-Link debug probe and software. What has been tested was the
|
||||
Segger JLlink edu or Segger JLink edu mini. As matching loader tool you can use
|
||||
Segger JFlashLite. The target address for loading is 0x60000000.
|
||||
142
ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h
Normal file
142
ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h
Normal file
@ -0,0 +1,142 @@
|
||||
#define MICROPY_HW_BOARD_NAME "Seeed ARCH MIX"
|
||||
#define MICROPY_HW_MCU_NAME "MIMXRT1052DVL5B"
|
||||
|
||||
// MIMXRT1050_EVKB has 1 user LED
|
||||
#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_B0_09)
|
||||
#define MICROPY_HW_LED2_PIN (pin_GPIO_AD_B0_10)
|
||||
#define MICROPY_HW_LED3_PIN (pin_GPIO_AD_B0_11)
|
||||
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
|
||||
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
|
||||
|
||||
#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
|
||||
|
||||
// Define mapping logical UART # to hardware UART #
|
||||
// LPUART1 on J3_19/J3_20 -> 1
|
||||
// LPUART2 on J4_16/J4_17 -> 2
|
||||
// LPUART3 on J4_06/J4_07 -> 3
|
||||
// LPUART8 on J4_10/J4_11 -> 4
|
||||
// LPUART4 on J5_08/J5_12 -> 5
|
||||
|
||||
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
|
||||
#define MICROPY_HW_UART_INDEX { 0, 1, 2, 3, 8, 4 }
|
||||
|
||||
#define IOMUX_TABLE_UART \
|
||||
{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
|
||||
{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
|
||||
{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
|
||||
{ IOMUXC_GPIO_B1_00_LPUART4_TX }, { IOMUXC_GPIO_B1_01_LPUART4_RX }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
|
||||
|
||||
#define MICROPY_HW_SPI_INDEX { 3, 4 }
|
||||
|
||||
#define IOMUX_TABLE_SPI \
|
||||
{ 0 }, { 0 }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK }, { IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 }, \
|
||||
{ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO }, { IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI }, \
|
||||
{ IOMUXC_GPIO_B1_07_LPSPI4_SCK }, { IOMUXC_GPIO_B1_04_LPSPI4_PCS0 }, \
|
||||
{ IOMUXC_GPIO_B1_06_LPSPI4_SDO }, { IOMUXC_GPIO_B1_05_LPSPI4_SDI },
|
||||
|
||||
#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
|
||||
kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
|
||||
|
||||
#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
|
||||
kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
|
||||
|
||||
// Define the mapping hardware I2C # to logical I2C #
|
||||
// SDA/SCL HW-I2C Logical I2C
|
||||
// J3_17/J3_16 LPI2C1 -> 0
|
||||
// J4_06/J4_07 LPI2C3 -> 1
|
||||
// J5_05/J5_04 LPI2C2 -> 2
|
||||
|
||||
#define MICROPY_HW_I2C_INDEX { 1, 3, 2 }
|
||||
|
||||
#define IOMUX_TABLE_I2C \
|
||||
{ IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA }, \
|
||||
{ IOMUXC_GPIO_B0_04_LPI2C2_SCL }, { IOMUXC_GPIO_B0_05_LPI2C2_SDA }, \
|
||||
{ IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA }
|
||||
|
||||
#define USDHC_DUMMY_PIN NULL, 0
|
||||
|
||||
#define MICROPY_USDHC1 \
|
||||
{ \
|
||||
.cmd = {GPIO_SD_B0_00_USDHC1_CMD}, \
|
||||
.clk = { GPIO_SD_B0_01_USDHC1_CLK }, \
|
||||
.cd_b = { GPIO_B1_12_USDHC1_CD_B }, \
|
||||
.data0 = { GPIO_SD_B0_02_USDHC1_DATA0 }, \
|
||||
.data1 = { GPIO_SD_B0_03_USDHC1_DATA1 }, \
|
||||
.data2 = { GPIO_SD_B0_04_USDHC1_DATA2 }, \
|
||||
.data3 = { GPIO_SD_B0_05_USDHC1_DATA3 }, \
|
||||
}
|
||||
|
||||
// Network definitions
|
||||
// Transceiver Phy Address & Type
|
||||
#define ENET_PHY_ADDRESS (1)
|
||||
#define ENET_PHY LAN8720
|
||||
#define ENET_PHY_OPS phylan8720_ops
|
||||
#define ENET_TX_CLK_OUTPUT false
|
||||
|
||||
// Etherner PIN definitions
|
||||
// No reset and interrupt pin by intention
|
||||
|
||||
#define IOMUX_TABLE_ENET \
|
||||
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
|
||||
{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
|
||||
{ IOMUXC_GPIO_B1_06_ENET_RX_EN, 0, 0xB0E9u }, \
|
||||
{ IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0, 0xB0E9u }, \
|
||||
{ IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0, 0xB0E9u }, \
|
||||
{ IOMUXC_GPIO_B1_09_ENET_TX_EN, 0, 0xB0E9u }, \
|
||||
{ IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1, 0x71u }, \
|
||||
{ IOMUXC_GPIO_B1_11_ENET_RX_ER, 0, 0x30E9u }, \
|
||||
{ IOMUXC_GPIO_EMC_41_ENET_MDIO, 0, 0xB0E9u }, \
|
||||
{ IOMUXC_GPIO_EMC_40_ENET_MDC, 0, 0xB0E9u },
|
||||
|
||||
// --- SEMC --- //
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
|
||||
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_11_SEMC_ADDR02
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_12_SEMC_ADDR03
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_13_SEMC_ADDR04
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_14_SEMC_ADDR05
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_15_SEMC_ADDR06
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_16_SEMC_ADDR07
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_17_SEMC_ADDR08
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_18_SEMC_ADDR09
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_23_SEMC_ADDR10
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_19_SEMC_ADDR11
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_20_SEMC_ADDR12
|
||||
|
||||
#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_21_SEMC_BA0
|
||||
#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_22_SEMC_BA1
|
||||
#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_24_SEMC_CAS
|
||||
#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_27_SEMC_CKE
|
||||
#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_26_SEMC_CLK
|
||||
#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_08_SEMC_DM00
|
||||
#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_38_SEMC_DM01
|
||||
#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_39_SEMC_DQS
|
||||
#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_25_SEMC_RAS
|
||||
#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_28_SEMC_WE
|
||||
|
||||
#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_29_SEMC_CS0
|
||||
14
ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk
Normal file
14
ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk
Normal file
@ -0,0 +1,14 @@
|
||||
MCU_SERIES = MIMXRT1052
|
||||
MCU_VARIANT = MIMXRT1052DVL6B
|
||||
|
||||
MICROPY_FLOAT_IMPL = double
|
||||
MICROPY_PY_MACHINE_SDCARD = 1
|
||||
MICROPY_HW_FLASH_TYPE ?= qspi_nor
|
||||
MICROPY_HW_FLASH_SIZE ?= 0x800000 # 8MB
|
||||
|
||||
MICROPY_HW_SDRAM_AVAIL = 1
|
||||
MICROPY_HW_SDRAM_SIZE = 0x2000000 # 32MB
|
||||
|
||||
MICROPY_PY_LWIP = 1
|
||||
MICROPY_PY_USSL = 1
|
||||
MICROPY_SSL_MBEDTLS = 1
|
||||
62
ports/mimxrt/boards/SEEED_ARCH_MIX/pins.csv
Normal file
62
ports/mimxrt/boards/SEEED_ARCH_MIX/pins.csv
Normal file
@ -0,0 +1,62 @@
|
||||
J3_04,GPIO_B1_11
|
||||
J3_05,GPIO_B1_06
|
||||
J3_06,GPIO_EMC_41
|
||||
J3_07,GPIO_EMC_40
|
||||
J3_08,GPIO_B1_05
|
||||
J3_09,GPIO_B1_04
|
||||
J3_10,GPIO_B1_08
|
||||
J3_11,GPIO_B1_07
|
||||
J3_12,GPIO_B1_09
|
||||
J3_13,GPIO_B1_10
|
||||
J3_14,GPIO_AD_B0_14
|
||||
J3_15,GPO_AD_B0_15
|
||||
J3_16,GPIO_AD_B1_00
|
||||
J3_17,GPIO_AD_B1_01
|
||||
J3_19,GPIO_AD_B0_13
|
||||
J3_20,GPIO_AD_B0_12
|
||||
J4_04,GPIO_AD_B1_04
|
||||
J4_05,GPIO_AD_B1_05
|
||||
J4_06,GPIO_AD_B1_06
|
||||
J4_07,GPIO_AD_B1_07
|
||||
J4_08,GPIO_AD_B1_08
|
||||
J4_09,GPIO_AD_B1_09
|
||||
J4_10,GPIO_AD_B1_10
|
||||
J4_11,GPIO_AD_B1_11
|
||||
J4_12,GPIO_AD_B1_12
|
||||
J4_13,GPIO_AD_B1_13
|
||||
J4_14,GPIO_AD_B1_14
|
||||
J4_15,GPIO_AD_B1_15
|
||||
J4_16,GPIO_AD_B1_02
|
||||
J4_17,GPIO_AD_B1_03
|
||||
J4_19,GPIO_AD_B0_07
|
||||
J4_20,GPIO_AD_B0_06
|
||||
J5_32,GPIO_B0_00
|
||||
J5_28,GPIO_B0_01
|
||||
J5_29,GPIO_B0_02
|
||||
J5_30,GPIO_B0_03
|
||||
J5_04,GPIO_B0_04
|
||||
J5_05,GPIO_B0_05
|
||||
J5_06,GPIO_B0_06
|
||||
J5_07,GPIO_B0_07
|
||||
J5_08,GPIO_B0_08
|
||||
J5_12,GPIO_B0_09
|
||||
J5_13,GPIO_B0_10
|
||||
J5_14,GPIO_B0_11
|
||||
J5_15,GPIO_B0_12
|
||||
J5_16,GPIO_B0_13
|
||||
J5_17,GPIO_B0_14
|
||||
J5_22,GPIO_B0_15
|
||||
J5_23,GPIO_B1_00
|
||||
J5_24,GPIO_B1_01
|
||||
J5_25,GPIO_B1_02
|
||||
J5_26,GPIO_B1_03
|
||||
J5_34,GPIO_AD_B1_15
|
||||
J5_35,GPIO_AD_B1_14
|
||||
J5_36,GPIO_AD_B1_13
|
||||
J5_37,GPIO_AD_B1_12
|
||||
J5_42,GPIO_AD_B1_00
|
||||
J5_43,GPIO_AD_B1_01
|
||||
J5_50,GPIO_AD_B0_02
|
||||
LED_RED,GPIO_AD_B0_09
|
||||
LED_GREEN,GPIO_AD_B0_10
|
||||
LED_BLUE,GPIO_AD_B0_11
|
||||
|
136
ports/mimxrt/boards/SEEED_ARCH_MIX/qspi_nor_flash_config.c
Normal file
136
ports/mimxrt/boards/SEEED_ARCH_MIX/qspi_nor_flash_config.c
Normal file
@ -0,0 +1,136 @@
|
||||
/*
|
||||
* Copyright 2019 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Based on tinyusb/hw/bsp/teensy_40/evkmimxrt1010_flexspi_nor_config.c
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.busyOffset = FLASH_BUSY_STATUS_OFFSET, // Status bit 0 indicates busy.
|
||||
.busyBitPolarity = FLASH_BUSY_STATUS_POL, // Busy when the bit is 1.
|
||||
.deviceModeCfgEnable = 1u,
|
||||
.deviceModeType = kDeviceConfigCmdType_QuadEnable,
|
||||
.deviceModeSeq = {
|
||||
.seqId = 4u,
|
||||
.seqNum = 1u,
|
||||
},
|
||||
.deviceModeArg = 0x40,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_100MHz,
|
||||
.sflashA1Size = BOARD_FLASH_SIZE,
|
||||
.lookupTable =
|
||||
{
|
||||
// 0 Read LUTs 0 -> 0
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 1 Read status register -> 1
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 2 Fast read quad mode - SDR
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 3 Write Enable -> 3
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 4 Read extend parameters
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 5 Erase Sector -> 5
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 6 Write Status Reg
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 7 Page Program - quad mode (-> 9)
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 8 Read ID
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x90, DUMMY_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x00, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 9 Page Program - single mode -> 9
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 10 Enter QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 11 Erase Chip
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 12 Exit QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_4PAD, 0xF5, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
// .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
Loading…
Reference in New Issue
Block a user