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nrf5/pin: Merging input and output pin configuration to one comon function. Adding implementation in Pin class to be able to configure mode and pull. Updating drivers which uses gpio pin configuration to use new function parameters.

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This commit is contained in:
Glenn Ruben Bakke 2016-12-27 15:40:20 +01:00
parent 4fee95c468
commit d6300a2e82
8 changed files with 43 additions and 46 deletions
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8
nrf5/hal/hal_spi.c
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@ -48,10 +48,10 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi
hal_gpio_pin_set(p_spi_init->enable_pin); hal_gpio_pin_set(p_spi_init->enable_pin);
m_ss_pin = p_spi_init->enable_pin; m_ss_pin = p_spi_init->enable_pin;
hal_gpio_cfg_pin_output(p_spi_init->clk_pin); hal_gpio_cfg_pin(p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_output(p_spi_init->mosi_pin); hal_gpio_cfg_pin(p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_input(p_spi_init->miso_pin, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_output(p_spi_init->enable_pin); hal_gpio_cfg_pin(p_spi_init->enable_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
#if NRF51 #if NRF51
p_instance->PSELSCK = p_spi_init->clk_pin; p_instance->PSELSCK = p_spi_init->clk_pin;

8
nrf5/hal/hal_spie.c
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@ -64,10 +64,10 @@ void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi
hal_gpio_pin_set(p_spi_init->enable_pin); hal_gpio_pin_set(p_spi_init->enable_pin);
m_ss_pin = p_spi_init->enable_pin; m_ss_pin = p_spi_init->enable_pin;
hal_gpio_cfg_pin_output(p_spi_init->clk_pin); hal_gpio_cfg_pin(p_spi_init->clk_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_output(p_spi_init->mosi_pin); hal_gpio_cfg_pin(p_spi_init->mosi_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_input(p_spi_init->miso_pin, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_spi_init->miso_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_output(p_spi_init->enable_pin); hal_gpio_cfg_pin(p_spi_init->enable_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
#if NRF51 #if NRF51
spim_instance->PSELSCK = p_spi_init->clk_pin; spim_instance->PSELSCK = p_spi_init->clk_pin;

8
nrf5/hal/hal_uart.c
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@ -103,15 +103,15 @@ void nrf_uart_buffer_read(uint8_t * p_buffer, uint32_t num_of_bytes, uart_comple
} }
void nrf_uart_init(hal_uart_init_t const * p_uart_init) { void nrf_uart_init(hal_uart_init_t const * p_uart_init) {
hal_gpio_cfg_pin_output(p_uart_init->tx_pin); hal_gpio_cfg_pin(p_uart_init->tx_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_input(p_uart_init->rx_pin, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->rx_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
UART_BASE->PSELTXD = p_uart_init->tx_pin; UART_BASE->PSELTXD = p_uart_init->tx_pin;
UART_BASE->PSELRXD = p_uart_init->rx_pin; UART_BASE->PSELRXD = p_uart_init->rx_pin;
if (p_uart_init->flow_control) { if (p_uart_init->flow_control) {
hal_gpio_cfg_pin_output(p_uart_init->rts_pin); hal_gpio_cfg_pin(p_uart_init->rts_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_input(p_uart_init->cts_pin, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->cts_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
UART_BASE->PSELCTS = p_uart_init->cts_pin; UART_BASE->PSELCTS = p_uart_init->cts_pin;
UART_BASE->PSELRTS = p_uart_init->rts_pin; UART_BASE->PSELRTS = p_uart_init->rts_pin;

8
nrf5/hal/hal_uarte.c
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@ -84,9 +84,9 @@ void nrf_sendchar(int ch) {
} }
void nrf_uart_init(hal_uart_init_t const * p_uart_init) { void nrf_uart_init(hal_uart_init_t const * p_uart_init) {
hal_gpio_cfg_pin_output(p_uart_init->tx_pin); hal_gpio_cfg_pin(p_uart_init->tx_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_pin_set(p_uart_init->tx_pin); hal_gpio_pin_set(p_uart_init->tx_pin);
hal_gpio_cfg_pin_input(p_uart_init->rx_pin, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->rx_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
UARTE_BASE->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]); UARTE_BASE->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]);
@ -104,8 +104,8 @@ void nrf_uart_init(hal_uart_init_t const * p_uart_init) {
UARTE_BASE->PSEL.TXD = p_uart_init->tx_pin; UARTE_BASE->PSEL.TXD = p_uart_init->tx_pin;
if (hwfc) { if (hwfc) {
hal_gpio_cfg_pin_input(p_uart_init->cts_pin, HAL_GPIO_PULL_DISABLED); hal_gpio_cfg_pin(p_uart_init->cts_pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin_output(p_uart_init->rts_pin); hal_gpio_cfg_pin(p_uart_init->rts_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_pin_set(p_uart_init->rts_pin); hal_gpio_pin_set(p_uart_init->rts_pin);
UARTE_BASE->PSEL.RTS = p_uart_init->rts_pin; UARTE_BASE->PSEL.RTS = p_uart_init->rts_pin;

2
nrf5/led.c
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@ -63,7 +63,7 @@ STATIC const pyb_led_obj_t pyb_led_obj[] = {
void led_init(void) { void led_init(void) {
for (uint8_t i = 0; i < NUM_LEDS; i++) { for (uint8_t i = 0; i < NUM_LEDS; i++) {
LED_OFF(pyb_led_obj[i].hw_pin); LED_OFF(pyb_led_obj[i].hw_pin);
hal_gpio_cfg_pin_output(pyb_led_obj[i].hw_pin); hal_gpio_cfg_pin(pyb_led_obj[i].hw_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
} }
} }

20
nrf5/mphalport.h
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@ -73,23 +73,19 @@ typedef enum {
HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos)
} hal_gpio_pull_t; } hal_gpio_pull_t;
static inline void hal_gpio_cfg_pin_output(uint32_t pin_number) { typedef enum {
HAL_GPIO_MODE_OUTPUT = (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos),
HAL_GPIO_MODE_INPUT = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos),
} hal_gpio_mode_t;
static inline void hal_gpio_cfg_pin(uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) {
GPIO_BASE->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) GPIO_BASE->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | pull
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); | mode;
} }
static inline void hal_gpio_cfg_pin_input(uint32_t pin_number, hal_gpio_pull_t pull) {
GPIO_BASE->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| pull
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
}
static inline void hal_gpio_out_set(uint32_t pin_mask) { static inline void hal_gpio_out_set(uint32_t pin_mask) {
GPIO_BASE->OUTSET = pin_mask; GPIO_BASE->OUTSET = pin_mask;
} }

34
nrf5/pin.c
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@ -215,7 +215,6 @@ STATIC void pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t
} }
} }
mp_print_str(print, qstr_str(mode_qst)); mp_print_str(print, qstr_str(mode_qst));
// pull mode // pull mode
qstr pull_qst = MP_QSTR_NULL; qstr pull_qst = MP_QSTR_NULL;
uint32_t pull = pin_get_pull(self); uint32_t pull = pin_get_pull(self);
@ -227,7 +226,6 @@ STATIC void pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t
if (pull_qst != MP_QSTR_NULL) { if (pull_qst != MP_QSTR_NULL) {
mp_printf(print, ", pull=Pin.%q", pull_qst); mp_printf(print, ", pull=Pin.%q", pull_qst);
} }
// AF mode // AF mode
if (af) { if (af) {
mp_uint_t af_idx = pin_get_af(self); mp_uint_t af_idx = pin_get_af(self);
@ -343,27 +341,25 @@ STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, con
// parse args // parse args
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
/*
// get io mode
uint mode = args[0].u_int;
if (!IS_GPIO_MODE(mode)) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "invalid pin mode: %d", mode));
}
*/
// get pull mode // get pull mode
uint pull = HAL_GPIO_PULL_DISABLED; uint pull = HAL_GPIO_PULL_DISABLED;
if (args[1].u_obj != mp_const_none) { if (args[1].u_obj != mp_const_none) {
pull = mp_obj_get_int(args[1].u_obj); pull = mp_obj_get_int(args[1].u_obj);
} }
(void)pull;
// if given, set the pin value before initialising to prevent glitches // if given, set the pin value before initialising to prevent glitches
if (args[3].u_obj != MP_OBJ_NULL) { if (args[3].u_obj != MP_OBJ_NULL) {
mp_hal_pin_write(self, mp_obj_is_true(args[3].u_obj)); mp_hal_pin_write(self, mp_obj_is_true(args[3].u_obj));
} }
hal_gpio_cfg_pin_output(self->pin_mask); // get io mode
uint mode = args[0].u_int;
if (mode == HAL_GPIO_MODE_OUTPUT || mode == HAL_GPIO_MODE_INPUT) {
hal_gpio_cfg_pin(self->pin, mode, pull);
} else {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "invalid pin mode: %d", mode));
}
return mp_const_none; return mp_const_none;
} }
@ -501,21 +497,25 @@ STATIC const mp_map_elem_t pin_locals_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_mapper), (mp_obj_t)&pin_mapper_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_mapper), (mp_obj_t)&pin_mapper_obj },
{ MP_OBJ_NEW_QSTR(MP_QSTR_dict), (mp_obj_t)&pin_map_dict_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_dict), (mp_obj_t)&pin_map_dict_obj },
{ MP_OBJ_NEW_QSTR(MP_QSTR_debug), (mp_obj_t)&pin_debug_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_debug), (mp_obj_t)&pin_debug_obj },
/*
// class attributes // class attributes
{ MP_OBJ_NEW_QSTR(MP_QSTR_board), (mp_obj_t)&pin_board_pins_obj_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_board), (mp_obj_t)&pin_board_pins_obj_type },
{ MP_OBJ_NEW_QSTR(MP_QSTR_cpu), (mp_obj_t)&pin_cpu_pins_obj_type }, { MP_OBJ_NEW_QSTR(MP_QSTR_cpu), (mp_obj_t)&pin_cpu_pins_obj_type },
// class constants // class constants
{ MP_OBJ_NEW_QSTR(MP_QSTR_IN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_INPUT) }, { MP_OBJ_NEW_QSTR(MP_QSTR_IN), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_MODE_INPUT) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_OUT), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, { MP_OBJ_NEW_QSTR(MP_QSTR_OUT), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_MODE_OUTPUT) },
/*
{ MP_OBJ_NEW_QSTR(MP_QSTR_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_ALT), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_PP) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ALT), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_PP) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_OD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_OD) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_ANALOG), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_ANALOG) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ANALOG), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_ANALOG) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_PULL_UP), MP_OBJ_NEW_SMALL_INT(GPIO_PULLUP) }, */
{ MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DOWN), MP_OBJ_NEW_SMALL_INT(GPIO_PULLDOWN) }, { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DISABLED), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_DISABLED) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_PULL_UP), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_UP) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DOWN), MP_OBJ_NEW_SMALL_INT(HAL_GPIO_PULL_DOWN) },
/*
// legacy class constants // legacy class constants
{ MP_OBJ_NEW_QSTR(MP_QSTR_OUT_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) }, { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_PP), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_PP) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_OUT_OD), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) }, { MP_OBJ_NEW_QSTR(MP_QSTR_OUT_OD), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_OUTPUT_OD) },

1
nrf5/pin.h
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@ -59,6 +59,7 @@ typedef struct {
uint32_t pin_mask; uint32_t pin_mask;
pin_gpio_t *gpio; pin_gpio_t *gpio;
const pin_af_obj_t *af; const pin_af_obj_t *af;
uint32_t pull;
} pin_obj_t; } pin_obj_t;
extern const mp_obj_type_t pin_type; extern const mp_obj_type_t pin_type;