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atmel-samd working

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This commit is contained in:
Dan Halbert 2019-12-06 15:18:20 -05:00
parent a0721fc94a
commit d628d2a261
7 changed files with 349 additions and 23 deletions
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260
ports/atmel-samd/bindings/samd/Clock.c
View File

@ -163,3 +163,263 @@ const mp_obj_type_t samd_clock_type = {
.print = samd_clock_print,
.locals_dict = (mp_obj_t)&samd_clock_locals_dict,
};
#ifdef SAMD21
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
CLOCK_SOURCE(XOSC);
CLOCK_SOURCE(GCLKIN);
CLOCK_SOURCE(GCLKGEN1);
CLOCK_SOURCE(OSCULP32K);
#endif
CLOCK_SOURCE(OSC32K);
CLOCK_SOURCE(XOSC32K);
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
CLOCK_SOURCE(OSC8M);
CLOCK_SOURCE(DFLL48M);
CLOCK_SOURCE(DPLL96M);
CLOCK_GCLK_(SYSCTRL, DFLL48);
CLOCK_GCLK_(SYSCTRL, FDPLL);
CLOCK_GCLK_(SYSCTRL, FDPLL32K);
CLOCK_GCLK(WDT);
#endif
CLOCK_GCLK(RTC);
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
CLOCK_GCLK(EIC);
CLOCK_GCLK(USB);
CLOCK_GCLK_(EVSYS, 0);
CLOCK_GCLK_(EVSYS, 1);
CLOCK_GCLK_(EVSYS, 2);
CLOCK_GCLK_(EVSYS, 3);
CLOCK_GCLK_(EVSYS, 4);
CLOCK_GCLK_(EVSYS, 5);
CLOCK_GCLK_(EVSYS, 6);
CLOCK_GCLK_(EVSYS, 7);
CLOCK_GCLK_(EVSYS, 8);
CLOCK_GCLK_(EVSYS, 9);
CLOCK_GCLK_(EVSYS, 10);
CLOCK_GCLK_(EVSYS, 11);
CLOCK(SERCOMx_SLOW, 1, 19);
CLOCK_GCLK_(SERCOM0, CORE);
CLOCK_GCLK_(SERCOM1, CORE);
CLOCK_GCLK_(SERCOM2, CORE);
CLOCK_GCLK_(SERCOM3, CORE);
CLOCK_GCLK_(SERCOM4, CORE);
CLOCK_GCLK_(SERCOM5, CORE);
CLOCK(TCC0_TCC1, 1, 26);
CLOCK(TCC2_TCC3, 1, 27);
CLOCK(TC4_TC5, 1, 28);
CLOCK(TC6_TC7, 1, 29);
CLOCK_GCLK(ADC);
CLOCK_GCLK_(AC, DIG);
CLOCK_GCLK_(AC, ANA);
CLOCK_GCLK(DAC);
CLOCK_GCLK(PTC);
CLOCK_GCLK_(I2S, 0);
CLOCK_GCLK_(I2S, 1);
CLOCK(SYSTICK, 2, 0);
#endif
STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
CLOCK_ENTRY(XOSC),
CLOCK_ENTRY(GCLKIN),
CLOCK_ENTRY(GCLKGEN1),
CLOCK_ENTRY(OSCULP32K),
#endif
CLOCK_ENTRY(OSC32K),
CLOCK_ENTRY(XOSC32K),
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
CLOCK_ENTRY(OSC8M),
CLOCK_ENTRY(DFLL48M),
CLOCK_ENTRY(DPLL96M),
CLOCK_ENTRY_(SYSCTRL, DFLL48),
CLOCK_ENTRY_(SYSCTRL, FDPLL),
CLOCK_ENTRY_(SYSCTRL, FDPLL32K),
CLOCK_ENTRY(WDT),
#endif
CLOCK_ENTRY(RTC),
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
CLOCK_ENTRY(EIC),
CLOCK_ENTRY(USB),
CLOCK_ENTRY_(EVSYS, 0),
CLOCK_ENTRY_(EVSYS, 1),
CLOCK_ENTRY_(EVSYS, 2),
CLOCK_ENTRY_(EVSYS, 3),
CLOCK_ENTRY_(EVSYS, 4),
CLOCK_ENTRY_(EVSYS, 5),
CLOCK_ENTRY_(EVSYS, 6),
CLOCK_ENTRY_(EVSYS, 7),
CLOCK_ENTRY_(EVSYS, 8),
CLOCK_ENTRY_(EVSYS, 9),
CLOCK_ENTRY_(EVSYS, 10),
CLOCK_ENTRY_(EVSYS, 11),
CLOCK_ENTRY(SERCOMx_SLOW),
CLOCK_ENTRY_(SERCOM0, CORE),
CLOCK_ENTRY_(SERCOM1, CORE),
CLOCK_ENTRY_(SERCOM2, CORE),
CLOCK_ENTRY_(SERCOM3, CORE),
CLOCK_ENTRY_(SERCOM4, CORE),
CLOCK_ENTRY_(SERCOM5, CORE),
CLOCK_ENTRY(TCC0_TCC1),
CLOCK_ENTRY(TCC2_TCC3),
CLOCK_ENTRY(TC4_TC5),
CLOCK_ENTRY(TC6_TC7),
CLOCK_ENTRY(ADC),
CLOCK_ENTRY_(AC, DIG),
CLOCK_ENTRY_(AC, ANA),
CLOCK_ENTRY(DAC),
CLOCK_ENTRY(PTC),
CLOCK_ENTRY_(I2S, 0),
CLOCK_ENTRY_(I2S, 1),
CLOCK_ENTRY(SYSTICK),
#endif
};
MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
#endif // SAMD21
#ifdef SAMD51
#include <instance/can0.h>
#include <instance/can1.h>
#include <instance/i2s.h>
#include <instance/sdhc1.h>
#include <instance/sercom6.h>
#include <instance/sercom7.h>
#include <instance/tcc4.h>
CLOCK_SOURCE(XOSC0);
CLOCK_SOURCE(XOSC1);
CLOCK_SOURCE(GCLKIN);
CLOCK_SOURCE(GCLKGEN1);
CLOCK_SOURCE(OSCULP32K);
CLOCK_SOURCE(XOSC32K);
CLOCK_SOURCE(DFLL);
CLOCK_SOURCE(DPLL0);
CLOCK_SOURCE(DPLL1);
CLOCK_GCLK_(OSCCTRL, DFLL48);
CLOCK_GCLK_(OSCCTRL, FDPLL0);
CLOCK_GCLK_(OSCCTRL, FDPLL1);
CLOCK_GCLK_(OSCCTRL, FDPLL032K); // GCLK_OSCCTRL_FDPLL1_32K, GCLK_SDHC0_SLOW, GCLK_SDHC1_SLOW, GCLK_SERCOM[0..7]_SLOW
CLOCK_GCLK(EIC);
CLOCK_GCLK_(FREQM, MSR);
// 6: GCLK_FREQM_REF
CLOCK_GCLK_(SERCOM0, CORE);
CLOCK_GCLK_(SERCOM1, CORE);
CLOCK(TC0_TC1, 1, 9);
CLOCK_GCLK(USB);
CLOCK_GCLK_(EVSYS, 0);
CLOCK_GCLK_(EVSYS, 1);
CLOCK_GCLK_(EVSYS, 2);
CLOCK_GCLK_(EVSYS, 3);
CLOCK_GCLK_(EVSYS, 4);
CLOCK_GCLK_(EVSYS, 5);
CLOCK_GCLK_(EVSYS, 6);
CLOCK_GCLK_(EVSYS, 7);
CLOCK_GCLK_(EVSYS, 8);
CLOCK_GCLK_(EVSYS, 9);
CLOCK_GCLK_(EVSYS, 10);
CLOCK_GCLK_(EVSYS, 11);
CLOCK_GCLK_(SERCOM2, CORE);
CLOCK_GCLK_(SERCOM3, CORE);
CLOCK(TCC0_TCC1, 1, 25);
CLOCK(TC2_TC3, 1, 26);
CLOCK_GCLK(CAN0);
CLOCK_GCLK(CAN1);
CLOCK(TCC2_TCC3, 1, 29);
CLOCK(TC4_TC5, 1, 30);
// CLOCK_GCLK(PDEC);
// CLOCK_GCLK(AC);
// CLOCK_GCLK(CCL);
CLOCK_GCLK_(SERCOM4, CORE);
CLOCK_GCLK_(SERCOM5, CORE);
CLOCK_GCLK_(SERCOM6, CORE);
CLOCK_GCLK_(SERCOM7, CORE);
CLOCK_GCLK(TCC4);
CLOCK(TC6_TC7, 1, 39);
CLOCK_GCLK(ADC0);
CLOCK_GCLK(ADC1);
CLOCK_GCLK(DAC);
CLOCK_GCLK_(I2S, 0);
CLOCK_GCLK_(I2S, 1);
// CLOCK_GCLK(SDHC0);
// CLOCK_GCLK(SDHC1);
// 47: GCLK_CM4_TRACE
CLOCK(SYSTICK, 2, 0);
CLOCK(CPU, 2, 1);
CLOCK(RTC, 2, 2);
STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
CLOCK_ENTRY(XOSC0),
CLOCK_ENTRY(XOSC1),
CLOCK_ENTRY(GCLKIN),
CLOCK_ENTRY(GCLKGEN1),
CLOCK_ENTRY(OSCULP32K),
CLOCK_ENTRY(XOSC32K),
CLOCK_ENTRY(DFLL),
CLOCK_ENTRY(DPLL0),
CLOCK_ENTRY(DPLL1),
CLOCK_ENTRY_(OSCCTRL, DFLL48),
CLOCK_ENTRY_(OSCCTRL, FDPLL0),
CLOCK_ENTRY_(OSCCTRL, FDPLL1),
CLOCK_ENTRY_(OSCCTRL, FDPLL032K),
CLOCK_ENTRY(EIC),
CLOCK_ENTRY_(FREQM, MSR),
CLOCK_ENTRY_(SERCOM0, CORE),
CLOCK_ENTRY_(SERCOM1, CORE),
CLOCK_ENTRY(TC0_TC1),
CLOCK_ENTRY(USB),
CLOCK_ENTRY_(EVSYS, 0),
CLOCK_ENTRY_(EVSYS, 1),
CLOCK_ENTRY_(EVSYS, 2),
CLOCK_ENTRY_(EVSYS, 3),
CLOCK_ENTRY_(EVSYS, 4),
CLOCK_ENTRY_(EVSYS, 5),
CLOCK_ENTRY_(EVSYS, 6),
CLOCK_ENTRY_(EVSYS, 7),
CLOCK_ENTRY_(EVSYS, 8),
CLOCK_ENTRY_(EVSYS, 9),
CLOCK_ENTRY_(EVSYS, 10),
CLOCK_ENTRY_(EVSYS, 11),
CLOCK_ENTRY_(SERCOM2, CORE),
CLOCK_ENTRY_(SERCOM3, CORE),
CLOCK_ENTRY(TCC0_TCC1),
CLOCK_ENTRY(TC2_TC3),
CLOCK_ENTRY(CAN0),
CLOCK_ENTRY(CAN1),
CLOCK_ENTRY(TCC2_TCC3),
CLOCK_ENTRY(TC4_TC5),
// CLOCK_ENTRY(PDEC),
// CLOCK_ENTRY(AC),
// CLOCK_ENTRY(CCL),
CLOCK_ENTRY_(SERCOM4, CORE),
CLOCK_ENTRY_(SERCOM5, CORE),
CLOCK_ENTRY_(SERCOM6, CORE),
CLOCK_ENTRY_(SERCOM7, CORE),
CLOCK_ENTRY(TCC4),
CLOCK_ENTRY(TC6_TC7),
CLOCK_ENTRY(ADC0),
CLOCK_ENTRY(ADC1),
CLOCK_ENTRY(DAC),
CLOCK_ENTRY_(I2S, 0),
CLOCK_ENTRY_(I2S, 1),
// CLOCK_ENTRY(SDHC0),
// CLOCK_ENTRY(SDHC1),
CLOCK_ENTRY(SYSTICK),
CLOCK_ENTRY(CPU),
CLOCK_ENTRY(RTC),
};
MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
#endif // SAMD51

2
ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c
View File

@ -213,7 +213,7 @@ void frequencyin_samd51_start_dpll() {
// Will also enable the Lock Bypass due to low-frequency sources causing DPLL unlocks
// as outlined in the Errata (1.12.1)
OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(2999);
if (board_has_crystal()) { // we can use XOSC32K directly as the source
if (BOARD_HAS_CRYSTAL) { // we can use XOSC32K directly as the source
OSC32KCTRL->XOSC32K.bit.EN32K = 1;
OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(1) |
OSCCTRL_DPLLCTRLB_LBYPASS;

48
ports/atmel-samd/mpconfigport.h
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@ -30,28 +30,16 @@
// Definitions for which SAMD chip we're using.
#include "include/sam.h"
////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef SAMD21
#if INTERNAL_FLASH_FILESYSTEM
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (64*1024)
#else
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0)
#endif
#ifndef CALIBRATE_CRYSTALLESS
#define CALIBRATE_CRYSTALLESS (0)
#endif
// if CALIBRATE_CRYSTALLESS is requested, make room for storing
// calibration data generated from external USB.
#ifndef CIRCUITPY_INTERNAL_CONFIG_SIZE
#if CALIBRATE_CRYSTALLESS
#define CIRCUITPY_INTERNAL_CONFIG_SIZE (256)
#else
#define CIRCUITPY_INTERNAL_CONFIG_SIZE (0)
#endif
#endif
#ifdef SAMD21
// HMCRAMC0_SIZE is defined in the ASF4 include files for each SAMD21 chip.
#define RAM_SIZE HMCRAMC0_SIZE
#define BOOTLOADER_SIZE (8*1024)
@ -84,6 +72,8 @@
#endif // SAMD21
////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef SAMD51
#ifndef CIRCUITPY_INTERNAL_NVM_SIZE
@ -110,6 +100,7 @@
#define MICROPY_PY_BUILTINS_NOTIMPLEMENTED (1)
#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1)
#define MICROPY_PY_FUNCTION_ATTRS (1)
// MICROPY_PY_UJSON depends on MICROPY_PY_IO
#define MICROPY_PY_IO (1)
#define MICROPY_PY_UJSON (1)
#define MICROPY_PY_REVERSE_SPECIAL_METHODS (1)
@ -117,6 +108,29 @@
#endif // SAMD51
////////////////////////////////////////////////////////////////////////////////////////////////////
// This also includes mpconfigboard.h.
#include "py/circuitpy_mpconfig.h"
#ifndef CALIBRATE_CRYSTALLESS
#define CALIBRATE_CRYSTALLESS (0)
#endif
#ifndef BOARD_HAS_CRYSTAL
#define BOARD_HAS_CRYSTAL (0)
#endif
// if CALIBRATE_CRYSTALLESS is requested, make room for storing
// calibration data generated from external USB.
#ifndef CIRCUITPY_INTERNAL_CONFIG_SIZE
#if CALIBRATE_CRYSTALLESS
#define CIRCUITPY_INTERNAL_CONFIG_SIZE (NVMCTRL_ROW_SIZE) // 256
#else
#define CIRCUITPY_INTERNAL_CONFIG_SIZE (0)
#endif
#endif
// Flash layout, starting at 0x00000000
//
// bootloader (8 or 16kB)
@ -155,8 +169,6 @@
#include "peripherals/samd/dma.h"
#include "py/circuitpy_mpconfig.h"
#define MICROPY_PORT_ROOT_POINTERS \
CIRCUITPY_COMMON_ROOT_POINTERS \
mp_obj_t playing_audio[AUDIO_DMA_CHANNEL_COUNT];

2
ports/atmel-samd/peripherals

@ -1 +1 @@
Subproject commit 2ba5b20ba725e1c91c77875fba3a5e22059cdb92
Subproject commit bb26a4145c86a51debc6571bb1f791e0d4fd296b

54
ports/atmel-samd/supervisor/port.c
View File

@ -24,12 +24,16 @@
* THE SOFTWARE.
*/
#include <string.h>
#include <stdlib.h>
#include "boards/board.h"
#include "supervisor/port.h"
// ASF 4
#include "atmel_start_pins.h"
#include "hal/include/hal_delay.h"
#include "hal/include/hal_flash.h"
#include "hal/include/hal_gpio.h"
#include "hal/include/hal_init.h"
#include "hpl/gclk/hpl_gclk_base.h"
@ -94,6 +98,40 @@ extern volatile bool mp_msc_enabled;
__attribute__((__aligned__(TRACE_BUFFER_SIZE_BYTES))) uint32_t mtb[TRACE_BUFFER_SIZE] = {0};
#endif
#if CALIBRATE_CRYSTALLESS
static void save_usb_clock_calibration(void) {
// If we are on USB lets double check our fine calibration for the clock and
// save the new value if its different enough.
SYSCTRL->DFLLSYNC.bit.READREQ = 1;
uint16_t saved_calibration = 0x1ff;
if (strcmp((char*) CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) {
saved_calibration = ((uint16_t *) CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8];
}
while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
// TODO(tannewt): Run the mass storage stuff if this takes a while.
}
int16_t current_calibration = SYSCTRL->DFLLVAL.bit.FINE;
if (abs(current_calibration - saved_calibration) > 10) {
// Copy the full internal config page to memory.
uint8_t page_buffer[NVMCTRL_ROW_SIZE];
memcpy(page_buffer, (uint8_t*) CIRCUITPY_INTERNAL_CONFIG_START_ADDR, NVMCTRL_ROW_SIZE);
// Modify it.
memcpy(page_buffer, "CIRCUITPYTHON1", 15);
// First 16 bytes (0-15) are ID. Little endian!
page_buffer[16] = current_calibration & 0xff;
page_buffer[17] = current_calibration >> 8;
// Write it back.
// We don't use features that use any advanced NVMCTRL features so we can fake the descriptor
// whenever we need it instead of storing it long term.
struct flash_descriptor desc;
desc.dev.hw = NVMCTRL;
flash_write(&desc, (uint32_t) CIRCUITPY_INTERNAL_CONFIG_START_ADDR, page_buffer, NVMCTRL_ROW_SIZE);
}
}
#endif
safe_mode_t port_init(void) {
#if defined(SAMD21)
@ -168,7 +206,19 @@ safe_mode_t port_init(void) {
hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
_pm_init();
#endif
clock_init();
#if CALIBRATE_CRYSTALLESS
uint32_t fine = DEFAULT_DFLL48M_FINE_CALIBRATION;
// The fine calibration data is stored in an NVM page after the text and data storage but before
// the optional file system. The first 16 bytes are the identifier for the section.
if (strcmp((char*) CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) {
fine = ((uint16_t *) CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8];
}
clock_init(BOARD_HAS_CRYSTAL, fine);
#else
// Use a default fine value
clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION);
#endif
// Configure millisecond timer initialization.
tick_init();
@ -257,9 +307,11 @@ void reset_port(void) {
// gpio_set_pin_function(PIN_PB15, GPIO_PIN_FUNCTION_M); // GCLK1, D6
// #endif
#if CALIBRATE_CRYSTALLESS
if (tud_cdc_connected()) {
save_usb_clock_calibration();
}
#endif
}
void reset_to_bootloader(void) {

3
py/circuitpy_mpconfig.h
View File

@ -174,7 +174,8 @@ typedef long mp_off_t;
{ MP_OBJ_NEW_QSTR(MP_QSTR_input), (mp_obj_t)&mp_builtin_input_obj }, \
{ MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj },
// board specific definitions
//////////////////////////////////////////////////////////////////////////////////////////////////
// board-specific definitions, which control and may override definitions below.
#include "mpconfigboard.h"
// CIRCUITPY_FULL_BUILD is defined in a *.mk file.

3
tools/build_memory_info.py
View File

@ -41,6 +41,7 @@ data = 0
bss = 0
# stdin is the linker output.
for line in sys.stdin:
print(line)
line = line.strip()
if not line.startswith("text"):
text, data, bss = map(int, line.split()[:3])
@ -64,7 +65,7 @@ for region in regions:
free_flash = regions["FLASH_FIRMWARE"] - text - data
free_ram = regions["RAM"] - data - bss
print("{} bytes free in flash firmware space out of {} bytes ({}kB).".format(free_flash, regions["FLASH_FIRMWARE"], regions["FLASH_FIRMWARE"] / 1024))
print("{} bytes free in ram for stack out of {} bytes ({}kB).".format(free_ram, regions["RAM"], regions["RAM"] / 1024))
print("{} bytes free in ram for heap out of {} bytes ({}kB).".format(free_ram, regions["RAM"], regions["RAM"] / 1024))
print()
# Check that we have free flash space. GCC doesn't fail when the text + data