Merge pull request #785 from notro/rtc_calibration
atmel-samd/samd21: Rework clock setup + calibration
This commit is contained in:
Scott Shawcroft
GitHub
commit
d3a5d40374
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@ -225,6 +225,7 @@ SRC_C = \
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audio_dma.c \
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audio_dma.c \
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background.c \
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background.c \
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clocks.c \
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clocks.c \
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$(CHIP_FAMILY)_clocks.c \
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events.c \
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events.c \
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fatfs_port.c \
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fatfs_port.c \
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flash_api.c \
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flash_api.c \
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@ -238,6 +239,8 @@ SRC_C = \
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timers.c \
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timers.c \
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usb.c \
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usb.c \
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usb_mass_storage.c \
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usb_mass_storage.c \
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bindings/samd/__init__.c \
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bindings/samd/Clock.c \
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boards/$(BOARD)/board.c \
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boards/$(BOARD)/board.c \
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boards/$(BOARD)/pins.c \
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boards/$(BOARD)/pins.c \
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lib/oofatfs/ff.c \
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lib/oofatfs/ff.c \
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@ -231,3 +231,9 @@ Mass storage
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All boards will also show up as a mass storage device. Make sure to eject it
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All boards will also show up as a mass storage device. Make sure to eject it
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before resetting or disconnecting the board.
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before resetting or disconnecting the board.
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Port Specific modules
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---------------------
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.. toctree::
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bindings/samd/__init__
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@ -109,7 +109,7 @@
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// <i> Indicates whether configuration for OSC32K is enabled or not
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// <i> Indicates whether configuration for OSC32K is enabled or not
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// <id> enable_osc32k
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// <id> enable_osc32k
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#ifndef CONF_OSC32K_CONFIG
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#ifndef CONF_OSC32K_CONFIG
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#define CONF_OSC32K_CONFIG 0
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#define CONF_OSC32K_CONFIG 1
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#endif
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#endif
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// <h> 32kHz Internal Oscillator (OSC32K) Control
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// <h> 32kHz Internal Oscillator (OSC32K) Control
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@ -117,7 +117,7 @@
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// <i> Indicates whether Internal 32K Oscillator is enabled or not
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// <i> Indicates whether Internal 32K Oscillator is enabled or not
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// <id> osc32k_arch_enable
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// <id> osc32k_arch_enable
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#ifndef CONF_OSC32K_ENABLE
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#ifndef CONF_OSC32K_ENABLE
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#define CONF_OSC32K_ENABLE 0
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#define CONF_OSC32K_ENABLE 1
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#endif
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#endif
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// <q> On Demand Control
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// <q> On Demand Control
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@ -142,7 +142,7 @@
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// <i> Enable 32 Khz Output
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// <i> Enable 32 Khz Output
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// <id> osc32k_arch_en32k
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// <id> osc32k_arch_en32k
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#ifndef CONF_OSC32K_EN32K
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#ifndef CONF_OSC32K_EN32K
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#define CONF_OSC32K_EN32K 0
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#define CONF_OSC32K_EN32K 1
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#endif
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#endif
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// <q> Enable 1K
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// <q> Enable 1K
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@ -0,0 +1,174 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 Noralf Trønnes
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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||||||
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "clocks.h"
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#include "bindings/samd/Clock.h"
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#include "py/obj.h"
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#include "py/objproperty.h"
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#include "py/runtime.h"
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//| .. currentmodule:: samd
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//|
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//| :class:`Clock` --- Clock reference
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//| ------------------------------------------
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//|
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//| Identifies a clock on the microcontroller.
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//|
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//| .. class:: Clock
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//|
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//| Identifies a clock on the microcontroller. They are fixed by the
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//| hardware so they cannot be constructed on demand. Instead, use
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//| `samd.clock` to reference the desired clock.
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//|
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STATIC void samd_clock_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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samd_clock_obj_t *self = MP_OBJ_TO_PTR(self_in);
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mp_printf(print, "%q.%q.%s(", MP_QSTR_samd, MP_QSTR_clock, self->name);
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if (clock_get_enabled(self->type, self->index)) {
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mp_printf(print, "frequency=%u", clock_get_frequency(self->type, self->index));
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uint32_t calibration = clock_get_calibration(self->type, self->index);
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if (calibration) {
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mp_printf(print, ", calibration=%u", calibration);
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}
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}
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mp_printf(print, ")");
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}
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//| .. attribute:: enabled
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//|
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//| Is the clock enabled? (read-only)
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//|
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STATIC mp_obj_t samd_clock_get_enabled(mp_obj_t self_in) {
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samd_clock_obj_t *self = MP_OBJ_TO_PTR(self_in);
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return mp_obj_new_bool(clock_get_enabled(self->type, self->index));
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}
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MP_DEFINE_CONST_FUN_OBJ_1(samd_clock_get_enabled_obj, samd_clock_get_enabled);
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const mp_obj_property_t samd_clock_enabled_obj = {
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.base.type = &mp_type_property,
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.proxy = {(mp_obj_t)&samd_clock_get_enabled_obj,
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(mp_obj_t)&mp_const_none_obj,
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(mp_obj_t)&mp_const_none_obj,
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},
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};
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//| .. attribute:: parent
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//|
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//| Clock parent. (read-only)
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//|
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STATIC mp_obj_t samd_clock_get_parent(mp_obj_t self_in) {
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samd_clock_obj_t *self = MP_OBJ_TO_PTR(self_in);
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uint8_t p_type, p_index;
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if (!clock_get_parent(self->type, self->index, &p_type, &p_index))
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return mp_const_none;
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const mp_map_t* samd_map = &samd_clock_globals.map;
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for (uint8_t i = 0; i < samd_map->alloc; i++) {
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samd_clock_obj_t *iter = samd_map->table[i].value;
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if (iter->type == p_type && iter->index == p_index)
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return iter;
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}
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_1(samd_clock_get_parent_obj, samd_clock_get_parent);
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const mp_obj_property_t samd_clock_parent_obj = {
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.base.type = &mp_type_property,
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.proxy = {(mp_obj_t)&samd_clock_get_parent_obj,
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(mp_obj_t)&mp_const_none_obj,
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(mp_obj_t)&mp_const_none_obj,
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},
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};
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//| .. attribute:: frequency
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//|
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//| Clock frequency. (read-only)
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//|
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STATIC mp_obj_t samd_clock_get_frequency(mp_obj_t self_in) {
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samd_clock_obj_t *self = MP_OBJ_TO_PTR(self_in);
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return mp_obj_new_int_from_uint(clock_get_frequency(self->type, self->index));
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}
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MP_DEFINE_CONST_FUN_OBJ_1(samd_clock_get_frequency_obj, samd_clock_get_frequency);
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const mp_obj_property_t samd_clock_frequency_obj = {
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.base.type = &mp_type_property,
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.proxy = {(mp_obj_t)&samd_clock_get_frequency_obj,
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(mp_obj_t)&mp_const_none_obj,
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(mp_obj_t)&mp_const_none_obj,
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},
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};
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//| .. attribute:: calibration
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//|
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//| Clock calibration. Not all clocks can be calibrated.
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//|
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STATIC mp_obj_t samd_clock_get_calibration(mp_obj_t self_in) {
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samd_clock_obj_t *self = MP_OBJ_TO_PTR(self_in);
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return mp_obj_new_int_from_uint(clock_get_calibration(self->type, self->index));
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}
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MP_DEFINE_CONST_FUN_OBJ_1(samd_clock_get_calibration_obj, samd_clock_get_calibration);
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STATIC mp_obj_t samd_clock_set_calibration(mp_obj_t self_in, mp_obj_t calibration) {
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samd_clock_obj_t *self = MP_OBJ_TO_PTR(self_in);
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int ret = clock_set_calibration(self->type, self->index, mp_obj_get_int(calibration));
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if (ret == -2)
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mp_raise_AttributeError("calibration is read only");
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if (ret == -1)
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mp_raise_ValueError("calibration is out of range");
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_2(samd_clock_set_calibration_obj, samd_clock_set_calibration);
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const mp_obj_property_t samd_clock_calibration_obj = {
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.base.type = &mp_type_property,
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.proxy = {(mp_obj_t)&samd_clock_get_calibration_obj,
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(mp_obj_t)&samd_clock_set_calibration_obj,
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(mp_obj_t)&mp_const_none_obj,
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},
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};
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STATIC const mp_rom_map_elem_t samd_clock_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_enabled), MP_ROM_PTR(&samd_clock_enabled_obj) },
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{ MP_ROM_QSTR(MP_QSTR_parent), MP_ROM_PTR(&samd_clock_parent_obj) },
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{ MP_ROM_QSTR(MP_QSTR_frequency), MP_ROM_PTR(&samd_clock_frequency_obj) },
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{ MP_ROM_QSTR(MP_QSTR_calibration), MP_ROM_PTR(&samd_clock_calibration_obj) },
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};
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STATIC MP_DEFINE_CONST_DICT(samd_clock_locals_dict, samd_clock_locals_dict_table);
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const mp_obj_type_t samd_clock_type = {
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{ &mp_type_type },
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.name = MP_QSTR_Clock,
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.print = samd_clock_print,
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.locals_dict = (mp_obj_t)&samd_clock_locals_dict,
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};
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@ -0,0 +1,77 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
|
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|
*
|
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|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 Noralf Trønnes
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
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|
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#ifndef MICROPY_INCLUDED_ATMEL_SAMD_BINDINGS_SAMD_CLOCK_H
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#define MICROPY_INCLUDED_ATMEL_SAMD_BINDINGS_SAMD_CLOCK_H
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#include "py/obj.h"
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typedef struct {
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mp_obj_base_t base;
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const char *name;
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uint8_t type;
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uint8_t index;
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} samd_clock_obj_t;
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#define CLOCK(_name, _type, _index) \
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const samd_clock_obj_t clock_ ## _name = { \
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{ &samd_clock_type }, \
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.name = #_name, \
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.type = _type, \
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.index = _index, \
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}
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#define CLOCK_SOURCE(_name) \
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const samd_clock_obj_t clock_ ## _name = { \
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{ &samd_clock_type }, \
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.name = #_name, \
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.type = 0, \
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.index = GCLK_SOURCE_ ## _name, \
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}
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#define CLOCK_GCLK(_name) \
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const samd_clock_obj_t clock_ ## _name = { \
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{ &samd_clock_type }, \
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.name = #_name, \
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.type = 1, \
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.index = _name ## _GCLK_ID, \
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}
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#define CLOCK_GCLK_(_name, _extra) \
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const samd_clock_obj_t clock_ ## _name ## _ ## _extra = { \
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{ &samd_clock_type }, \
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.name = #_name "_" #_extra, \
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.type = 1, \
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.index = _name ## _GCLK_ID_ ## _extra, \
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}
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#define CLOCK_ENTRY(_name) { MP_ROM_QSTR(MP_QSTR_ ## _name), MP_ROM_PTR(&clock_ ## _name) }
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#define CLOCK_ENTRY_(_name, _extra) { MP_ROM_QSTR(MP_QSTR_ ## _name ## _ ## _extra), MP_ROM_PTR(&clock_ ## _name ## _ ## _extra) }
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||||||
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extern const mp_obj_type_t samd_clock_type;
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extern const mp_obj_dict_t samd_clock_globals;
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|
||||||
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#endif // MICROPY_INCLUDED_ATMEL_SAMD_BINDINGS_SAMD_CLOCK_H
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|
@ -0,0 +1,72 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the MicroPython project, http://micropython.org/
|
||||||
|
*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 Noralf Trønnes
|
||||||
|
* Copyright (c) 2016 Scott Shawcroft for Adafruit Industries
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "py/obj.h"
|
||||||
|
#include "py/runtime.h"
|
||||||
|
|
||||||
|
#include "bindings/samd/Clock.h"
|
||||||
|
|
||||||
|
//| :mod:`samd` --- SAMD implementation settings
|
||||||
|
//| =================================================
|
||||||
|
//|
|
||||||
|
//| .. module:: samd
|
||||||
|
//| :synopsis: SAMD implementation settings
|
||||||
|
//| :platform: SAMD21
|
||||||
|
//|
|
||||||
|
//| Libraries
|
||||||
|
//|
|
||||||
|
//| .. toctree::
|
||||||
|
//| :maxdepth: 3
|
||||||
|
//|
|
||||||
|
//| Clock
|
||||||
|
//|
|
||||||
|
|
||||||
|
//| :mod:`samd.clock` --- samd clock names
|
||||||
|
//| --------------------------------------------------------
|
||||||
|
//|
|
||||||
|
//| .. module:: samd.clock
|
||||||
|
//| :synopsis: samd clock names
|
||||||
|
//| :platform: SAMD21
|
||||||
|
//|
|
||||||
|
//| References to clocks as named by the microcontroller
|
||||||
|
//|
|
||||||
|
const mp_obj_module_t samd_clock_module = {
|
||||||
|
.base = { &mp_type_module },
|
||||||
|
.globals = (mp_obj_dict_t*)&samd_clock_globals,
|
||||||
|
};
|
||||||
|
|
||||||
|
STATIC const mp_rom_map_elem_t samd_module_globals_table[] = {
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_samd) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_clock), MP_ROM_PTR(&samd_clock_module) },
|
||||||
|
};
|
||||||
|
|
||||||
|
STATIC MP_DEFINE_CONST_DICT(samd_module_globals, samd_module_globals_table);
|
||||||
|
|
||||||
|
const mp_obj_module_t samd_module = {
|
||||||
|
.base = { &mp_type_module },
|
||||||
|
.globals = (mp_obj_dict_t*)&samd_module_globals,
|
||||||
|
};
|
||||||
|
|
@ -46,3 +46,5 @@
|
||||||
GD25Q16C
|
GD25Q16C
|
||||||
|
|
||||||
#include "external_flash/external_flash.h"
|
#include "external_flash/external_flash.h"
|
||||||
|
|
||||||
|
#define BOARD_HAS_CRYSTAL 1
|
||||||
|
|
|
||||||
|
|
@ -47,3 +47,5 @@
|
||||||
GD25Q16C
|
GD25Q16C
|
||||||
|
|
||||||
#include "external_flash/external_flash.h"
|
#include "external_flash/external_flash.h"
|
||||||
|
|
||||||
|
#define BOARD_HAS_CRYSTAL 1
|
||||||
|
|
|
||||||
|
|
@ -56,77 +56,6 @@ uint8_t find_free_gclk(uint16_t divisor) {
|
||||||
return 0xff;
|
return 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool gclk_enabled(uint8_t gclk) {
|
|
||||||
#ifdef SAMD51
|
|
||||||
return GCLK->GENCTRL[gclk].bit.GENEN;
|
|
||||||
#endif
|
|
||||||
#ifdef SAMD21
|
|
||||||
common_hal_mcu_disable_interrupts();
|
|
||||||
// Explicitly do a byte write so the peripheral knows we're just wanting to read the channel
|
|
||||||
// rather than write to it.
|
|
||||||
*((uint8_t*) &GCLK->GENCTRL.reg) = gclk;
|
|
||||||
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
|
||||||
bool enabled = GCLK->GENCTRL.bit.GENEN;
|
|
||||||
common_hal_mcu_enable_interrupts();
|
|
||||||
return enabled;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void disable_gclk(uint8_t gclk) {
|
|
||||||
#ifdef SAMD51
|
|
||||||
while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
|
|
||||||
GCLK->GENCTRL[gclk].bit.GENEN = false;
|
|
||||||
while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
|
|
||||||
#endif
|
|
||||||
#ifdef SAMD21
|
|
||||||
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
|
||||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
|
|
||||||
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
|
|
||||||
#ifdef SAMD21
|
|
||||||
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk) | GCLK_CLKCTRL_CLKEN;
|
|
||||||
#endif
|
|
||||||
#ifdef SAMD51
|
|
||||||
GCLK->PCHCTRL[peripheral].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk);
|
|
||||||
while(GCLK->SYNCBUSY.reg != 0) {}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
|
|
||||||
#ifdef SAMD21
|
|
||||||
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk);
|
|
||||||
#endif
|
|
||||||
#ifdef SAMD51
|
|
||||||
GCLK->PCHCTRL[peripheral].reg = 0;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void enable_clock_generator(uint8_t gclk, uint8_t source, uint16_t divisor) {
|
|
||||||
#ifdef SAMD21
|
|
||||||
GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk) | GCLK_GENDIV_DIV(divisor);
|
|
||||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk) | GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_GENEN;
|
|
||||||
while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
|
|
||||||
#endif
|
|
||||||
#ifdef SAMD51
|
|
||||||
GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_DIV(divisor) | GCLK_GENCTRL_GENEN;
|
|
||||||
while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void disable_clock_generator(uint8_t gclk) {
|
|
||||||
#ifdef SAMD21
|
|
||||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
|
|
||||||
while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
|
|
||||||
#endif
|
|
||||||
#ifdef SAMD51
|
|
||||||
GCLK->GENCTRL[gclk].reg = 0;
|
|
||||||
while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void reset_gclks(void) {
|
void reset_gclks(void) {
|
||||||
// Never reset GCLK0 because its used for the core
|
// Never reset GCLK0 because its used for the core
|
||||||
#if CONF_GCLK_GEN_1_GENEN == 0
|
#if CONF_GCLK_GEN_1_GENEN == 0
|
||||||
|
|
|
||||||
|
|
@ -31,6 +31,7 @@
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#include "include/sam.h"
|
#include "include/sam.h"
|
||||||
|
#include "mpconfigboard.h" // for BOARD_HAS_CRYSTAL
|
||||||
|
|
||||||
#ifdef SAMD51
|
#ifdef SAMD51
|
||||||
#define CLOCK_48MHZ GCLK_GENCTRL_SRC_DFLL_Val
|
#define CLOCK_48MHZ GCLK_GENCTRL_SRC_DFLL_Val
|
||||||
|
|
@ -44,12 +45,29 @@
|
||||||
uint8_t find_free_gclk(uint16_t divisor);
|
uint8_t find_free_gclk(uint16_t divisor);
|
||||||
|
|
||||||
bool gclk_enabled(uint8_t gclk);
|
bool gclk_enabled(uint8_t gclk);
|
||||||
|
void disable_gclk(uint8_t gclk);
|
||||||
void reset_gclks(void);
|
void reset_gclks(void);
|
||||||
|
|
||||||
void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral);
|
void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral);
|
||||||
void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral);
|
void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral);
|
||||||
|
|
||||||
void enable_clock_generator(uint8_t gclk, uint8_t source, uint16_t divisor);
|
void enable_clock_generator(uint8_t gclk, uint32_t source, uint16_t divisor);
|
||||||
void disable_clock_generator(uint8_t gclk);
|
void disable_clock_generator(uint8_t gclk);
|
||||||
|
|
||||||
|
static inline bool board_has_crystal(void) {
|
||||||
|
#ifdef BOARD_HAS_CRYSTAL
|
||||||
|
return BOARD_HAS_CRYSTAL == 1;
|
||||||
|
#else
|
||||||
|
return false;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_init(void);
|
||||||
|
|
||||||
|
bool clock_get_enabled(uint8_t type, uint8_t index);
|
||||||
|
bool clock_get_parent(uint8_t type, uint8_t index, uint8_t *p_type, uint8_t *p_index);
|
||||||
|
uint32_t clock_get_frequency(uint8_t type, uint8_t index);
|
||||||
|
uint32_t clock_get_calibration(uint8_t type, uint8_t index);
|
||||||
|
int clock_set_calibration(uint8_t type, uint8_t index, uint32_t val);
|
||||||
|
|
||||||
#endif // MICROPY_INCLUDED_ATMEL_SAMD_CLOCKS_H
|
#endif // MICROPY_INCLUDED_ATMEL_SAMD_CLOCKS_H
|
||||||
|
|
|
||||||
|
|
@ -167,6 +167,7 @@ extern const struct _mp_obj_module_t math_module;
|
||||||
extern const struct _mp_obj_module_t os_module;
|
extern const struct _mp_obj_module_t os_module;
|
||||||
extern const struct _mp_obj_module_t random_module;
|
extern const struct _mp_obj_module_t random_module;
|
||||||
extern const struct _mp_obj_module_t rtc_module;
|
extern const struct _mp_obj_module_t rtc_module;
|
||||||
|
extern const struct _mp_obj_module_t samd_module;
|
||||||
extern const struct _mp_obj_module_t storage_module;
|
extern const struct _mp_obj_module_t storage_module;
|
||||||
extern const struct _mp_obj_module_t struct_module;
|
extern const struct _mp_obj_module_t struct_module;
|
||||||
extern const struct _mp_obj_module_t time_module;
|
extern const struct _mp_obj_module_t time_module;
|
||||||
|
|
@ -236,6 +237,7 @@ extern const struct _mp_obj_module_t usb_hid_module;
|
||||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_pulseio), (mp_obj_t)&pulseio_module }, \
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_pulseio), (mp_obj_t)&pulseio_module }, \
|
||||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_random), (mp_obj_t)&random_module }, \
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_random), (mp_obj_t)&random_module }, \
|
||||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_rtc), (mp_obj_t)&rtc_module }, \
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_rtc), (mp_obj_t)&rtc_module }, \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_samd),(mp_obj_t)&samd_module }, \
|
||||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_storage), (mp_obj_t)&storage_module }, \
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_storage), (mp_obj_t)&storage_module }, \
|
||||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_struct), (mp_obj_t)&struct_module }, \
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_struct), (mp_obj_t)&struct_module }, \
|
||||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_supervisor), (mp_obj_t)&supervisor_module }, \
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_supervisor), (mp_obj_t)&supervisor_module }, \
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,425 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the MicroPython project, http://micropython.org/
|
||||||
|
*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "clocks.h"
|
||||||
|
|
||||||
|
#include "hpl_gclk_config.h"
|
||||||
|
|
||||||
|
#include "bindings/samd/Clock.h"
|
||||||
|
#include "shared-bindings/microcontroller/__init__.h"
|
||||||
|
|
||||||
|
#include "py/runtime.h"
|
||||||
|
|
||||||
|
bool gclk_enabled(uint8_t gclk) {
|
||||||
|
common_hal_mcu_disable_interrupts();
|
||||||
|
// Explicitly do a byte write so the peripheral knows we're just wanting to read the channel
|
||||||
|
// rather than write to it.
|
||||||
|
*((uint8_t*) &GCLK->GENCTRL.reg) = gclk;
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
||||||
|
bool enabled = GCLK->GENCTRL.bit.GENEN;
|
||||||
|
common_hal_mcu_enable_interrupts();
|
||||||
|
return enabled;
|
||||||
|
}
|
||||||
|
|
||||||
|
void disable_gclk(uint8_t gclk) {
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
||||||
|
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
|
||||||
|
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk) | GCLK_CLKCTRL_CLKEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
|
||||||
|
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_clock_generator(uint8_t gclk, uint32_t source, uint16_t divisor) {
|
||||||
|
uint32_t divsel = 0;
|
||||||
|
if (gclk == 2 && divisor > 31) {
|
||||||
|
divsel = GCLK_GENCTRL_DIVSEL;
|
||||||
|
for (int i = 15; i > 4; i++) {
|
||||||
|
if (divisor & (1 << i)) {
|
||||||
|
divisor = i - 1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk) | GCLK_GENDIV_DIV(divisor);
|
||||||
|
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk) | GCLK_GENCTRL_SRC(source) | divsel | GCLK_GENCTRL_OE | GCLK_GENCTRL_GENEN;
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
void disable_clock_generator(uint8_t gclk) {
|
||||||
|
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void init_clock_source_osc8m(void) {
|
||||||
|
// Preserve CALIB and FRANGE
|
||||||
|
SYSCTRL->OSC8M.bit.ONDEMAND = 0;
|
||||||
|
SYSCTRL->OSC8M.bit.PRESC = 3;
|
||||||
|
SYSCTRL->OSC8M.bit.ENABLE = 1;
|
||||||
|
while (!SYSCTRL->PCLKSR.bit.OSC8MRDY) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void init_clock_source_osc32k(void) {
|
||||||
|
uint32_t calib = (*((uint32_t *)FUSES_OSC32K_CAL_ADDR) & FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
|
||||||
|
SYSCTRL->OSC32K.reg = SYSCTRL_OSC32K_CALIB(calib) |
|
||||||
|
SYSCTRL_OSC32K_EN32K |
|
||||||
|
SYSCTRL_OSC32K_ENABLE;
|
||||||
|
while (!SYSCTRL->PCLKSR.bit.OSC32KRDY) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void init_clock_source_xosc32k(void) {
|
||||||
|
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_EN32K |
|
||||||
|
SYSCTRL_XOSC32K_XTALEN |
|
||||||
|
SYSCTRL_XOSC32K_ENABLE;
|
||||||
|
while (!SYSCTRL->PCLKSR.bit.XOSC32KRDY) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void init_clock_source_dfll48m(void) {
|
||||||
|
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
|
||||||
|
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}
|
||||||
|
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(1) |
|
||||||
|
SYSCTRL_DFLLMUL_FSTEP(1) |
|
||||||
|
SYSCTRL_DFLLMUL_MUL(48000);
|
||||||
|
uint32_t coarse = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR) & FUSES_DFLL48M_COARSE_CAL_Msk) >> FUSES_DFLL48M_COARSE_CAL_Pos;
|
||||||
|
if (coarse == 0x3f)
|
||||||
|
coarse = 0x1f;
|
||||||
|
SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) |
|
||||||
|
SYSCTRL_DFLLVAL_FINE(512);
|
||||||
|
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_CCDIS |
|
||||||
|
SYSCTRL_DFLLCTRL_USBCRM |
|
||||||
|
SYSCTRL_DFLLCTRL_MODE |
|
||||||
|
SYSCTRL_DFLLCTRL_ENABLE;
|
||||||
|
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_init(void)
|
||||||
|
{
|
||||||
|
init_clock_source_osc8m();
|
||||||
|
if (board_has_crystal())
|
||||||
|
init_clock_source_xosc32k();
|
||||||
|
else
|
||||||
|
init_clock_source_osc32k();
|
||||||
|
enable_clock_generator(0, GCLK_GENCTRL_SRC_DFLL48M_Val, 1);
|
||||||
|
enable_clock_generator(1, GCLK_GENCTRL_SRC_DFLL48M_Val, 150);
|
||||||
|
init_clock_source_dfll48m();
|
||||||
|
if (board_has_crystal())
|
||||||
|
enable_clock_generator(2, GCLK_GENCTRL_SRC_XOSC32K_Val, 32);
|
||||||
|
else
|
||||||
|
enable_clock_generator(2, GCLK_GENCTRL_SRC_OSC32K_Val, 32);
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool clk_enabled(uint8_t clk) {
|
||||||
|
common_hal_mcu_disable_interrupts();
|
||||||
|
*((uint8_t*) &GCLK->CLKCTRL.reg) = clk;
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
||||||
|
bool enabled = GCLK->CLKCTRL.bit.CLKEN;
|
||||||
|
common_hal_mcu_enable_interrupts();
|
||||||
|
return enabled;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint8_t clk_get_generator(uint8_t clk) {
|
||||||
|
common_hal_mcu_disable_interrupts();
|
||||||
|
*((uint8_t*) &GCLK->CLKCTRL.reg) = clk;
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
||||||
|
uint8_t gen = GCLK->CLKCTRL.bit.GEN;
|
||||||
|
common_hal_mcu_enable_interrupts();
|
||||||
|
return gen;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint8_t generator_get_source(uint8_t gen) {
|
||||||
|
common_hal_mcu_disable_interrupts();
|
||||||
|
*((uint8_t*) &GCLK->GENCTRL.reg) = gen;
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
||||||
|
uint8_t src = GCLK->GENCTRL.bit.SRC;
|
||||||
|
common_hal_mcu_enable_interrupts();
|
||||||
|
return src;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool osc_enabled(uint8_t index) {
|
||||||
|
switch (index) {
|
||||||
|
case GCLK_SOURCE_XOSC:
|
||||||
|
return SYSCTRL->XOSC.bit.ENABLE;
|
||||||
|
// TODO: GCLK_SOURCE_GCLKIN
|
||||||
|
// TODO: GCLK_SOURCE_GCLKGEN1
|
||||||
|
case GCLK_SOURCE_OSCULP32K:
|
||||||
|
return true;
|
||||||
|
case GCLK_SOURCE_OSC32K:
|
||||||
|
return SYSCTRL->OSC32K.bit.ENABLE;
|
||||||
|
case GCLK_SOURCE_XOSC32K:
|
||||||
|
return SYSCTRL->XOSC32K.bit.ENABLE;
|
||||||
|
case GCLK_SOURCE_OSC8M:
|
||||||
|
return SYSCTRL->OSC8M.bit.ENABLE;
|
||||||
|
case GCLK_SOURCE_DFLL48M:
|
||||||
|
return SYSCTRL->DFLLCTRL.bit.ENABLE;
|
||||||
|
case GCLK_SOURCE_DPLL96M:
|
||||||
|
return SYSCTRL->DPLLCTRLA.bit.ENABLE;
|
||||||
|
};
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t osc_get_frequency(uint8_t index) {
|
||||||
|
switch (index) {
|
||||||
|
case GCLK_SOURCE_XOSC:
|
||||||
|
return 0; // unknown 0.4-32MHz
|
||||||
|
// TODO: GCLK_SOURCE_GCLKIN
|
||||||
|
// TODO: GCLK_SOURCE_GCLKGEN1
|
||||||
|
case GCLK_SOURCE_OSCULP32K:
|
||||||
|
case GCLK_SOURCE_OSC32K:
|
||||||
|
case GCLK_SOURCE_XOSC32K:
|
||||||
|
return 32768;
|
||||||
|
case GCLK_SOURCE_OSC8M:
|
||||||
|
return 8000000;
|
||||||
|
case GCLK_SOURCE_DFLL48M:
|
||||||
|
return 48000000;
|
||||||
|
case GCLK_SOURCE_DPLL96M:
|
||||||
|
return 96000000;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool clock_get_enabled(uint8_t type, uint8_t index) {
|
||||||
|
if (type == 0)
|
||||||
|
return osc_enabled(index);
|
||||||
|
if (type == 1)
|
||||||
|
return clk_enabled(index);
|
||||||
|
if (type == 2)
|
||||||
|
return SysTick->CTRL & SysTick_CTRL_ENABLE_Msk;
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool clock_get_parent(uint8_t type, uint8_t index, uint8_t *p_type, uint8_t *p_index) {
|
||||||
|
if (type == 1 && index <= 0x24 && clk_enabled(index)) {
|
||||||
|
*p_type = 0;
|
||||||
|
*p_index = generator_get_source(clk_get_generator(index));
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
if (type == 2 && index == 0) {
|
||||||
|
*p_type = 0;
|
||||||
|
*p_index = generator_get_source(0);
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t clock_get_frequency(uint8_t type, uint8_t index) {
|
||||||
|
if (type == 0) {
|
||||||
|
return osc_get_frequency(index);
|
||||||
|
}
|
||||||
|
if (type == 1) {
|
||||||
|
if (!clk_enabled(index))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
uint8_t gen = clk_get_generator(index);
|
||||||
|
|
||||||
|
common_hal_mcu_disable_interrupts();
|
||||||
|
*((uint8_t*) &GCLK->GENCTRL.reg) = gen;
|
||||||
|
*((uint8_t*) &GCLK->GENDIV.reg) = gen;
|
||||||
|
while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
|
||||||
|
|
||||||
|
uint8_t src = GCLK->GENCTRL.bit.SRC;
|
||||||
|
uint32_t div;
|
||||||
|
if (GCLK->GENCTRL.bit.DIVSEL) {
|
||||||
|
div = 1 << (GCLK->GENDIV.bit.DIV + 1);
|
||||||
|
} else {
|
||||||
|
div = GCLK->GENDIV.bit.DIV;
|
||||||
|
if (!div)
|
||||||
|
div = 1;
|
||||||
|
}
|
||||||
|
common_hal_mcu_enable_interrupts();
|
||||||
|
|
||||||
|
return osc_get_frequency(src) / div;
|
||||||
|
}
|
||||||
|
if (type == 2 && index == 0) {
|
||||||
|
return clock_get_frequency(0, generator_get_source(0)) / SysTick->LOAD;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t clock_get_calibration(uint8_t type, uint8_t index) {
|
||||||
|
if (type == 0) {
|
||||||
|
switch (index) {
|
||||||
|
case GCLK_SOURCE_OSCULP32K:
|
||||||
|
return SYSCTRL->OSCULP32K.bit.CALIB;
|
||||||
|
case GCLK_SOURCE_OSC32K:
|
||||||
|
return SYSCTRL->OSC32K.bit.CALIB;
|
||||||
|
case GCLK_SOURCE_OSC8M:
|
||||||
|
return SYSCTRL->OSC8M.bit.CALIB;
|
||||||
|
};
|
||||||
|
}
|
||||||
|
if (type == 2 && index == 0) {
|
||||||
|
return SysTick->LOAD + 1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int clock_set_calibration(uint8_t type, uint8_t index, uint32_t val) {
|
||||||
|
if (type == 0) {
|
||||||
|
switch (index) {
|
||||||
|
case GCLK_SOURCE_OSCULP32K:
|
||||||
|
if (val > 0x1f)
|
||||||
|
return -1;
|
||||||
|
SYSCTRL->OSCULP32K.bit.CALIB = val;
|
||||||
|
return 0;
|
||||||
|
case GCLK_SOURCE_OSC32K:
|
||||||
|
if (val > 0x7f)
|
||||||
|
return -1;
|
||||||
|
SYSCTRL->OSC32K.bit.CALIB = val;
|
||||||
|
return 0;
|
||||||
|
case GCLK_SOURCE_OSC8M:
|
||||||
|
if (val > 0xfff)
|
||||||
|
return -1;
|
||||||
|
SYSCTRL->OSC8M.bit.CALIB = val;
|
||||||
|
return 0;
|
||||||
|
};
|
||||||
|
}
|
||||||
|
if (type == 2 && index == 0) {
|
||||||
|
if (val < 0x1000 || val > 0x1000000)
|
||||||
|
return -1;
|
||||||
|
SysTick->LOAD = val - 1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
return -2; // calibration is read only
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
|
||||||
|
CLOCK_SOURCE(XOSC);
|
||||||
|
CLOCK_SOURCE(GCLKIN);
|
||||||
|
CLOCK_SOURCE(GCLKGEN1);
|
||||||
|
CLOCK_SOURCE(OSCULP32K);
|
||||||
|
#endif
|
||||||
|
CLOCK_SOURCE(OSC32K);
|
||||||
|
CLOCK_SOURCE(XOSC32K);
|
||||||
|
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
|
||||||
|
CLOCK_SOURCE(OSC8M);
|
||||||
|
CLOCK_SOURCE(DFLL48M);
|
||||||
|
CLOCK_SOURCE(DPLL96M);
|
||||||
|
|
||||||
|
CLOCK_GCLK_(SYSCTRL, DFLL48);
|
||||||
|
CLOCK_GCLK_(SYSCTRL, FDPLL);
|
||||||
|
CLOCK_GCLK_(SYSCTRL, FDPLL32K);
|
||||||
|
CLOCK_GCLK(WDT);
|
||||||
|
#endif
|
||||||
|
CLOCK_GCLK(RTC);
|
||||||
|
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
|
||||||
|
CLOCK_GCLK(EIC);
|
||||||
|
CLOCK_GCLK(USB);
|
||||||
|
CLOCK_GCLK_(EVSYS, 0);
|
||||||
|
CLOCK_GCLK_(EVSYS, 1);
|
||||||
|
CLOCK_GCLK_(EVSYS, 2);
|
||||||
|
CLOCK_GCLK_(EVSYS, 3);
|
||||||
|
CLOCK_GCLK_(EVSYS, 4);
|
||||||
|
CLOCK_GCLK_(EVSYS, 5);
|
||||||
|
CLOCK_GCLK_(EVSYS, 6);
|
||||||
|
CLOCK_GCLK_(EVSYS, 7);
|
||||||
|
CLOCK_GCLK_(EVSYS, 8);
|
||||||
|
CLOCK_GCLK_(EVSYS, 9);
|
||||||
|
CLOCK_GCLK_(EVSYS, 10);
|
||||||
|
CLOCK_GCLK_(EVSYS, 11);
|
||||||
|
CLOCK(SERCOMx_SLOW, 1, 19);
|
||||||
|
CLOCK_GCLK_(SERCOM0, CORE);
|
||||||
|
CLOCK_GCLK_(SERCOM1, CORE);
|
||||||
|
CLOCK_GCLK_(SERCOM2, CORE);
|
||||||
|
CLOCK_GCLK_(SERCOM3, CORE);
|
||||||
|
CLOCK_GCLK_(SERCOM4, CORE);
|
||||||
|
CLOCK_GCLK_(SERCOM5, CORE);
|
||||||
|
CLOCK(TCC0_TCC1, 1, 26);
|
||||||
|
CLOCK(TCC2_TCC3, 1, 27);
|
||||||
|
CLOCK(TC4_TC5, 1, 28);
|
||||||
|
CLOCK(TC6_TC7, 1, 29);
|
||||||
|
CLOCK_GCLK(ADC);
|
||||||
|
CLOCK_GCLK_(AC, DIG);
|
||||||
|
CLOCK_GCLK_(AC, ANA);
|
||||||
|
CLOCK_GCLK(DAC);
|
||||||
|
CLOCK_GCLK(PTC);
|
||||||
|
CLOCK_GCLK_(I2S, 0);
|
||||||
|
CLOCK_GCLK_(I2S, 1);
|
||||||
|
|
||||||
|
CLOCK(SYSTICK, 2, 0);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
|
||||||
|
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
|
||||||
|
CLOCK_ENTRY(XOSC),
|
||||||
|
CLOCK_ENTRY(GCLKIN),
|
||||||
|
CLOCK_ENTRY(GCLKGEN1),
|
||||||
|
CLOCK_ENTRY(OSCULP32K),
|
||||||
|
#endif
|
||||||
|
CLOCK_ENTRY(OSC32K),
|
||||||
|
CLOCK_ENTRY(XOSC32K),
|
||||||
|
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
|
||||||
|
CLOCK_ENTRY(OSC8M),
|
||||||
|
CLOCK_ENTRY(DFLL48M),
|
||||||
|
CLOCK_ENTRY(DPLL96M),
|
||||||
|
CLOCK_ENTRY_(SYSCTRL, DFLL48),
|
||||||
|
CLOCK_ENTRY_(SYSCTRL, FDPLL),
|
||||||
|
CLOCK_ENTRY_(SYSCTRL, FDPLL32K),
|
||||||
|
CLOCK_ENTRY(WDT),
|
||||||
|
#endif
|
||||||
|
CLOCK_ENTRY(RTC),
|
||||||
|
#ifdef SAMD21_EXPOSE_ALL_CLOCKS
|
||||||
|
CLOCK_ENTRY(EIC),
|
||||||
|
CLOCK_ENTRY(USB),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 0),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 1),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 2),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 3),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 4),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 5),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 6),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 7),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 8),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 9),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 10),
|
||||||
|
CLOCK_ENTRY_(EVSYS, 11),
|
||||||
|
CLOCK_ENTRY(SERCOMx_SLOW),
|
||||||
|
CLOCK_ENTRY_(SERCOM0, CORE),
|
||||||
|
CLOCK_ENTRY_(SERCOM1, CORE),
|
||||||
|
CLOCK_ENTRY_(SERCOM2, CORE),
|
||||||
|
CLOCK_ENTRY_(SERCOM3, CORE),
|
||||||
|
CLOCK_ENTRY_(SERCOM4, CORE),
|
||||||
|
CLOCK_ENTRY_(SERCOM5, CORE),
|
||||||
|
CLOCK_ENTRY(TCC0_TCC1),
|
||||||
|
CLOCK_ENTRY(TCC2_TCC3),
|
||||||
|
CLOCK_ENTRY(TC4_TC5),
|
||||||
|
CLOCK_ENTRY(TC6_TC7),
|
||||||
|
CLOCK_ENTRY(ADC),
|
||||||
|
CLOCK_ENTRY_(AC, DIG),
|
||||||
|
CLOCK_ENTRY_(AC, ANA),
|
||||||
|
CLOCK_ENTRY(DAC),
|
||||||
|
CLOCK_ENTRY(PTC),
|
||||||
|
CLOCK_ENTRY_(I2S, 0),
|
||||||
|
CLOCK_ENTRY_(I2S, 1),
|
||||||
|
|
||||||
|
CLOCK_ENTRY(SYSTICK),
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
|
||||||
|
|
@ -0,0 +1,86 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the MicroPython project, http://micropython.org/
|
||||||
|
*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "clocks.h"
|
||||||
|
|
||||||
|
#include "hpl_gclk_config.h"
|
||||||
|
|
||||||
|
#include "shared-bindings/microcontroller/__init__.h"
|
||||||
|
|
||||||
|
#include "py/runtime.h"
|
||||||
|
|
||||||
|
bool gclk_enabled(uint8_t gclk) {
|
||||||
|
return GCLK->GENCTRL[gclk].bit.GENEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
void disable_gclk(uint8_t gclk) {
|
||||||
|
while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
|
||||||
|
GCLK->GENCTRL[gclk].bit.GENEN = false;
|
||||||
|
while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
|
||||||
|
GCLK->PCHCTRL[peripheral].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk);
|
||||||
|
while(GCLK->SYNCBUSY.reg != 0) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
|
||||||
|
GCLK->PCHCTRL[peripheral].reg = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_clock_generator(uint8_t gclk, uint32_t source, uint16_t divisor) {
|
||||||
|
GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_DIV(divisor) | GCLK_GENCTRL_GENEN;
|
||||||
|
while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
void disable_clock_generator(uint8_t gclk) {
|
||||||
|
GCLK->GENCTRL[gclk].reg = 0;
|
||||||
|
while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
bool clock_get_enabled(uint8_t type, uint8_t index) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool clock_get_parent(uint8_t type, uint8_t index, uint8_t *p_type, uint8_t *p_index) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t clock_get_frequency(uint8_t type, uint8_t index) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t clock_get_calibration(uint8_t type, uint8_t index) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int clock_set_calibration(uint8_t type, uint8_t index, uint32_t val) {
|
||||||
|
return -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
|
||||||
|
};
|
||||||
|
MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
|
||||||
|
|
@ -177,8 +177,14 @@ safe_mode_t port_init(void) {
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef SAMD21
|
||||||
|
hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
|
||||||
|
_pm_init();
|
||||||
|
clock_init();
|
||||||
|
#endif
|
||||||
|
#ifdef SAMD51
|
||||||
init_mcu();
|
init_mcu();
|
||||||
|
#endif
|
||||||
board_init();
|
board_init();
|
||||||
|
|
||||||
// Configure millisecond timer initialization.
|
// Configure millisecond timer initialization.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue