diff --git a/ports/stm32/modmachine.c b/ports/stm32/modmachine.c
index 5a499e3da6..8b2c4e2f61 100644
--- a/ports/stm32/modmachine.c
+++ b/ports/stm32/modmachine.c
@@ -59,6 +59,24 @@
 #define RCC_CSR_PORRSTF RCC_CSR_BORRSTF
 #endif
 
+#if defined(STM32H7)
+#define RCC_SR          RSR
+#define RCC_SR_IWDGRSTF RCC_RSR_IWDG1RSTF
+#define RCC_SR_WWDGRSTF RCC_RSR_WWDG1RSTF
+#define RCC_SR_PORRSTF  RCC_RSR_PORRSTF
+#define RCC_SR_BORRSTF  RCC_RSR_BORRSTF
+#define RCC_SR_PINRSTF  RCC_RSR_PINRSTF
+#define RCC_SR_RMVF     RCC_RSR_RMVF
+#else
+#define RCC_SR          CSR
+#define RCC_SR_IWDGRSTF RCC_CSR_IWDGRSTF
+#define RCC_SR_WWDGRSTF RCC_CSR_WWDGRSTF
+#define RCC_SR_PORRSTF  RCC_CSR_PORRSTF
+#define RCC_SR_BORRSTF  RCC_CSR_BORRSTF
+#define RCC_SR_PINRSTF  RCC_CSR_PINRSTF
+#define RCC_SR_RMVF     RCC_CSR_RMVF
+#endif
+
 #define PYB_RESET_SOFT      (0)
 #define PYB_RESET_POWER_ON  (1)
 #define PYB_RESET_HARD      (2)
@@ -80,15 +98,21 @@ void machine_init(void) {
         reset_cause = PYB_RESET_DEEPSLEEP;
         PWR->CR1 |= PWR_CR1_CSBF;
     } else
+    #elif defined(STM32H7)
+    if (PWR->CPUCR & PWR_CPUCR_SBF || PWR->CPUCR & PWR_CPUCR_STOPF) {
+        // came out of standby or stop mode
+        reset_cause = PYB_RESET_DEEPSLEEP;
+        PWR->CPUCR |= PWR_CPUCR_CSSF;
+    } else
     #endif
     {
         // get reset cause from RCC flags
-        uint32_t state = RCC->CSR;
-        if (state & RCC_CSR_IWDGRSTF || state & RCC_CSR_WWDGRSTF) {
+        uint32_t state = RCC->RCC_SR;
+        if (state & RCC_SR_IWDGRSTF || state & RCC_SR_WWDGRSTF) {
             reset_cause = PYB_RESET_WDT;
-        } else if (state & RCC_CSR_PORRSTF || state & RCC_CSR_BORRSTF) {
+        } else if (state & RCC_SR_PORRSTF || state & RCC_SR_BORRSTF) {
             reset_cause = PYB_RESET_POWER_ON;
-        } else if (state & RCC_CSR_PINRSTF) {
+        } else if (state & RCC_SR_PINRSTF) {
             reset_cause = PYB_RESET_HARD;
         } else {
             // default is soft reset
@@ -96,7 +120,7 @@ void machine_init(void) {
         }
     }
     // clear RCC reset flags
-    RCC->CSR |= RCC_CSR_RMVF;
+    RCC->RCC_SR |= RCC_SR_RMVF;
 }
 
 void machine_deinit(void) {
@@ -217,7 +241,7 @@ STATIC NORETURN mp_obj_t machine_bootloader(void) {
     HAL_MPU_Disable();
     #endif
 
-#if defined(MCU_SERIES_F7)
+#if defined(MCU_SERIES_F7) || defined(STM32H7)
     // arm-none-eabi-gcc 4.9.0 does not correctly inline this
     // MSP function, so we write it out explicitly here.
     //__set_MSP(*((uint32_t*) 0x1FF00000));
@@ -487,7 +511,11 @@ STATIC mp_obj_t machine_sleep(void) {
 
     // select PLL as system clock source
     MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
+    #if defined(STM32H7)
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) {
+    #else
     while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
+    #endif
     }
 
     #endif
@@ -526,6 +554,8 @@ STATIC mp_obj_t machine_deepsleep(void) {
     PWR->CSR2 &= ~(PWR_CSR2_EWUP6 | PWR_CSR2_EWUP5 | PWR_CSR2_EWUP4 | PWR_CSR2_EWUP3 | PWR_CSR2_EWUP2 | PWR_CSR2_EWUP1);
     // clear global wake-up flag
     PWR->CR2 |= PWR_CR2_CWUPF6 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF1;
+    #elif defined(STM32H7)
+    // TODO
     #else
     // clear global wake-up flag
     PWR->CR |= PWR_CR_CWUF;