stm32/board/NUCLEO_F746ZG: Enable Ethernet periph, lwip and ussl.
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c8c37ca407
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cfec054073
@ -75,3 +75,14 @@
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#define MICROPY_HW_USB_FS (1)
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#define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9)
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#define MICROPY_HW_USB_OTG_ID_PIN (pin_A10)
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// Ethernet via RMII
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#define MICROPY_HW_ETH_MDC (pin_C1)
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#define MICROPY_HW_ETH_MDIO (pin_A2)
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#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1)
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#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7)
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#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4)
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#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5)
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#define MICROPY_HW_ETH_RMII_TX_EN (pin_G11)
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#define MICROPY_HW_ETH_RMII_TXD0 (pin_G13)
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#define MICROPY_HW_ETH_RMII_TXD1 (pin_B13)
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@ -4,3 +4,8 @@ AF_FILE = boards/stm32f746_af.csv
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LD_FILES = boards/stm32f746.ld boards/common_ifs.ld
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TEXT0_ADDR = 0x08000000
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TEXT1_ADDR = 0x08020000
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# MicroPython settings
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MICROPY_PY_LWIP = 1
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MICROPY_PY_USSL = 1
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MICROPY_SSL_MBEDTLS = 1
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@ -66,3 +66,12 @@ UART6_RX,PG9
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SPI_B_NSS,PA4
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SPI_B_SCK,PB3
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SPI_B_MOSI,PB5
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ETH_MDC,PC1
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ETH_MDIO,PA2
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ETH_RMII_REF_CLK,PA1
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ETH_RMII_CRS_DV,PA7
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ETH_RMII_RXD0,PC4
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ETH_RMII_RXD1,PC5
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ETH_RMII_TX_EN,PG11
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ETH_RMII_TXD0,PG13
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ETH_RMII_TXD1,PB13
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