From cb7e133dbe0e13333534a21fc11bbf6a800ac4a2 Mon Sep 17 00:00:00 2001 From: "Kwabena W. Agyeman" Date: Tue, 25 Jul 2023 18:20:37 -0700 Subject: [PATCH] mimxrt/boards: Add support for GPIO control of SNVS pins. Signed-off-by: "Kwabena W. Agyeman" --- ports/mimxrt/boards/MIMXRT1062_af.csv | 3 ++ ports/mimxrt/boards/MIMXRT1176_af.csv | 20 ++++++------- ports/mimxrt/boards/make-pins.py | 42 ++++++++++++++++++++++++--- ports/mimxrt/boards/mimxrt_prefix.c | 14 +++++++++ 4 files changed, 65 insertions(+), 14 deletions(-) diff --git a/ports/mimxrt/boards/MIMXRT1062_af.csv b/ports/mimxrt/boards/MIMXRT1062_af.csv index 9b83efeddc..d2f0b22023 100644 --- a/ports/mimxrt/boards/MIMXRT1062_af.csv +++ b/ports/mimxrt/boards/MIMXRT1062_af.csv @@ -123,3 +123,6 @@ GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,LPUART7_TXD,SAI1_TX_BCLK,LPSPI2_SOUT, GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA1,LPUART7_RXD,SAI1_TX_SYNC,LPSPI2_SIN,GPIO3_IO09,,,,,,,ALT5 GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA2,LPUART2_RXD,LPI2C2_SDA,LPSPI2_PCS2,GPIO3_IO10,,,,,,,ALT5 GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_DATA3,LPUART2_TXD,LPI2C2_SCL,LPSPI2_PCS3,GPIO3_IO11,,,,,,,ALT5 +WAKEUP,,,,,,GPIO5_IO00,,NMI,,,,,ALT5 +PMIC_ON_REQ,SNVS_PMIC_ON_REQ,,,,,GPIO5_IO01,,,,,,,ALT0 +PMIC_STBY_REQ,CCM_PMIC_STBY_REQ,,,,,GPIO5_IO02,,,,,,,ALT0 diff --git a/ports/mimxrt/boards/MIMXRT1176_af.csv b/ports/mimxrt/boards/MIMXRT1176_af.csv index fe31f502e4..21fd2a2417 100644 --- a/ports/mimxrt/boards/MIMXRT1176_af.csv +++ b/ports/mimxrt/boards/MIMXRT1176_af.csv @@ -80,16 +80,16 @@ GPIO_EMC_B2_17,SEMC_DM03,XBAR1_INOUT15,ENET_1G_RX_EN,SAI3_MCLK,FLEXSPI2_A_DATA04 GPIO_EMC_B2_18,SEMC_DQS4,XBAR1_INOUT16,ENET_1G_RX_ER,EWM_OUT_B,FLEXSPI2_A_DATA05,GPIO2_IO28,FLEXSPI1_A_DQS,,WDOG1_B,TMR3_TIMER1,GPIO8_IO28,,, GPIO_EMC_B2_19,SEMC_CLKX00,ENET_MDC,ENET_1G_MDC,ENET_1G_REF_CLK,FLEXSPI2_A_DATA06,GPIO2_IO29,,,ENET_QOS_MDC,TMR3_TIMER2,GPIO8_IO29,,, GPIO_EMC_B2_20,SEMC_CLKX01,ENET_MDIO,ENET_1G_MDIO,ENET_QOS_REF_CLK,FLEXSPI2_A_DATA07,GPIO2_IO30,,,ENET_QOS_MDIO,TMR3_TIMER3,GPIO8_IO30,,, -GPIO_SNVS_00,SNVS_TAMPER0,,,,,GPIO13_IO03,,,,,,,, -GPIO_SNVS_01,SNVS_TAMPER1,,,,,GPIO13_IO04,,,,,,,, -GPIO_SNVS_02,SNVS_TAMPER2,,,,,GPIO13_IO05,,,,,,,, -GPIO_SNVS_03,SNVS_TAMPER3,,,,,GPIO13_IO06,,,,,,,, -GPIO_SNVS_04,SNVS_TAMPER4,,,,,GPIO13_IO07,,,,,,,, -GPIO_SNVS_05,SNVS_TAMPER5,,,,,GPIO13_IO08,,,,,,,, -GPIO_SNVS_06,SNVS_TAMPER6,,,,,GPIO13_IO09,,,,,,,, -GPIO_SNVS_07,SNVS_TAMPER7,,,,,GPIO13_IO10,,,,,,,, -GPIO_SNVS_08,SNVS_TAMPER8,,,,,GPIO13_IO11,,,,,,,, -GPIO_SNVS_09,SNVS_TAMPER9,,,,,GPIO13_IO12,,,,,,,, +GPIO_SNVS_00_DIG,SNVS_TAMPER0,,,,,GPIO13_IO03,,,,,,,, +GPIO_SNVS_01_DIG,SNVS_TAMPER1,,,,,GPIO13_IO04,,,,,,,, +GPIO_SNVS_02_DIG,SNVS_TAMPER2,,,,,GPIO13_IO05,,,,,,,, +GPIO_SNVS_03_DIG,SNVS_TAMPER3,,,,,GPIO13_IO06,,,,,,,, +GPIO_SNVS_04_DIG,SNVS_TAMPER4,,,,,GPIO13_IO07,,,,,,,, +GPIO_SNVS_05_DIG,SNVS_TAMPER5,,,,,GPIO13_IO08,,,,,,,, +GPIO_SNVS_06_DIG,SNVS_TAMPER6,,,,,GPIO13_IO09,,,,,,,, +GPIO_SNVS_07_DIG,SNVS_TAMPER7,,,,,GPIO13_IO10,,,,,,,, +GPIO_SNVS_08_DIG,SNVS_TAMPER8,,,,,GPIO13_IO11,,,,,,,, +GPIO_SNVS_09_DIG,SNVS_TAMPER9,,,,,GPIO13_IO12,,,,,,,, GPIO_LPSR_00,FLEXCAN3_TX,MIC_CLK,MQS_RIGHT,ARM_CM4_EVENTO,,GPIO6_IO00,LPUART12_TXD,SAI4_MCLK,,,GPIO12_IO00,,, GPIO_LPSR_01,FLEXCAN3_RX,MIC_BITSTREAM0,MQS_LEFT,ARM_CM4_EVENTI,,GPIO6_IO01,LPUART12_RXD,,,,GPIO12_IO01,,, GPIO_LPSR_02,SRC_BOOT_MODE00,LPSPI5_SCK,SAI4_TX_DATA,MQS_RIGHT,,GPIO6_IO02,,,,,GPIO12_IO02,,, diff --git a/ports/mimxrt/boards/make-pins.py b/ports/mimxrt/boards/make-pins.py index 429d648696..51ae9eb717 100644 --- a/ports/mimxrt/boards/make-pins.py +++ b/ports/mimxrt/boards/make-pins.py @@ -24,6 +24,10 @@ regexes = [ r"IOMUXC_(?PGPIO_EMC_B\d_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", r"IOMUXC_(?PGPIO_DISP_B\d_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", r"IOMUXC_(?PGPIO_LPSR_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_[SNVS_]*(?PWAKEUP[_DIG]*)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_SNVS_(?PPMIC_ON_REQ)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_SNVS_(?PPMIC_STBY_REQ)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_(?PGPIO_SNVS_\d\d_DIG)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", ] @@ -118,10 +122,43 @@ class Pin(object): self.print_pin_af() self.print_pin_adc() + options = { + "GPIO_LPSR_00": "PIN_LPSR", + "GPIO_LPSR_01": "PIN_LPSR", + "GPIO_LPSR_02": "PIN_LPSR", + "GPIO_LPSR_03": "PIN_LPSR", + "GPIO_LPSR_04": "PIN_LPSR", + "GPIO_LPSR_05": "PIN_LPSR", + "GPIO_LPSR_06": "PIN_LPSR", + "GPIO_LPSR_07": "PIN_LPSR", + "GPIO_LPSR_08": "PIN_LPSR", + "GPIO_LPSR_09": "PIN_LPSR", + "GPIO_LPSR_10": "PIN_LPSR", + "GPIO_LPSR_11": "PIN_LPSR", + "GPIO_LPSR_12": "PIN_LPSR", + "GPIO_LPSR_13": "PIN_LPSR", + "GPIO_LPSR_14": "PIN_LPSR", + "GPIO_LPSR_15": "PIN_LPSR", + "GPIO_SNVS_00_DIG": "PIN_SNVS", + "GPIO_SNVS_01_DIG": "PIN_SNVS", + "GPIO_SNVS_02_DIG": "PIN_SNVS", + "GPIO_SNVS_03_DIG": "PIN_SNVS", + "GPIO_SNVS_04_DIG": "PIN_SNVS", + "GPIO_SNVS_05_DIG": "PIN_SNVS", + "GPIO_SNVS_06_DIG": "PIN_SNVS", + "GPIO_SNVS_07_DIG": "PIN_SNVS", + "GPIO_SNVS_08_DIG": "PIN_SNVS", + "GPIO_SNVS_09_DIG": "PIN_SNVS", + "WAKEUP": "PIN_SNVS", + "WAKEUP_DIG": "PIN_SNVS", + "PMIC_ON_REQ": "PIN_SNVS", + "PMIC_STBY_REQ": "PIN_SNVS", + } + print( "const machine_pin_obj_t pin_{0} = {1}({0}, {2}, {3}, pin_{0}_af, {4}, {5});\n".format( self.name, - "PIN_LPSR" if "LPSR" in self.name else "PIN", + options.get(self.name, "PIN"), self.gpio, int(self.pin), len(self.adc_fns), @@ -233,9 +270,6 @@ class Pins(object): pin_number = pin.lstrip("IO") pin = Pin(pad, gpio, pin_number, idx=idx) - if any(s in pad for s in ("SNVS", "WAKEUP")): - continue - # Parse alternate functions af_idx = 0 for af_idx, af in enumerate(row[(pad_col + 1) : adc_col]): diff --git a/ports/mimxrt/boards/mimxrt_prefix.c b/ports/mimxrt/boards/mimxrt_prefix.c index 09c0aa109e..d7a2bcfc80 100644 --- a/ports/mimxrt/boards/mimxrt_prefix.c +++ b/ports/mimxrt/boards/mimxrt_prefix.c @@ -49,3 +49,17 @@ .adc_list = (_adc_list), \ } \ +#define PIN_SNVS(_name, _gpio, _pin, _af_list, _adc_list_len, _adc_list) \ + { \ + .base = { &machine_pin_type }, \ + .name = MP_QSTR_##_name, \ + .gpio = (_gpio), \ + .pin = (uint32_t)(_pin), \ + .muxRegister = (uint32_t)&(IOMUXC_SNVS->SW_MUX_CTL_PAD_##_name), \ + .configRegister = (uint32_t)&(IOMUXC_SNVS->SW_PAD_CTL_PAD_##_name), \ + .af_list_len = (uint8_t)(sizeof((_af_list)) / sizeof(machine_pin_af_obj_t)), \ + .adc_list_len = (_adc_list_len), \ + .af_list = (_af_list), \ + .adc_list = (_adc_list), \ + } \ +