stm32/boards/STM32F769DISC: Fix number of SDRAM row bits.
According to the schematic, the SDRAM part on this board is a MT48LC4M32B2B5-6A, with "Row addressing 4K A[11:0]" (per datasheet). This commit updates mpconfigboard.h from 13 to 12 to match.
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@ -100,7 +100,14 @@ void board_early_init(void);
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#define MICROPY_HW_ETH_RMII_TXD1 (pin_G14)
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#if 0
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// Optional SDRAM configuration; requires SYSCLK <= 200MHz
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// Optional SDRAM configuration.
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// Note: This requires SYSCLK <= 200MHz. 192MHz example below:
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// #define MICROPY_HW_CLK_PLLM (25)
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// #define MICROPY_HW_CLK_PLLN (384)
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// #define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
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// #define MICROPY_HW_CLK_PLLQ (8)
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#define MICROPY_HW_SDRAM_SIZE (128 * 1024 * 1024 / 8) // 128 Mbit
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#define MICROPY_HW_SDRAM_STARTUP_TEST (0)
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#define MICROPY_HEAP_START sdram_start()
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@ -119,7 +126,7 @@ void board_early_init(void);
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#define MICROPY_HW_SDRAM_BURST_LENGTH 1
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#define MICROPY_HW_SDRAM_CAS_LATENCY 2
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#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM 8
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#define MICROPY_HW_SDRAM_ROW_BITS_NUM 13
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#define MICROPY_HW_SDRAM_ROW_BITS_NUM 12
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#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH 32
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#define MICROPY_HW_SDRAM_INTERN_BANKS_NUM 4
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#define MICROPY_HW_SDRAM_CLOCK_PERIOD 2
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