stmhal: Adjust computation of SYSCLK to retain precision.
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@ -972,7 +972,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
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if (__RCC_PLLSRC() != 0)
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if (__RCC_PLLSRC() != 0)
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{
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{
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/* HSE used as PLL clock source */
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/* HSE used as PLL clock source */
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pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
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//pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
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// dpgeorge: Adjust the way the arithmetic is done so it retains
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// precision for the case that pllm doesn't evenly divide HSE_VALUE.
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// Must be sure not to overflow, so divide by 4 first. HSE_VALUE
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// should be a multiple of 4 (being a multiple of 100 is enough).
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pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
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}
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}
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else
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else
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{
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{
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