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stmhal: Adjust computation of SYSCLK to retain precision.

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This commit is contained in:
Damien George 2014-10-04 01:54:02 +01:00
parent 1f2558d647
commit c568a2b443
1 changed files with 6 additions and 1 deletions
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7
stmhal/hal/src/stm32f4xx_hal_rcc.c
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@ -972,7 +972,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
if (__RCC_PLLSRC() != 0) if (__RCC_PLLSRC() != 0)
{ {
/* HSE used as PLL clock source */ /* HSE used as PLL clock source */
pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
// dpgeorge: Adjust the way the arithmetic is done so it retains
// precision for the case that pllm doesn't evenly divide HSE_VALUE.
// Must be sure not to overflow, so divide by 4 first. HSE_VALUE
// should be a multiple of 4 (being a multiple of 100 is enough).
pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
} }
else else
{ {