update ulp implementation

This commit is contained in:
MicroDev 2023-03-02 15:38:58 +05:30 committed by Scott Shawcroft
parent 242a720593
commit c38972b51c
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GPG Key ID: 0DFD512649C052DA
6 changed files with 44 additions and 23 deletions

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@ -104,7 +104,7 @@ INC += \
-isystem esp-idf/components/soc/include \
-isystem esp-idf/components/soc/$(IDF_TARGET)/include \
-isystem esp-idf/components/spi_flash/include \
-isystem esp-idf/components/ulp/include \
-isystem esp-idf/components/ulp/ulp_fsm/include \
-isystem esp-idf/components/ulp/ulp_riscv/include \
-isystem esp-idf/components/ulp/ulp_common/include \
-isystem esp-idf/components/ulp/ulp_common/include/$(IDF_TARGET) \

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@ -90,12 +90,14 @@ void common_hal_espulp_ulp_run(espulp_ulp_obj_t *self, uint32_t *program, size_t
ulp_set_wakeup_period(0, 20000);
switch (self->arch) {
#ifdef CONFIG_ULP_COPROC_TYPE_FSM
case FSM:
ulp_load_binary(0, (const uint8_t *)program, length);
ulp_run(0);
break;
#endif
#ifdef CONFIG_ULP_COPROC_TYPE_RISCV
case RISCV:
#ifndef CONFIG_IDF_TARGET_ESP32
ulp_riscv_load_binary((const uint8_t *)program, length);
ulp_riscv_run();
break;
@ -107,12 +109,23 @@ void common_hal_espulp_ulp_run(espulp_ulp_obj_t *self, uint32_t *program, size_t
}
void common_hal_espulp_ulp_halt(espulp_ulp_obj_t *self) {
#ifdef CONFIG_IDF_TARGET_ESP32
mp_raise_NotImplementedError(NULL);
#else
switch (self->arch) {
/*
#ifdef CONFIG_ULP_COPROC_TYPE_FSM
case FSM:
break;
#endif
*/
#ifdef CONFIG_ULP_COPROC_TYPE_RISCV
case RISCV:
ulp_riscv_timer_stop();
ulp_riscv_halt();
break;
#endif
default:
mp_raise_NotImplementedError(NULL);
break;
}
// Release pins we were using.
for (uint8_t i = 0; i < 32; i++) {
@ -130,11 +143,19 @@ void common_hal_espulp_ulp_construct(espulp_ulp_obj_t *self, espulp_architecture
mp_raise_ValueError_varg(translate("%q in use"), MP_QSTR_ULP);
}
#ifdef CONFIG_IDF_TARGET_ESP32
if (self->arch == RISCV) {
mp_raise_NotImplementedError(NULL);
}
switch (self->arch) {
#ifdef CONFIG_ULP_COPROC_TYPE_FSM
case FSM:
break;
#endif
#ifdef CONFIG_ULP_COPROC_TYPE_RISCV
case RISCV:
break;
#endif
default:
mp_raise_NotImplementedError(NULL);
break;
}
self->arch = arch;
self->inited = true;

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@ -81,17 +81,19 @@ void espulp_ulpalarm_set_alarm(const bool deep_sleep, const size_t n_alarms, con
// enable ulp interrupt
switch (alarm->ulp->arch) {
#ifdef CONFIG_ULP_COPROC_TYPE_FSM
case FSM:
#ifdef CONFIG_IDF_TARGET_ESP32
rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_ULP_CP_INT_RAW);
rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_ULP_CP_INT_RAW, 0);
#else
rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_ULP_CP_INT_ST);
rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_ULP_CP_INT_ST, 0);
#endif
REG_SET_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_ULP_CP_INT_ENA);
break;
#endif
#ifdef CONFIG_ULP_COPROC_TYPE_RISCV
case RISCV:
#ifndef CONFIG_IDF_TARGET_ESP32
rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_COCPU_INT_ST);
rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_COCPU_INT_ST, 0);
REG_SET_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_COCPU_INT_ENA);
break;
#endif
@ -110,8 +112,10 @@ void espulp_ulpalarm_prepare_for_deep_sleep(void) {
// disable ulp interrupt
rtc_isr_deregister(&ulp_interrupt, NULL);
#ifdef CONFIG_ULP_COPROC_TYPE_FSM
REG_CLR_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_ULP_CP_INT_ENA);
#ifndef CONFIG_IDF_TARGET_ESP32
#endif
#ifdef CONFIG_ULP_COPROC_TYPE_RISCV
REG_CLR_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_COCPU_INT_ENA);
#endif

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@ -7,5 +7,4 @@ CONFIG_ESP32S2_DATA_CACHE_16KB=y
CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_TYPE_RISCV=y
CONFIG_ULP_COPROC_RESERVE_MEM=8176

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@ -8,5 +8,4 @@ CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1=y
CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM=y
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_TYPE_RISCV=y
CONFIG_ULP_COPROC_RESERVE_MEM=8176

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@ -48,8 +48,6 @@ CIRCUITPY_WIFI ?= 1
ifeq ($(IDF_TARGET),esp32)
# Modules
CIRCUITPY_BLEIO = 0
CIRCUITPY_ESPULP = 0
CIRCUITPY_MEMORYMAP = 0
CIRCUITPY_PARALLELDISPLAY = 0
CIRCUITPY_RGBMATRIX = 0
# Features