update ulp implementation

ports/espressif/Makefile

@@ -104,7 +104,7 @@ INC += \
 	-isystem esp-idf/components/soc/include \
 	-isystem esp-idf/components/soc/$(IDF_TARGET)/include \
 	-isystem esp-idf/components/spi_flash/include \
-	-isystem esp-idf/components/ulp/include \
+	-isystem esp-idf/components/ulp/ulp_fsm/include \
 	-isystem esp-idf/components/ulp/ulp_riscv/include \
 	-isystem esp-idf/components/ulp/ulp_common/include \
 	-isystem esp-idf/components/ulp/ulp_common/include/$(IDF_TARGET) \

ports/espressif/common-hal/espulp/ULP.c

@@ -90,16 +90,18 @@ void common_hal_espulp_ulp_run(espulp_ulp_obj_t *self, uint32_t *program, size_t
     ulp_set_wakeup_period(0, 20000);
 
     switch (self->arch) {
+        #ifdef CONFIG_ULP_COPROC_TYPE_FSM
         case FSM:
             ulp_load_binary(0, (const uint8_t *)program, length);
             ulp_run(0);
             break;
+        #endif
+        #ifdef CONFIG_ULP_COPROC_TYPE_RISCV
         case RISCV:
-            #ifndef CONFIG_IDF_TARGET_ESP32
             ulp_riscv_load_binary((const uint8_t *)program, length);
             ulp_riscv_run();
             break;
-            #endif
+        #endif
         default:
             mp_raise_NotImplementedError(NULL);
             break;
@@ -107,12 +109,23 @@ void common_hal_espulp_ulp_run(espulp_ulp_obj_t *self, uint32_t *program, size_t
 }
 
 void common_hal_espulp_ulp_halt(espulp_ulp_obj_t *self) {
-    #ifdef CONFIG_IDF_TARGET_ESP32
+    switch (self->arch) {
-    mp_raise_NotImplementedError(NULL);
+        /*
-    #else
+        #ifdef CONFIG_ULP_COPROC_TYPE_FSM
-    ulp_riscv_timer_stop();
+        case FSM:
-    ulp_riscv_halt();
+            break;
-    #endif
+        #endif
+        */
+        #ifdef CONFIG_ULP_COPROC_TYPE_RISCV
+        case RISCV:
+            ulp_riscv_timer_stop();
+            ulp_riscv_halt();
+            break;
+        #endif
+        default:
+            mp_raise_NotImplementedError(NULL);
+            break;
+    }
 
     // Release pins we were using.
     for (uint8_t i = 0; i < 32; i++) {
@@ -130,11 +143,19 @@ void common_hal_espulp_ulp_construct(espulp_ulp_obj_t *self, espulp_architecture
         mp_raise_ValueError_varg(translate("%q in use"), MP_QSTR_ULP);
     }
 
-    #ifdef CONFIG_IDF_TARGET_ESP32
+    switch (self->arch) {
-    if (self->arch == RISCV) {
+        #ifdef CONFIG_ULP_COPROC_TYPE_FSM
-        mp_raise_NotImplementedError(NULL);
+        case FSM:
+            break;
+        #endif
+        #ifdef CONFIG_ULP_COPROC_TYPE_RISCV
+        case RISCV:
+            break;
+        #endif
+        default:
+            mp_raise_NotImplementedError(NULL);
+            break;
     }
-    #endif
 
     self->arch = arch;
     self->inited = true;

ports/espressif/common-hal/espulp/ULPAlarm.c

@@ -81,20 +81,22 @@ void espulp_ulpalarm_set_alarm(const bool deep_sleep, const size_t n_alarms, con
 
     // enable ulp interrupt
     switch (alarm->ulp->arch) {
+        #ifdef CONFIG_ULP_COPROC_TYPE_FSM
         case FSM:
             #ifdef CONFIG_IDF_TARGET_ESP32
-            rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_ULP_CP_INT_RAW);
+            rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_ULP_CP_INT_RAW, 0);
             #else
-            rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_ULP_CP_INT_ST);
+            rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_ULP_CP_INT_ST, 0);
             #endif
             REG_SET_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_ULP_CP_INT_ENA);
             break;
+        #endif
+        #ifdef CONFIG_ULP_COPROC_TYPE_RISCV
         case RISCV:
-            #ifndef CONFIG_IDF_TARGET_ESP32
+            rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_COCPU_INT_ST, 0);
-            rtc_isr_register(&ulp_interrupt, NULL, RTC_CNTL_COCPU_INT_ST);
             REG_SET_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_COCPU_INT_ENA);
             break;
-            #endif
+        #endif
         default:
             mp_raise_NotImplementedError(NULL);
             break;
@@ -110,8 +112,10 @@ void espulp_ulpalarm_prepare_for_deep_sleep(void) {
 
     // disable ulp interrupt
     rtc_isr_deregister(&ulp_interrupt, NULL);
+    #ifdef CONFIG_ULP_COPROC_TYPE_FSM
     REG_CLR_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_ULP_CP_INT_ENA);
-    #ifndef CONFIG_IDF_TARGET_ESP32
+    #endif
+    #ifdef CONFIG_ULP_COPROC_TYPE_RISCV
     REG_CLR_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_COCPU_INT_ENA);
     #endif
 

ports/espressif/esp-idf-config/sdkconfig-esp32s2.defaults

@@ -7,5 +7,4 @@ CONFIG_ESP32S2_DATA_CACHE_16KB=y
 CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y
 
 CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_TYPE_RISCV=y
 CONFIG_ULP_COPROC_RESERVE_MEM=8176

ports/espressif/esp-idf-config/sdkconfig-esp32s3.defaults

@@ -8,5 +8,4 @@ CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1=y
 CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM=y
 
 CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_TYPE_RISCV=y
 CONFIG_ULP_COPROC_RESERVE_MEM=8176

ports/espressif/mpconfigport.mk

@@ -48,8 +48,6 @@ CIRCUITPY_WIFI ?= 1
 ifeq ($(IDF_TARGET),esp32)
 # Modules
 CIRCUITPY_BLEIO = 0
-CIRCUITPY_ESPULP = 0
-CIRCUITPY_MEMORYMAP = 0
 CIRCUITPY_PARALLELDISPLAY = 0
 CIRCUITPY_RGBMATRIX = 0
 # Features