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212
.github/workflows/build.yml vendored
View File

@ -10,30 +10,32 @@ on:
jobs:
test:
runs-on: ubuntu-16.04
runs-on: ubuntu-18.04
steps:
- name: Dump GitHub context
env:
GITHUB_CONTEXT: ${{ toJson(github) }}
run: echo "$GITHUB_CONTEXT"
- name: Set up Python 3.5
- uses: actions/checkout@v2.2.0
with:
submodules: true
fetch-depth: 0
- run: git fetch --recurse-submodules=no https://github.com/adafruit/circuitpython refs/tags/*:refs/tags/*
- name: CircuitPython version
run: git describe --dirty --tags
- name: Set up Python 3.8
uses: actions/setup-python@v1
with:
python-version: 3.5
python-version: 3.8
- name: Install deps
run: |
sudo apt-get install -y eatmydata
sudo eatmydata apt-get install -y gettext librsvg2-bin mingw-w64
pip install requests sh click setuptools cpp-coveralls Sphinx sphinx-rtd-theme recommonmark sphinxcontrib-svg2pdfconverter polib pyyaml
pip install requests sh click setuptools cpp-coveralls "Sphinx<4" sphinx-rtd-theme recommonmark sphinx-autoapi sphinxcontrib-svg2pdfconverter polib pyyaml astroid
- name: Versions
run: |
gcc --version
python3 --version
- uses: actions/checkout@v1
with:
submodules: true
- name: CircuitPython version
run: git describe --dirty --always --tags
- name: Build mpy-cross
run: make -C mpy-cross -j2
- name: Build unix port
@ -42,7 +44,7 @@ jobs:
make -C ports/unix -j2
make -C ports/unix coverage -j2
- name: Test all
run: MICROPY_CPYTHON3=python3.5 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests -j1
run: MICROPY_CPYTHON3=python3.8 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests -j1
working-directory: tests
- name: Print failure info
run: |
@ -54,19 +56,28 @@ jobs:
working-directory: tests
if: failure()
- name: Native Tests
run: MICROPY_CPYTHON3=python3.5 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests -j1 --emit native
run: MICROPY_CPYTHON3=python3.8 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests -j1 --emit native
working-directory: tests
- name: mpy Tests
run: MICROPY_CPYTHON3=python3.5 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests -j1 --via-mpy -d basics float
run: MICROPY_CPYTHON3=python3.8 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests -j1 --via-mpy -d basics float
working-directory: tests
- name: Stubs
run: make stubs -j2
- uses: actions/upload-artifact@v2
with:
name: stubs
path: circuitpython-stubs*
- name: Docs
run: sphinx-build -E -W -b html . _build/html
- uses: actions/upload-artifact@v2
with:
name: docs
path: _build/html
- name: Translations
run: make check-translate
- name: New boards check
run: python3 -u ci_new_boards_check.py
working-directory: tools
- name: Build mpy-cross.static-raspbian
run: make -C mpy-cross -j2 -f Makefile.static-raspbian
- uses: actions/upload-artifact@v1.0.0
@ -89,25 +100,28 @@ jobs:
path: mpy-cross/mpy-cross.static.exe
mpy-cross-mac:
runs-on: macos-latest
runs-on: macos-10.15
steps:
- name: Dump GitHub context
env:
GITHUB_CONTEXT: ${{ toJson(github) }}
run: echo "$GITHUB_CONTEXT"
- name: Install deps
- name: Make gettext programs available
run: |
brew link --force gettext
brew install gettext
echo "::set-env name=PATH::/usr/local/opt/gettext/bin:$PATH"
- name: Versions
run: |
gcc --version
python3 --version
msgfmt --version
- uses: actions/checkout@v1
- uses: actions/checkout@v2.2.0
with:
submodules: true
fetch-depth: 0
- run: git fetch --recurse-submodules=no https://github.com/adafruit/circuitpython refs/tags/*:refs/tags/*
- name: CircuitPython version
run: git describe --dirty --always --tags
run: git describe --dirty --tags
- name: Build mpy-cross
run: make -C mpy-cross -j2
- uses: actions/upload-artifact@v1.0.0
@ -116,12 +130,15 @@ jobs:
path: mpy-cross/mpy-cross
build-arm:
runs-on: ubuntu-16.04
runs-on: ubuntu-18.04
needs: test
strategy:
fail-fast: false
matrix:
board:
- "8086_commander"
- "TG-Watch02A"
- "aloriumtech_evo_m51"
- "aramcon_badge_2019"
- "arduino_mkr1300"
- "arduino_mkrzero"
@ -129,6 +146,7 @@ jobs:
- "arduino_nano_33_iot"
- "arduino_zero"
- "bast_pro_mini_m0"
- "bdmicro_vina_m0"
- "capablerobot_usbhub"
- "catwan_usbstick"
- "circuitbrains_basic_m0"
@ -164,10 +182,12 @@ jobs:
- "feather_nrf52840_express"
- "feather_radiofruit_zigbee"
- "feather_stm32f405_express"
- "fluff_m0"
- "gemma_m0"
- "grandcentral_m4_express"
- "hallowing_m0_express"
- "hallowing_m4_express"
- "hiibot_bluefi"
- "imxrt1010_evk"
- "imxrt1020_evk"
- "imxrt1060_evk"
@ -175,6 +195,7 @@ jobs:
- "itsybitsy_m4_express"
- "itsybitsy_nrf52840_express"
- "kicksat-sprite"
- "loc_ber_m4_base_board"
- "makerdiary_nrf52840_mdk"
- "makerdiary_nrf52840_mdk_usb_dongle"
- "meowbit_v121"
@ -186,21 +207,30 @@ jobs:
- "mini_sam_m4"
- "monster_m4sk"
- "ndgarage_ndbit6"
- "nfc_copy_cat"
- "nice_nano"
- "nucleo_f746zg"
- "nucleo_f767zi"
- "nucleo_h743zi_2"
- "ohs2020_badge"
- "openbook_m4"
- "openmv_h7"
- "particle_argon"
- "particle_boron"
- "particle_xenon"
- "pca10056"
- "pca10059"
- "pca10100"
- "pewpew10"
- "pewpew_m4"
- "pirkey_m0"
- "pitaya_go"
- "pyb_nano_v2"
- "pybadge"
- "pybadge_airlift"
- "pyboard_v11"
- "pycubed"
- "pycubed_mram"
- "pygamer"
- "pygamer_advance"
- "pyportal"
@ -208,9 +238,12 @@ jobs:
- "pyruler"
- "robohatmm1_m4"
- "sam32"
- "same54_xplained"
- "seeeduino_wio_terminal"
- "seeeduino_xiao"
- "serpente"
- "shirtty"
- "simmel"
- "snekboard"
- "sparkfun_lumidrive"
- "sparkfun_nrf52840_mini"
@ -225,23 +258,28 @@ jobs:
- "stm32f411ve_discovery"
- "stm32f412zg_discovery"
- "stm32f4_discovery"
- "stm32f746g_discovery"
- "stringcar_m0_express"
- "teensy40"
- "teensy41"
- "teknikio_bluebird"
- "thunderpack"
- "trellis_m4_express"
- "trinket_m0"
- "trinket_m0_haxpress"
- "uartlogger2"
- "uchip"
- "ugame10"
- "winterbloom_big_honking_button"
- "winterbloom_sol"
- "xinabox_cc03"
- "xinabox_cs11"
steps:
- name: Set up Python 3.5
- name: Set up Python 3.8
uses: actions/setup-python@v1
with:
python-version: 3.5
python-version: 3.8
- name: Install deps
run: |
sudo apt-get install -y gettext
@ -253,9 +291,11 @@ jobs:
gcc --version
arm-none-eabi-gcc --version
python3 --version
- uses: actions/checkout@v1
- uses: actions/checkout@v2.2.0
with:
submodules: true
fetch-depth: 0
- run: git fetch --recurse-submodules=no https://github.com/adafruit/circuitpython refs/tags/*:refs/tags/*
- name: mpy-cross
run: make -C mpy-cross -j2
- name: build
@ -273,3 +313,131 @@ jobs:
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }}
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
if: github.event_name == 'push' || (github.event_name == 'release' && (github.event.action == 'published' || github.event.action == 'rerequested'))
build-riscv:
runs-on: ubuntu-18.04
needs: test
strategy:
fail-fast: false
matrix:
board:
- "fomu"
steps:
- name: Set up Python 3.8
uses: actions/setup-python@v1
with:
python-version: 3.8
- name: Install deps
run: |
sudo apt-get install -y gettext
pip install requests sh click setuptools awscli
wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-centos6.tar.gz
sudo tar -C /usr --strip-components=1 -xaf riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-centos6.tar.gz
- name: Versions
run: |
gcc --version
riscv64-unknown-elf-gcc --version
python3 --version
- uses: actions/checkout@v2.2.0
with:
submodules: true
fetch-depth: 0
- run: git fetch --recurse-submodules=no https://github.com/adafruit/circuitpython refs/tags/*:refs/tags/*
- name: mpy-cross
run: make -C mpy-cross -j2
- name: build
run: python3 -u build_release_files.py
working-directory: tools
env:
BOARDS: ${{ matrix.board }}
- uses: actions/upload-artifact@v1.0.0
with:
name: ${{ matrix.board }}
path: bin/${{ matrix.board }}
- name: Upload to S3
run: "[ -z \"$AWS_ACCESS_KEY_ID\" ] || aws s3 cp bin/ s3://adafruit-circuit-python/bin/ --recursive --no-progress --region us-east-1"
env:
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }}
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
if: github.event_name == 'push' || (github.event_name == 'release' && (github.event.action == 'published' || github.event.action == 'rerequested'))
build-xtensa:
runs-on: ubuntu-latest
needs: test
strategy:
fail-fast: false
matrix:
board:
- "espressif_saola_1_wroom"
- "espressif_saola_1_wrover"
- "unexpectedmaker_feathers2"
steps:
- name: Set up Python 3.8
uses: actions/setup-python@v1
with:
python-version: 3.8
- uses: actions/checkout@v2.2.0
with:
submodules: true
fetch-depth: 0
- run: git fetch --recurse-submodules=no https://github.com/adafruit/circuitpython refs/tags/*:refs/tags/*
- name: CircuitPython version
run: git describe --dirty --tags
- uses: actions/cache@v1
name: Fetch IDF tool cache
id: idf-cache
with:
path: ${{ github.workspace }}/.idf_tools
key: ${{ runner.os }}-idf-tools-${{ hashFiles('.git/modules/ports/esp32s2/esp-idf/HEAD') }}-20200523
- name: Install IDF tools
run: |
$IDF_PATH/tools/idf_tools.py --non-interactive install required
$IDF_PATH/tools/idf_tools.py --non-interactive install cmake
$IDF_PATH/tools/idf_tools.py --non-interactive install-python-env
rm -rf $IDF_TOOLS_PATH/dist
env:
IDF_PATH: ${{ github.workspace }}/ports/esp32s2/esp-idf
IDF_TOOLS_PATH: ${{ github.workspace }}/.idf_tools
- name: Install CircuitPython deps
run: |
source $IDF_PATH/export.sh
pip install requests sh click setuptools awscli
sudo apt-get install -y gettext ninja-build
env:
IDF_PATH: ${{ github.workspace }}/ports/esp32s2/esp-idf
IDF_TOOLS_PATH: ${{ github.workspace }}/.idf_tools
- name: Versions
run: |
source $IDF_PATH/export.sh
gcc --version
xtensa-esp32s2-elf-gcc --version
python3 --version
ninja --version
cmake --version
shell: bash
env:
IDF_PATH: ${{ github.workspace }}/ports/esp32s2/esp-idf
IDF_TOOLS_PATH: ${{ github.workspace }}/.idf_tools
- name: mpy-cross
run: make -C mpy-cross -j2
- name: build
run: |
source $IDF_PATH/export.sh
python3 -u build_release_files.py
working-directory: tools
shell: bash
env:
IDF_PATH: ${{ github.workspace }}/ports/esp32s2/esp-idf
IDF_TOOLS_PATH: ${{ github.workspace }}/.idf_tools
BOARDS: ${{ matrix.board }}
- uses: actions/upload-artifact@v1.0.0
with:
name: ${{ matrix.board }}
path: bin/${{ matrix.board }}
- name: Upload to S3
run: "[ -z \"$AWS_ACCESS_KEY_ID\" ] || aws s3 cp bin/ s3://adafruit-circuit-python/bin/ --recursive --no-progress --region us-east-1"
env:
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }}
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
if: github.event_name == 'push' || (github.event_name == 'release' && (github.event.action == 'published' || github.event.action == 'rerequested'))

10
.github/workflows/create_website_pr.yml vendored
View File

@ -12,10 +12,10 @@ jobs:
env:
GITHUB_CONTEXT: ${{ toJson(github) }}
run: echo "$GITHUB_CONTEXT"
- name: Set up Python 3.5
- name: Set up Python 3.8
uses: actions/setup-python@v1
with:
python-version: 3.5
python-version: 3.8
- name: Install deps
run: |
pip install requests sh click
@ -23,11 +23,13 @@ jobs:
run: |
gcc --version
python3 --version
- uses: actions/checkout@v1
- uses: actions/checkout@v2.2.0
with:
submodules: true
fetch-depth: 0
- run: git fetch --recurse-submodules=no https://github.com/adafruit/circuitpython refs/tags/*:refs/tags/*
- name: CircuitPython version
run: git describe --dirty --always --tags
run: git describe --dirty --tags
- name: Website
run: python3 build_board_info.py
working-directory: tools

24
.github/workflows/pre-commit.yml vendored Normal file
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@ -0,0 +1,24 @@
# SPDX-FileCopyrightText: Copyright (c) 2019 Anthony Sottile
#
# SPDX-License-Identifier: MIT
name: pre-commit
on:
pull_request:
push:
branches: [main]
jobs:
pre-commit:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v1
- uses: actions/setup-python@v1
- name: set PY
run: echo "::set-env name=PY::$(python -c 'import hashlib, sys;print(hashlib.sha256(sys.version.encode()+sys.executable.encode()).hexdigest())')"
- uses: actions/cache@v1
with:
path: ~/.cache/pre-commit
key: pre-commit|${{ env.PY }}|${{ hashFiles('.pre-commit-config.yaml') }}
- uses: pre-commit/action@v1.1.0

3
.gitignore vendored
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@ -14,6 +14,7 @@
############
dist/
*.egg-info
.eggs
# Logs and Databases
######################
@ -51,6 +52,8 @@ _build
# Generated rst files
######################
genrst/
/autoapi/
/shared-bindings/**/*.rst
# ctags and similar
###################

37
.gitmodules vendored
View File

@ -29,10 +29,6 @@
[submodule "tools/python-semver"]
path = tools/python-semver
url = https://github.com/k-bx/python-semver.git
[submodule "lib/stm32lib"]
path = lib/stm32lib
url = https://github.com/micropython/stm32lib
branch = work-F4-1.13.1+F7-1.5.0+L4-1.3.0
[submodule "atmel-samd/asf4"]
path = ports/atmel-samd/asf4
url = https://github.com/adafruit/asf4.git
@ -96,9 +92,6 @@
[submodule "frozen/circuitpython-stage"]
path = frozen/circuitpython-stage
url = https://github.com/python-ugame/circuitpython-stage.git
[submodule "ports/stm32f4/stm32f4"]
path = ports/stm32f4/stm32f4
url = https://github.com/adafruit/stm32f4.git
[submodule "ports/cxd56/spresense-exported-sdk"]
path = ports/cxd56/spresense-exported-sdk
url = https://github.com/sonydevworld/spresense-exported-sdk.git
@ -114,9 +107,39 @@
[submodule "frozen/Adafruit_CircuitPython_Register"]
path = frozen/Adafruit_CircuitPython_Register
url = https://github.com/adafruit/Adafruit_CircuitPython_Register.git
[submodule "extmod/ulab"]
path = extmod/ulab
url = https://github.com/v923z/micropython-ulab
[submodule "frozen/Adafruit_CircuitPython_ESP32SPI"]
path = frozen/Adafruit_CircuitPython_ESP32SPI
url = https://github.com/adafruit/Adafruit_CircuitPython_ESP32SPI
[submodule "frozen/Adafruit_CircuitPython_Requests"]
path = frozen/Adafruit_CircuitPython_Requests
url = https://github.com/adafruit/Adafruit_CircuitPython_Requests
[submodule "ports/stm/st_driver"]
path = ports/stm/st_driver
url = https://github.com/hathach/st_driver.git
[submodule "lib/protomatter"]
path = lib/protomatter
url = https://github.com/adafruit/Adafruit_Protomatter
[submodule "frozen/Adafruit_CircuitPython_LSM6DS"]
path = frozen/Adafruit_CircuitPython_LSM6DS
url = https://github.com/adafruit/Adafruit_CircuitPython_LSM6DS
[submodule "frozen/Adafruit_CircuitPython_FocalTouch"]
path = frozen/Adafruit_CircuitPython_FocalTouch
url = https://github.com/adafruit/Adafruit_CircuitPython_FocalTouch
[submodule "frozen/Adafruit_CircuitPython_DS3231"]
path = frozen/Adafruit_CircuitPython_DS3231
url = https://github.com/adafruit/Adafruit_CircuitPython_DS3231
[submodule "frozen/Adafruit_CircuitPython_DRV2605"]
path = frozen/Adafruit_CircuitPython_DRV2605
url = https://github.com/adafruit/Adafruit_CircuitPython_DRV2605
[submodule "frozen/Adafruit_CircuitPython_BLE"]
path = frozen/Adafruit_CircuitPython_BLE
url = https://github.com/adafruit/Adafruit_CircuitPython_BLE
[submodule "frozen/Adafruit_CircuitPython_BLE_Apple_Notification_Center"]
path = frozen/Adafruit_CircuitPython_BLE_Apple_Notification_Center
url = https://github.com/adafruit/Adafruit_CircuitPython_BLE_Apple_Notification_Center
[submodule "ports/esp32s2/esp-idf"]
path = ports/esp32s2/esp-idf
url = https://github.com/tannewt/esp-idf.git

13
.pre-commit-config.yaml Normal file
View File

@ -0,0 +1,13 @@
# SPDX-FileCopyrightText: 2020 Diego Elio Pettenò
#
# SPDX-License-Identifier: Unlicense
repos:
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v2.3.0
hooks:
- id: check-yaml
- id: end-of-file-fixer
exclude: '^(tests/.*\.exp|tests/cmdline/.*|tests/.*/data/.*)'
- id: trailing-whitespace
exclude: '^(tests/.*\.exp|tests/cmdline/.*|tests/.*/data/.*)'

133
CODE_OF_CONDUCT.md
View File

@ -1,74 +1,135 @@
# Contributor Covenant Code of Conduct
<!--
SPDX-FileCopyrightText: 2014 Coraline Ada Ehmke
SPDX-FileCopyrightText: 2019 Kattni Rembor for Adafruit Industries
SPDX-License-Identifier: CC-BY-4.0
-->
# Adafruit Community Code of Conduct
## Our Pledge
In the interest of fostering an open and welcoming environment, we as
contributors and maintainers pledge to making participation in our project and
contributors and leaders pledge to making participation in our project and
our community a harassment-free experience for everyone, regardless of age, body
size, disability, ethnicity, gender identity and expression, level of experience,
nationality, personal appearance, race, religion, or sexual identity and
orientation.
size, disability, ethnicity, gender identity and expression, level or type of
experience, education, socio-economic status, nationality, personal appearance,
race, religion, or sexual identity and orientation.
## Our Standards
We are committed to providing a friendly, safe and welcoming environment for
all.
Examples of behavior that contributes to creating a positive environment
include:
* Be kind and courteous to others
* Using welcoming and inclusive language
* Being respectful of differing viewpoints and experiences
* Collaborating with other community members
* Gracefully accepting constructive criticism
* Focusing on what is best for the community
* Showing empathy towards other community members
Examples of unacceptable behavior by participants include:
* The use of sexualized language or imagery and unwelcome sexual attention or
advances
* The use of sexualized language or imagery and sexual attention or advances
* The use of inappropriate images, including in a community member's avatar
* The use of inappropriate language, including in a community member's nickname
* Any spamming, flaming, baiting or other attention-stealing behavior
* Excessive or unwelcome helping; answering outside the scope of the question
asked
* Trolling, insulting/derogatory comments, and personal or political attacks
* Promoting or spreading disinformation, lies, or conspiracy theories against
a person, group, organisation, project, or community
* Public or private harassment
* Publishing others' private information, such as a physical or electronic
address, without explicit permission
* Other conduct which could reasonably be considered inappropriate in a
professional setting
* Other conduct which could reasonably be considered inappropriate
The goal of the standards and moderation guidelines outlined here is to build
and maintain a respectful community. We ask that you don’t just aim to be
"technically unimpeachable", but rather try to be your best self.
We value many things beyond technical expertise, including collaboration and
supporting others within our community. Providing a positive experience for
other community members can have a much more significant impact than simply
providing the correct answer.
## Our Responsibilities
Project maintainers are responsible for clarifying the standards of acceptable
Project leaders are responsible for clarifying the standards of acceptable
behavior and are expected to take appropriate and fair corrective action in
response to any instances of unacceptable behavior.
Project maintainers have the right and responsibility to remove, edit, or
reject comments, commits, code, wiki edits, issues, and other contributions
Project leaders have the right and responsibility to remove, edit, or
reject messages, comments, commits, code, issues, and other contributions
that are not aligned to this Code of Conduct, or to ban temporarily or
permanently any contributor for other behaviors that they deem inappropriate,
threatening, offensive, or harmful.
permanently any community member for other behaviors that they deem
inappropriate, threatening, offensive, or harmful.
## Moderation
Instances of behaviors that violate the Adafruit Community Code of Conduct
may be reported by any member of the community. Community members are
encouraged to report these situations, including situations they witness
involving other community members.
You may report in the following ways:
In any situation, you may send an email to <support@adafruit.com>.
On the Adafruit Discord, you may send an open message from any channel
to all Community Moderators by tagging @community moderators. You may
also send an open message from any channel, or a direct message to
@kattni#1507, @tannewt#4653, @danh#1614, @cater#2442,
@sommersoft#0222, @Mr. Certainly#0472 or @Andon#8175.
Email and direct message reports will be kept confidential.
In situations on Discord where the issue is particularly egregious, possibly
illegal, requires immediate action, or violates the Discord terms of service,
you should also report the message directly to Discord.
These are the steps for upholding our community’s standards of conduct.
1. Any member of the community may report any situation that violates the
Adafruit Community Code of Conduct. All reports will be reviewed and
investigated.
2. If the behavior is an egregious violation, the community member who
committed the violation may be banned immediately, without warning.
3. Otherwise, moderators will first respond to such behavior with a warning.
4. Moderators follow a soft "three strikes" policy - the community member may
be given another chance, if they are receptive to the warning and change their
behavior.
5. If the community member is unreceptive or unreasonable when warned by a
moderator, or the warning goes unheeded, they may be banned for a first or
second offense. Repeated offenses will result in the community member being
banned.
## Scope
This Code of Conduct and the enforcement policies listed above apply to all
Adafruit Community venues. This includes but is not limited to any community
spaces (both public and private), the entire Adafruit Discord server, and
Adafruit GitHub repositories. Examples of Adafruit Community spaces include
but are not limited to meet-ups, audio chats on the Adafruit Discord, or
interaction at a conference.
This Code of Conduct applies both within project spaces and in public spaces
when an individual is representing the project or its community. Examples of
representing a project or community include using an official project e-mail
address, posting via an official social media account, or acting as an appointed
representative at an online or offline event. Representation of a project may be
further defined and clarified by project maintainers.
## Enforcement
Instances of abusive, harassing, or otherwise unacceptable behavior may be
reported by contacting the project team at support@adafruit.com. All
complaints will be reviewed and investigated and will result in a response that
is deemed necessary and appropriate to the circumstances. The project team is
obligated to maintain confidentiality with regard to the reporter of an incident.
Further details of specific enforcement policies may be posted separately.
Project maintainers who do not follow or enforce the Code of Conduct in good
faith may face temporary or permanent repercussions as determined by other
members of the project's leadership.
when an individual is representing the project or its community. As a community
member, you are representing our community, and are expected to behave
accordingly.
## Attribution
This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
available at [http://contributor-covenant.org/version/1/4][version]
This Code of Conduct is adapted from the [Contributor Covenant][homepage],
version 1.4, available at
<https://www.contributor-covenant.org/version/1/4/code-of-conduct.html>,
and the [Rust Code of Conduct](https://www.rust-lang.org/en-US/conduct.html).
[homepage]: http://contributor-covenant.org
[version]: http://contributor-covenant.org/version/1/4/
For other projects adopting the Adafruit Community Code of
Conduct, please contact the maintainers of those projects for enforcement.
If you wish to use this code of conduct for your own project, consider
explicitly mentioning your moderation policy or making a copy with your
own moderation policy so as to avoid confusion.

2
CONTRIBUTING.md
View File

@ -1,6 +1,6 @@
# Contributing
Please note that this project is released with a
[Contributor Code of Conduct](https://github.com/adafruit/circuitpython/blob/master/CODE_OF_CONDUCT.md).
[Contributor Code of Conduct](https://github.com/adafruit/circuitpython/blob/main/CODE_OF_CONDUCT.md).
By participating in this project you agree to abide by its terms. Participation
covers any forum used to converse about CircuitPython including unofficial and official spaces. Failure to do
so will result in corrective actions such as time out or ban from the project.

82
Makefile
View File

@ -36,7 +36,7 @@ ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(BASEOPTS)
# the i18n builder cannot share the environment and doctrees with the others
I18NSPHINXOPTS = $(BASEOPTS)
TRANSLATE_SOURCES = extmod lib main.c ports/atmel-samd ports/cxd56 ports/mimxrt10xx ports/nrf ports/stm32f4 py shared-bindings shared-module supervisor
TRANSLATE_SOURCES = extmod lib main.c ports/atmel-samd ports/cxd56 ports/mimxrt10xx ports/nrf ports/stm py shared-bindings shared-module supervisor
.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext stubs
@ -67,9 +67,10 @@ help:
clean:
rm -rf $(BUILDDIR)/*
rm -rf autoapi
rm -rf $(STUBDIR) $(DISTDIR) *.egg-info
html:
html: stubs
$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
@echo
@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
@ -201,21 +202,90 @@ pseudoxml:
@echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."
# phony target so we always run
.PHONY: all-source
all-source:
locale/circuitpython.pot: all-source
find $(TRANSLATE_SOURCES) -iname "*.c" -print | (LC_ALL=C sort) | xgettext -f- -L C -s --add-location=file --keyword=translate -o circuitpython.pot -p locale
# Historically, `make translate` updated the .pot file and ran msgmerge.
# However, this was a frequent source of merge conflicts. Weblate can perform
# msgmerge, so make translate merely update the translation template file.
.PHONY: translate
translate: locale/circuitpython.pot
# Note that normally we rely on weblate to perform msgmerge. This reduces the
# chance of a merge conflict between developer changes (that only add and
# remove source strings) and weblate changes (that only add and remove
# translated strings from po files). However, in case this is legitimately
# needed we preserve a rule to do it.
.PHONY: msgmerge
msgmerge:
for po in $(shell ls locale/*.po); do msgmerge -U $$po -s --no-fuzzy-matching --add-location=file locale/circuitpython.pot; done
check-translate: locale/circuitpython.pot $(wildcard locale/*.po)
$(PYTHON) tools/check_translations.py $^
merge-translate:
git merge HEAD 1>&2 2> /dev/null; test $$? -eq 128
rm locale/*~ || true
git checkout --theirs -- locale/*
make translate
.PHONY: check-translate
check-translate:
find $(TRANSLATE_SOURCES) -iname "*.c" -print | (LC_ALL=C sort) | xgettext -f- -L C -s --add-location=file --keyword=translate -o circuitpython.pot.tmp -p locale
$(PYTHON) tools/check_translations.py locale/circuitpython.pot.tmp locale/circuitpython.pot; status=$$?; rm -f locale/circuitpython.pot.tmp; exit $$status
stubs:
rst2pyi $(VALIDATE) shared-bindings/ $(STUBDIR)
python setup.py sdist
@mkdir -p circuitpython-stubs
@$(PYTHON) tools/extract_pyi.py shared-bindings/ $(STUBDIR)
@$(PYTHON) tools/extract_pyi.py ports/atmel-samd/bindings $(STUBDIR)
@$(PYTHON) setup.py -q sdist
update-frozen-libraries:
@echo "Updating all frozen libraries to latest tagged version."
cd frozen; for library in *; do cd $$library; ../../tools/git-checkout-latest-tag.sh; cd ..; done
one-of-each: samd21 samd51 esp32s2 litex mimxrt10xx nrf stm
samd21:
$(MAKE) -C ports/atmel-samd BOARD=trinket_m0
samd51:
$(MAKE) -C ports/atmel-samd BOARD=feather_m4_express
esp32s2:
$(MAKE) -C ports/esp32s2 BOARD=espressif_saola_1_wroom
litex:
$(MAKE) -C ports/litex BOARD=fomu
mimxrt10xx:
$(MAKE) -C ports/mimxrt10xx BOARD=feather_mimxrt1011
nrf:
$(MAKE) -C ports/nrf BOARD=feather_nrf52840_express
stm:
$(MAKE) -C ports/stm BOARD=feather_stm32f405_express
clean-one-of-each: clean-samd21 clean-samd51 clean-esp32s2 clean-litex clean-mimxrt10xx clean-nrf clean-stm
clean-samd21:
$(MAKE) -C ports/atmel-samd BOARD=trinket_m0 clean
clean-samd51:
$(MAKE) -C ports/atmel-samd BOARD=feather_m4_express clean
clean-esp32s2:
$(MAKE) -C ports/esp32s2 BOARD=espressif_saola_1_wroom clean
clean-litex:
$(MAKE) -C ports/litex BOARD=fomu clean
clean-mimxrt10xx:
$(MAKE) -C ports/mimxrt10xx BOARD=feather_mimxrt1011 clean
clean-nrf:
$(MAKE) -C ports/nrf BOARD=feather_nrf52840_express clean
clean-stm:
$(MAKE) -C ports/stm BOARD=feather_stm32f405_express clean

15
README.rst
View File

@ -3,7 +3,7 @@ CircuitPython
.. image:: https://s3.amazonaws.com/adafruit-circuit-python/CircuitPython_Repo_header_logo.png
|Build Status| |Doc Status| |License| |Discord|
|Build Status| |Doc Status| |License| |Discord| |Weblate|
`circuitpython.org <https://circuitpython.org>`__ \| `Get CircuitPython <#get-circuitpython>`__ \|
`Documentation <#documentation>`__ \| `Contributing <#contributing>`__ \|
@ -55,12 +55,12 @@ Contributing
------------
See
`CONTRIBUTING.md <https://github.com/adafruit/circuitpython/blob/master/CONTRIBUTING.md>`__
`CONTRIBUTING.md <https://github.com/adafruit/circuitpython/blob/main/CONTRIBUTING.md>`__
for full guidelines but please be aware that by contributing to this
project you are agreeing to the `Code of
Conduct <https://github.com/adafruit/circuitpython/blob/master/CODE_OF_CONDUCT.md>`__.
Conduct <https://github.com/adafruit/circuitpython/blob/main/CODE_OF_CONDUCT.md>`__.
Contributors who follow the `Code of
Conduct <https://github.com/adafruit/circuitpython/blob/master/CODE_OF_CONDUCT.md>`__
Conduct <https://github.com/adafruit/circuitpython/blob/main/CODE_OF_CONDUCT.md>`__
are welcome to submit pull requests and they will be promptly reviewed
by project admins. Please join the
`Discord <https://adafru.it/discord>`__ too.
@ -96,7 +96,6 @@ CircuitPython:
- Supports native USB on all boards, allowing file editing without special tools.
- Supports only SAMD21, SAMD51, nRF52840, CXD56, STM32F4 and i.MX RT ports.
- Tracks MicroPython's releases (not master).
- Floats (aka decimals) are enabled for all builds.
- Error messages are translated into 10+ languages.
- Does not support concurrency within Python (including interrupts and threading). Some concurrency
@ -211,11 +210,13 @@ The remaining port directories not listed above are in the repo to maintain comp
`back to top <#circuitpython>`__
.. |Build Status| image:: https://travis-ci.com/adafruit/circuitpython.svg?branch=master
:target: https://travis-ci.org/adafruit/circuitpython
.. |Build Status| image:: https://github.com/adafruit/circuitpython/workflows/Build%20CI/badge.svg
:target: https://github.com/adafruit/circuitpython/actions?query=branch%3Amain
.. |Doc Status| image:: https://readthedocs.org/projects/circuitpython/badge/?version=latest
:target: http://circuitpython.readthedocs.io/
.. |Discord| image:: https://img.shields.io/discord/327254708534116352.svg
:target: https://adafru.it/discord
.. |License| image:: https://img.shields.io/badge/License-MIT-brightgreen.svg
:target: https://choosealicense.com/licenses/mit/
.. |Weblate| image:: https://hosted.weblate.org/widgets/circuitpython/-/svg-badge.svg
:target: https://hosted.weblate.org/engage/circuitpython/?utm_source=widget

104
conf.py
View File

@ -14,10 +14,13 @@
# serve to show the default.
import json
import sys
import logging
import os
import subprocess
import sys
import urllib.parse
from recommonmark.parser import CommonMarkParser
import recommonmark
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
@ -55,16 +58,32 @@ extensions = [
'sphinx.ext.todo',
'sphinx.ext.coverage',
'rstjinja',
'c2rst'
'recommonmark',
]
# Add any paths that contain templates here, relative to this directory.
templates_path = ['templates']
# The suffix of source filenames.
source_suffix = ['.rst', '.md', '.c', '.h']
source_suffix = {
'.rst': 'restructuredtext',
'.md': 'markdown',
}
source_parsers = {'.md': CommonMarkParser}
subprocess.check_output(["make", "stubs"])
extensions.append('autoapi.extension')
autoapi_type = 'python'
# Uncomment this if debugging autoapi
autoapi_keep_files = True
autoapi_dirs = [os.path.join('circuitpython-stubs', x) for x in os.listdir('circuitpython-stubs')]
autoapi_add_toctree_entry = False
autoapi_options = ['members', 'undoc-members', 'private-members', 'show-inheritance', 'special-members', 'show-module-summary']
autoapi_template_dir = 'docs/autoapi/templates'
autoapi_python_use_implicit_namespaces = True
autoapi_root = "shared-bindings"
redirects_file = 'docs/redirects.txt'
# The encoding of source files.
#source_encoding = 'utf-8-sig'
@ -74,7 +93,7 @@ source_parsers = {'.md': CommonMarkParser}
# General information about the project.
project = 'Adafruit CircuitPython'
copyright = '2014-2018, MicroPython & CircuitPython contributors (https://github.com/adafruit/circuitpython/graphs/contributors)'
copyright = '2014-2020, MicroPython & CircuitPython contributors (https://github.com/adafruit/circuitpython/graphs/contributors)'
# These are overwritten on ReadTheDocs.
# The version info for the project you're documenting, acts as replacement for
@ -101,6 +120,7 @@ exclude_patterns = ["**/build*",
".git",
".venv",
".direnv",
"docs/autoapi",
"docs/README.md",
"drivers",
"examples",
@ -121,16 +141,11 @@ exclude_patterns = ["**/build*",
"ports/atmel-samd/peripherals",
"ports/atmel-samd/QTouch",
"ports/atmel-samd/tools",
"ports/bare-arm",
"ports/cc3200",
"ports/cc3200/FreeRTOS",
"ports/cc3200/hal",
"ports/cxd56/mkspk",
"ports/cxd56/spresense-exported-sdk",
"ports/esp32",
"ports/esp8266/boards",
"ports/esp8266/common-hal",
"ports/esp8266/modules",
"ports/esp32s2/esp-idf",
"ports/esp32s2/peripherals",
"ports/litex/hw",
"ports/minimal",
"ports/mimxrt10xx/peripherals",
"ports/mimxrt10xx/sdk",
@ -140,20 +155,11 @@ exclude_patterns = ["**/build*",
"ports/nrf/nrfx",
"ports/nrf/peripherals",
"ports/nrf/usb",
"ports/stm32f4/stm32f4",
"ports/stm32f4/peripherals",
"ports/stm32f4/ref",
"ports/pic16bit",
"ports/qemu-arm",
"ports/stm32",
"ports/stm32/hal",
"ports/stm32/cmsis",
"ports/stm32/usbdev",
"ports/stm32/usbhost",
"ports/teensy",
"ports/stm/st_driver",
"ports/stm/packages",
"ports/stm/peripherals",
"ports/stm/ref",
"ports/unix",
"ports/windows",
"ports/zephyr",
"py",
"shared-bindings/util.*",
"shared-module",
@ -373,5 +379,47 @@ intersphinx_mapping = {"cpython": ('https://docs.python.org/3/', None),
"bus_device": ('https://circuitpython.readthedocs.io/projects/busdevice/en/latest/', None),
"register": ('https://circuitpython.readthedocs.io/projects/register/en/latest/', None)}
# Adapted from sphinxcontrib-redirects
from sphinx.builders import html as builders
TEMPLATE = """<html>
<head><meta http-equiv="refresh" content="0; url=%s"/></head>
</html>
"""
def generate_redirects(app):
path = os.path.join(app.srcdir, app.config.redirects_file)
if not os.path.exists(path):
logging.error("Could not find redirects file at '%s'" % path)
return
if not isinstance(app.builder, builders.StandaloneHTMLBuilder):
logging.warn("The 'sphinxcontib-redirects' plugin is only supported "
"by the 'html' builder and subclasses. Skipping...")
logging.warn(f"Builder is {app.builder.name} ({type(app.builder)})")
return
with open(path) as redirects:
for line in redirects.readlines():
from_path, to_path = line.rstrip().split(' ')
logging.debug("Redirecting '%s' to '%s'" % (from_path, to_path))
from_path = os.path.splitext(from_path)[0] + ".html"
to_path_prefix = '..%s' % os.path.sep * (
len(from_path.split(os.path.sep)) - 1)
to_path = to_path_prefix + to_path
redirected_filename = os.path.join(app.builder.outdir, from_path)
redirected_directory = os.path.dirname(redirected_filename)
if not os.path.exists(redirected_directory):
os.makedirs(redirected_directory)
with open(redirected_filename, 'w') as f:
f.write(TEMPLATE % urllib.parse.quote(to_path, '#/'))
def setup(app):
app.add_stylesheet("customstyle.css")
app.add_css_file("customstyle.css")
app.add_config_value('redirects_file', 'redirects', 'env')
app.connect('builder-inited', generate_redirects)

2
docs/README.md
View File

@ -5,7 +5,7 @@ The latest documentation can be found at:
http://circuitpython.readthedocs.io/en/latest/
The documentation you see there is generated from the files in the whole tree:
https://github.com/adafruit/circuitpython/tree/master
https://github.com/adafruit/circuitpython/tree/main
Building the documentation locally
----------------------------------

93
docs/autoapi/templates/python/module.rst Normal file
View File

@ -0,0 +1,93 @@
{% if not obj.display %}
:orphan:
{% endif %}
:mod:`{{ obj.name }}`
======={{ "=" * obj.name|length }}
.. py:module:: {{ obj.name }}
{% if obj.docstring %}
.. autoapi-nested-parse::
{{ obj.docstring|prepare_docstring|indent(3) }}
{% endif %}
{% block subpackages %}
{% set visible_subpackages = obj.subpackages|selectattr("display")|list %}
{% if visible_subpackages %}
.. toctree::
:titlesonly:
:maxdepth: 3
{% for subpackage in visible_subpackages %}
{{ subpackage.short_name }}/index.rst
{% endfor %}
{% endif %}
{% endblock %}
{% block submodules %}
{% set visible_submodules = obj.submodules|selectattr("display")|list %}
{% if visible_submodules %}
.. toctree::
:titlesonly:
:maxdepth: 1
{% for submodule in visible_submodules %}
{{ submodule.short_name }}/index.rst
{% endfor %}
{% endif %}
{% endblock %}
{% block content %}
{% if obj.all is not none %}
{% set visible_children = obj.children|selectattr("short_name", "in", obj.all)|list %}
{% elif obj.type is equalto("package") %}
{% set visible_children = obj.children|selectattr("display")|list %}
{% else %}
{% set visible_children = obj.children|selectattr("display")|rejectattr("imported")|list %}
{% endif %}
{% if visible_children %}
{% set visible_classes = visible_children|selectattr("type", "equalto", "class")|list %}
{% set visible_functions = visible_children|selectattr("type", "equalto", "function")|list %}
{% if "show-module-summary" in autoapi_options and (visible_classes or visible_functions) %}
{% block classes %}
{% if visible_classes %}
Classes
~~~~~~~
.. autoapisummary::
{% for klass in visible_classes %}
{{ klass.id }}
{% endfor %}
{% endif %}
{% endblock %}
{% block functions %}
{% if visible_functions %}
Functions
~~~~~~~~~
.. autoapisummary::
{% for function in visible_functions %}
{{ function.id }}
{% endfor %}
{% endif %}
{% endblock %}
{% endif %}
{% for obj_item in visible_children %}
{{ obj_item.rendered|indent(0) }}
{% endfor %}
{% endif %}
{% endblock %}

31
docs/c2rst.py
View File

@ -1,31 +0,0 @@
def c2rst(app, docname, source):
""" Pre-parse '.c' & '.h' files that contain rST source.
"""
# Make sure we're outputting HTML
if app.builder.format != 'html':
return
fname = app.env.doc2path(docname)
if (not fname.endswith(".c") and
not fname.endswith(".h")):
#print("skipping:", fname)
return
src = source[0]
stripped = []
for line in src.split("\n"):
line = line.strip()
if line == "//|":
stripped.append("")
elif line.startswith("//| "):
stripped.append(line[len("//| "):])
stripped = "\r\n".join(stripped)
rendered = app.builder.templates.render_string(
stripped, app.config.html_context
)
source[0] = rendered
def setup(app):
app.connect("source-read", c2rst)

43
docs/design_guide.rst
View File

@ -1,9 +1,11 @@
.. role:: strike
Design Guide
============
This guide covers a variety of development practices for CircuitPython core and library APIs. These
APIs are both `built-into CircuitPython
<https://github.com/adafruit/circuitpython/tree/master/shared-bindings>`_ and those that are
<https://github.com/adafruit/circuitpython/tree/main/shared-bindings>`_ and those that are
`distributed on GitHub <https://github.com/search?utf8=%E2%9C%93&q=topic%3Acircuitpython&type=>`_
and in the `Adafruit <https://github.com/adafruit/Adafruit_CircuitPython_Bundle>`_ and `Community
<https://github.com/adafruit/CircuitPython_Community_Bundle/>`_ bundles. Consistency with these
@ -46,6 +48,41 @@ not have the ``adafruit_`` module or package prefix.
Both should have the CircuitPython repository topic on GitHub.
Terminology
-----------
As our Code of Conduct states, we strive to use "welcoming and inclusive
language." Whether it is in documentation or in code, the words we use matter.
This means we disfavor language that due to historical and social context can
make community members and potential community members feel unwelcome.
There are specific terms to avoid except where technical limitations require it.
While specific cases may call for other terms, consider using these suggested
terms first:
+--------------------+---------------------+
| Preferred | Deprecated |
+====================+=====================+
| Main (device) | :strike:`Master` |
+--------------------+---------------------+
| Peripheral | :strike:`Slave` |
+--------------------+ +
| Sensor | |
+--------------------+ +
| Secondary (device) | |
+--------------------+---------------------+
| Denylist | :strike:`Blacklist` |
+--------------------+---------------------+
| Allowlist | :strike:`Whitelist` |
+--------------------+---------------------+
Note that "technical limitations" refers e.g., to the situation where an
upstream library or URL has to contain those substrings in order to work.
However, when it comes to documentation and the names of parameters and
properties in CircuitPython, we will use alternate terms even if this breaks
tradition with past practice.
.. _lifetime-and-contextmanagers:
Lifetime and ContextManagers
@ -476,6 +513,8 @@ properties.
+-----------------------+-----------------------+-------------------------------------------------------------------------+
| ``distance`` | float | centimeters |
+-----------------------+-----------------------+-------------------------------------------------------------------------+
| ``proximity`` | int | non-unit-specifc proximity values (monotonic but not actual distance) |
+-----------------------+-----------------------+-------------------------------------------------------------------------+
| ``light`` | float | non-unit-specific light levels (should be monotonic but is not lux) |
+-----------------------+-----------------------+-------------------------------------------------------------------------+
| ``lux`` | float | SI lux |
@ -504,6 +543,8 @@ properties.
+-----------------------+-----------------------+-------------------------------------------------------------------------+
| ``weight`` | float | grams (g) |
+-----------------------+-----------------------+-------------------------------------------------------------------------+
| ``sound_level`` | float | non-unit-specific sound level (monotonic but not actual decibels) |
+-----------------------+-----------------------+-------------------------------------------------------------------------+
Adding native modules
--------------------------------------------------------------------------------

2
docs/library/network.rst
View File

@ -247,7 +247,7 @@ Methods
nic.ifconfig(('192.168.0.4', '255.255.255.0', '192.168.0.1', '8.8.8.8'))
.. method:: wlan.config('param')
.. method:: wlan.config(param=value, ...)
wlan.config(param=value, ...)
Get or set general network interface parameters. These methods allow to work
with additional parameters beyond standard IP configuration (as dealt with by

42
docs/porting.rst
View File

@ -1,5 +1,5 @@
We love CircuitPython and would love to see it come to more microcontroller
platforms. With 3.0 we've reworked CircuitPython to make it easier than ever to
platforms. Since 3.0 we've reworked CircuitPython to make it easier than ever to
add support. While there are some major differences between ports, this page
covers the similarities that make CircuitPython what it is and how that core
fits into a variety of microcontrollers.
@ -19,7 +19,7 @@ prepping file systems and automatically running user code on boot. In
CircuitPython we've dubbed this component the supervisor because it monitors
and facilitates the VMs which run user Python code. Porting involves the
supervisor because many of the tasks it does while interfacing with the
hardware. Once its going though, the REPL works and debugging can migrate to a
hardware. Once complete, the REPL works and debugging can migrate to a
Python based approach rather than C.
The third core piece is the plethora of low level APIs that CircuitPython
@ -42,6 +42,44 @@ to the port's directory (in the top level until the ``ports`` directory is
present). This includes the Makefile and any C library resources. Make sure
these resources are compatible with the MIT License of the rest of the code!
Circuitpython has a number of modules enabled by default in
``py/circuitpy_mpconfig.mk``. Most of these modules will need to be disabled in
``mpconfigboard.mk`` during the early stages of a port in order for it to
compile. As the port progresses in module support, this list can be pruned down
as a natural "TODO" list. An example minimal build list is shown below:
.. code-block:: makefile
# These modules are implemented in ports/<port>/common-hal:
CIRCUITPY_MICROCONTROLLER = 0 # Typically the first module to create
CIRCUITPY_DIGITALIO = 0 # Typically the second module to create
CIRCUITPY_ANALOGIO = 0
CIRCUITPY_BUSIO = 0
CIRCUITPY_NEOPIXEL_WRITE = 0
CIRCUITPY_PULSEIO = 0
CIRCUITPY_OS = 0
CIRCUITPY_NVM = 0
CIRCUITPY_AUDIOBUSIO = 0
CIRCUITPY_AUDIOIO = 0
CIRCUITPY_ROTARYIO = 0
CIRCUITPY_RTC = 0
CIRCUITPY_FREQUENCYIO = 0
CIRCUITPY_I2CPERIPHERAL = 0
CIRCUITPY_DISPLAYIO = 0 # Requires SPI, PulseIO (stub ok)
# These modules are implemented in shared-module/ - they can be included in
# any port once their prerequisites in common-hal are complete.
CIRCUITPY_BITBANGIO = 0 # Requires DigitalIO
CIRCUITPY_GAMEPAD = 0 # Requires DigitalIO
CIRCUITPY_PIXELBUF = 0 # Requires neopixel_write or SPI (dotstar)
CIRCUITPY_RANDOM = 0 # Requires OS
CIRCUITPY_STORAGE = 0 # Requires OS, filesystem
CIRCUITPY_TOUCHIO = 0 # Requires Microcontroller
CIRCUITPY_USB_HID = 0 # Requires USB
CIRCUITPY_USB_MIDI = 0 # Requires USB
CIRCUITPY_REQUIRE_I2C_PULLUPS = 0 # Does nothing without I2C
CIRCUITPY_ULAB = 0 # No requirements, but takes extra flash
Step 2: Init
--------------
Once your build is setup, the next step should be to get your clocks going as

161
docs/redirects.txt Normal file
View File

@ -0,0 +1,161 @@
shared-bindings//__init__.rst shared-bindings//
shared-bindings/_bleio/Adapter.rst shared-bindings/_bleio/#_bleio.Adapter
shared-bindings/_bleio/Address.rst shared-bindings/_bleio/#_bleio.Address
shared-bindings/_bleio/Attribute.rst shared-bindings/_bleio/#_bleio.Attribute
shared-bindings/_bleio/BluetoothError.rst shared-bindings/_bleio/#_bleio.BluetoothError
shared-bindings/_bleio/Characteristic.rst shared-bindings/_bleio/#_bleio.Characteristic
shared-bindings/_bleio/CharacteristicBuffer.rst shared-bindings/_bleio/#_bleio.CharacteristicBuffer
shared-bindings/_bleio/Connection.rst shared-bindings/_bleio/#_bleio.Connection
shared-bindings/_bleio/ConnectionError.rst shared-bindings/_bleio/#_bleio.ConnectionError
shared-bindings/_bleio/Descriptor.rst shared-bindings/_bleio/#_bleio.Descriptor
shared-bindings/_bleio/PacketBuffer.rst shared-bindings/_bleio/#_bleio.PacketBuffer
shared-bindings/_bleio/RoleError.rst shared-bindings/_bleio/#_bleio.RoleError
shared-bindings/_bleio/ScanEntry.rst shared-bindings/_bleio/#_bleio.ScanEntry
shared-bindings/_bleio/ScanResults.rst shared-bindings/_bleio/#_bleio.ScanResults
shared-bindings/_bleio/SecurityError.rst shared-bindings/_bleio/#_bleio.SecurityError
shared-bindings/_bleio/Service.rst shared-bindings/_bleio/#_bleio.Service
shared-bindings/_bleio/UUID.rst shared-bindings/_bleio/#_bleio.UUID
shared-bindings/_bleio/__init__.rst shared-bindings/_bleio/
shared-bindings/_eve/__init__.rst shared-bindings/_eve/
shared-bindings/_pew/PewPew.rst shared-bindings/_pew/#_pew.PewPew
shared-bindings/_pew/__init__.rst shared-bindings/_pew/
shared-bindings/_pixelbuf/PixelBuf.rst shared-bindings/_pixelbuf/#_pixelbuf.PixelBuf
shared-bindings/_pixelbuf/__init__.rst shared-bindings/_pixelbuf/
shared-bindings/_stage/Layer.rst shared-bindings/_stage/#_stage.Layer
shared-bindings/_stage/Text.rst shared-bindings/_stage/#_stage.Text
shared-bindings/_stage/__init__.rst shared-bindings/_stage/
shared-bindings/aesio/AES.rst shared-bindings/aesio/#aesio.AES
shared-bindings/aesio/__init__.rst shared-bindings/aesio/
shared-bindings/analogio/AnalogIn.rst shared-bindings/analogio/#analogio.AnalogIn
shared-bindings/analogio/AnalogOut.rst shared-bindings/analogio/#analogio.AnalogOut
shared-bindings/analogio/__init__.rst shared-bindings/analogio/
shared-bindings/audiobusio/I2SOut.rst shared-bindings/audiobusio/#audiobusio.I2SOut
shared-bindings/audiobusio/PDMIn.rst shared-bindings/audiobusio/#audiobusio.PDMIn
shared-bindings/audiobusio/__init__.rst shared-bindings/audiobusio/
shared-bindings/audiocore/RawSample.rst shared-bindings/audiocore/#audiocore.RawSample
shared-bindings/audiocore/WaveFile.rst shared-bindings/audiocore/#audiocore.WaveFile
shared-bindings/audiocore/__init__.rst shared-bindings/audiocore/
shared-bindings/audioio/AudioOut.rst shared-bindings/audioio/#audioio.AudioOut
shared-bindings/audioio/__init__.rst shared-bindings/audioio/
shared-bindings/audiomixer/Mixer.rst shared-bindings/audiomixer/#audiomixer.Mixer
shared-bindings/audiomixer/MixerVoice.rst shared-bindings/audiomixer/#audiomixer.MixerVoice
shared-bindings/audiomixer/__init__.rst shared-bindings/audiomixer/
shared-bindings/audiomp3/MP3.rst shared-bindings/audiomp3/#audiomp3.MP3
shared-bindings/audiomp3/__init__.rst shared-bindings/audiomp3/
shared-bindings/audiopwmio/PWMAudioOut.rst shared-bindings/audiopwmio/#audiopwmio.PWMAudioOut
shared-bindings/audiopwmio/__init__.rst shared-bindings/audiopwmio/
shared-bindings/bitbangio/I2C.rst shared-bindings/bitbangio/#bitbangio.I2C
shared-bindings/bitbangio/OneWire.rst shared-bindings/bitbangio/#bitbangio.OneWire
shared-bindings/bitbangio/SPI.rst shared-bindings/bitbangio/#bitbangio.SPI
shared-bindings/bitbangio/__init__.rst shared-bindings/bitbangio/
shared-bindings/board/__init__.rst shared-bindings/board/
shared-bindings/busio/I2C.rst shared-bindings/busio/#busio.I2C
shared-bindings/busio/OneWire.rst shared-bindings/busio/#busio.OneWire
shared-bindings/busio/Parity.rst shared-bindings/busio/#busio.Parity
shared-bindings/busio/SPI.rst shared-bindings/busio/#busio.SPI
shared-bindings/busio/UART.rst shared-bindings/busio/#busio.UART
shared-bindings/busio/__init__.rst shared-bindings/busio/
shared-bindings/countio/Counter.rst shared-bindings/countio/#countio.Counter
shared-bindings/countio/__init__.rst shared-bindings/countio/
shared-bindings/digitalio/DigitalInOut.rst shared-bindings/digitalio/#digitalio.DigitalInOut
shared-bindings/digitalio/Direction.rst shared-bindings/digitalio/#digitalio.Direction
shared-bindings/digitalio/DriveMode.rst shared-bindings/digitalio/#digitalio.DriveMode
shared-bindings/digitalio/Pull.rst shared-bindings/digitalio/#digitalio.Pull
shared-bindings/digitalio/__init__.rst shared-bindings/digitalio/
shared-bindings/displayio/Bitmap.rst shared-bindings/displayio/#displayio.Bitmap
shared-bindings/displayio/ColorConverter.rst shared-bindings/displayio/#displayio.ColorConverter
shared-bindings/displayio/Display.rst shared-bindings/displayio/#displayio.Display
shared-bindings/displayio/EPaperDisplay.rst shared-bindings/displayio/#displayio.EPaperDisplay
shared-bindings/displayio/FourWire.rst shared-bindings/displayio/#displayio.FourWire
shared-bindings/displayio/Group.rst shared-bindings/displayio/#displayio.Group
shared-bindings/displayio/I2CDisplay.rst shared-bindings/displayio/#displayio.I2CDisplay
shared-bindings/displayio/OnDiskBitmap.rst shared-bindings/displayio/#displayio.OnDiskBitmap
shared-bindings/displayio/Palette.rst shared-bindings/displayio/#displayio.Palette
shared-bindings/displayio/ParallelBus.rst shared-bindings/displayio/#displayio.ParallelBus
shared-bindings/displayio/Shape.rst shared-bindings/displayio/#displayio.Shape
shared-bindings/displayio/TileGrid.rst shared-bindings/displayio/#displayio.TileGrid
shared-bindings/displayio/__init__.rst shared-bindings/displayio/
shared-bindings/fontio/BuiltinFont.rst shared-bindings/fontio/#fontio.BuiltinFont
shared-bindings/fontio/Glyph.rst shared-bindings/fontio/#fontio.Glyph
shared-bindings/fontio/__init__.rst shared-bindings/fontio/
shared-bindings/framebufferio/FramebufferDisplay.rst shared-bindings/framebufferio/#framebufferio.FramebufferDisplay
shared-bindings/framebufferio/__init__.rst shared-bindings/framebufferio/
shared-bindings/frequencyio/FrequencyIn.rst shared-bindings/frequencyio/#frequencyio.FrequencyIn
shared-bindings/frequencyio/__init__.rst shared-bindings/frequencyio/
shared-bindings/gamepad/GamePad.rst shared-bindings/gamepad/#gamepad.GamePad
shared-bindings/gamepad/__init__.rst shared-bindings/gamepad/
shared-bindings/gamepadshift/GamePadShift.rst shared-bindings/gamepadshift/#gamepadshift.GamePadShift
shared-bindings/gamepadshift/__init__.rst shared-bindings/gamepadshift/
shared-bindings/gnss/__init__.rst shared-bindings/gnss/
shared-bindings/i2cperipheral/__init__.rst shared-bindings/i2cperipheral/
shared-bindings/i2csecondary/__init__.rst shared-bindings/i2csecondary/
shared-bindings/i2cslave/I2CSlave.rst shared-bindings/i2cperipheral/#i2cperipheral.I2CPeripheral
shared-bindings/i2cslave/I2CSlaveRequest.rst shared-bindings/i2cperipheral/#i2cperipheral.I2CPeripheralRequest
shared-bindings/math/__init__.rst shared-bindings/math/
shared-bindings/microcontroller/Pin.rst shared-bindings/microcontroller/#microcontroller.Pin
shared-bindings/microcontroller/Processor.rst shared-bindings/microcontroller/#microcontroller.Processor
shared-bindings/microcontroller/RunMode.rst shared-bindings/microcontroller/#microcontroller.RunMode
shared-bindings/microcontroller/__init__.rst shared-bindings/microcontroller/
shared-bindings/multiterminal/__init__.rst shared-bindings/multiterminal/
shared-bindings/neopixel_write/__init__.rst shared-bindings/neopixel_write/
shared-bindings/network/__init__.rst shared-bindings/network/
shared-bindings/nvm/ByteArray.rst shared-bindings/nvm/#nvm.ByteArray
shared-bindings/nvm/__init__.rst shared-bindings/nvm/
shared-bindings/os/__init__.rst shared-bindings/os/
shared-bindings/protomatter/__init__.rst shared-bindings/protomatter/
shared-bindings/ps2io/Ps2.rst shared-bindings/ps2io/#ps2io.Ps2
shared-bindings/ps2io/__init__.rst shared-bindings/ps2io/
shared-bindings/pulseio/PWMOut.rst shared-bindings/pulseio/#pulseio.PWMOut
shared-bindings/pulseio/PulseIn.rst shared-bindings/pulseio/#pulseio.PulseIn
shared-bindings/pulseio/PulseOut.rst shared-bindings/pulseio/#pulseio.PulseOut
shared-bindings/pulseio/__init__.rst shared-bindings/pulseio/
shared-bindings/random/__init__.rst shared-bindings/random/
shared-bindings/rgbmatrix/RGBMatrix.rst shared-bindings/rgbmatrix/#rgbmatrix.RGBMatrix
shared-bindings/rgbmatrix/__init__.rst shared-bindings/rgbmatrix/
shared-bindings/rotaryio/IncrementalEncoder.rst shared-bindings/rotaryio/#rotaryio.IncrementalEncoder
shared-bindings/rotaryio/__init__.rst shared-bindings/rotaryio/
shared-bindings/rtc/RTC.rst shared-bindings/rtc/#rtc.RTC
shared-bindings/rtc/__init__.rst shared-bindings/rtc/
shared-bindings/samd/Clock.rst shared-bindings/samd/#samd.Clock
shared-bindings/samd/__init__.rst shared-bindings/samd/
shared-bindings/socket/__init__.rst shared-bindings/socket/
shared-bindings/socket/socket.rst shared-bindings/socket/#socket.socket
shared-bindings/storage/VfsFat.rst shared-bindings/storage/#storage.VfsFat
shared-bindings/storage/__init__.rst shared-bindings/storage/
shared-bindings/struct/__init__.rst shared-bindings/struct/
shared-bindings/supervisor/Runtime.rst shared-bindings/supervisor/#supervisor.Runtime
shared-bindings/supervisor/__init__.rst shared-bindings/supervisor/
shared-bindings/terminalio/Terminal.rst shared-bindings/terminalio/#terminalio.Terminal
shared-bindings/terminalio/__init__.rst shared-bindings/terminalio/
shared-bindings/time/__init__.rst shared-bindings/time/
shared-bindings/time/struct_time.rst shared-bindings/time/#time.struct_time
shared-bindings/touchio/TouchIn.rst shared-bindings/touchio/#touchio.TouchIn
shared-bindings/touchio/__init__.rst shared-bindings/touchio/
shared-bindings/uheap/__init__.rst shared-bindings/uheap/
shared-bindings/ulab/__init__.rst shared-bindings/ulab/
shared-bindings/ulab/approx/__init__.rst shared-bindings/ulab/approx/
shared-bindings/ulab/array.rst shared-bindings/ulab/#ulab.array
shared-bindings/ulab/compare/__init__.rst shared-bindings/ulab/compare/
shared-bindings/ulab/extras/__init__.rst shared-bindings/ulab/extras/
shared-bindings/ulab/fft/__init__.rst shared-bindings/ulab/fft/
shared-bindings/ulab/filter/__init__.rst shared-bindings/ulab/filter/
shared-bindings/ulab/linalg/__init__.rst shared-bindings/ulab/linalg/
shared-bindings/ulab/numerical/__init__.rst shared-bindings/ulab/numerical/
shared-bindings/ulab/poly/__init__.rst shared-bindings/ulab/poly/
shared-bindings/ulab/vector/__init__.rst shared-bindings/ulab/vector/
shared-bindings/usb_hid/Device.rst shared-bindings/usb_hid/#usb_hid.Device
shared-bindings/usb_hid/__init__.rst shared-bindings/usb_hid/
shared-bindings/usb_midi/PortIn.rst shared-bindings/usb_midi/#usb_midi.PortIn
shared-bindings/usb_midi/PortOut.rst shared-bindings/usb_midi/#usb_midi.PortOut
shared-bindings/usb_midi/__init__.rst shared-bindings/usb_midi/
shared-bindings/ustack/__init__.rst shared-bindings/ustack/
shared-bindings/vectorio/Circle.rst shared-bindings/vectorio/#vectorio.Circle
shared-bindings/vectorio/Polygon.rst shared-bindings/vectorio/#vectorio.Polygon
shared-bindings/vectorio/Rectangle.rst shared-bindings/vectorio/#vectorio.Rectangle
shared-bindings/vectorio/VectorShape.rst shared-bindings/vectorio/#vectorio.VectorShape
shared-bindings/vectorio/__init__.rst shared-bindings/vectorio/
shared-bindings/watchdog/WatchDogMode.rst shared-bindings/watchdog/#watchdog.WatchDogMode
shared-bindings/watchdog/WatchDogTimer.rst shared-bindings/watchdog/#watchdog.WatchDogTimer
shared-bindings/watchdog/__init__.rst shared-bindings/watchdog/
shared-bindings/wiznet/WIZNET5K.rst shared-bindings/wiznet/#wiznet.WIZNET5K
shared-bindings/wiznet/__init__.rst shared-bindings/wiznet/

6
docs/requirements.txt
View File

@ -1,3 +1,5 @@
sphinx==1.8.5
recommonmark==0.5.0
sphinx<3
recommonmark==0.6.0
sphinxcontrib-svg2pdfconverter==0.1.0
astroid
sphinx-autoapi

252
docs/shared_bindings_matrix.py
View File

@ -23,62 +23,35 @@
import json
import os
import pathlib
import re
import subprocess
import sys
SUPPORTED_PORTS = ["atmel-samd", "nrf", "mimxrt10xx"]
SUPPORTED_PORTS = ['atmel-samd', 'esp32s2', 'litex', 'mimxrt10xx', 'nrf', 'stm']
def parse_port_config(contents, chip_keyword=None):
""" Compile a dictionary of port-wide module configs, which may
be categorized by chipset.
def get_circuitpython_root_dir():
""" The path to the root './circuitpython' directory
"""
chip_fam = "all"
ifeq_found = False
port_config_results = {"all": []}
file_path = pathlib.Path(__file__).resolve()
root_dir = file_path.parent.parent
chip_pattern = ""
if chip_keyword:
chip_pattern = (
re.compile("(?<=ifeq\s\(\$\({}\)\,)(\w+)".format(chip_keyword))
)
for line in contents:
if chip_keyword:
if not ifeq_found:
check_ifeq = chip_pattern.search(line)
if check_ifeq:
ifeq_found = True
chip_fam = check_ifeq.group(1)
#print("found chip:", chip_fam)
else:
ifeq_found = False
chip_fam = "all"
else:
if "endif" in line:
ifeq_found = False
chip_fam = "all"
if "CIRCUITPY_" in line:
if chip_fam in port_config_results:
port_config_results[chip_fam].append(line.rstrip("\n"))
else:
port_config_results[chip_fam] = [line.rstrip("\n")]
#print(port_config_results)
return port_config_results
return root_dir
def get_shared_bindings():
""" Get a list of modules in shared-bindings based on folder names
"""
return [item for item in os.listdir("./shared-bindings")]
shared_bindings_dir = get_circuitpython_root_dir() / "shared-bindings"
return [item.name for item in shared_bindings_dir.iterdir()]
def read_mpconfig():
""" Open 'circuitpy_mpconfig.mk' and return the contents.
"""
configs = []
with open("py/circuitpy_mpconfig.mk") as mpconfig:
cpy_mpcfg = get_circuitpython_root_dir() / "py" / "circuitpy_mpconfig.mk"
with open(cpy_mpcfg) as mpconfig:
configs = mpconfig.read()
return configs
@ -98,7 +71,7 @@ def build_module_map():
for module in modules:
full_name = module
search_name = module.lstrip("_")
re_pattern = "CIRCUITPY_{}\s=\s(.+)".format(search_name.upper())
re_pattern = "CIRCUITPY_{}\s*\??=\s*(.+)".format(search_name.upper())
find_config = re.findall(re_pattern, configs)
if not find_config:
continue
@ -117,171 +90,82 @@ def build_module_map():
"excluded": {}
}
#print(base)
return base
def get_settings_from_makefile(port_dir, board_name):
""" Invoke make in a mode which prints the database, then parse it for
settings.
def get_excluded_boards(base):
""" Cycles through each board's `mpconfigboard.mk` file to determine
if each module is included or not. Boards are selected by existence
in a port listed in `SUPPORTED_PORTS` (e.g. `/port/nrf/feather_52840`)
Boards are further categorized by their respective chipset (SAMD21,
SAMD51, nRF52840, etc.)
This means that the effect of all Makefile directives is taken
into account, without having to re-encode the logic that sets them
in this script, something that has proved error-prone
"""
modules = list(base.keys())
contents = subprocess.run(
["make", "-C", port_dir, f"BOARD={board_name}", "-qp", "print-CC"],
encoding="utf-8",
errors="replace",
stdout=subprocess.PIPE,
stderr=subprocess.PIPE
)
# Make signals errors with exit status 2; 0 and 1 are "non-error" statuses
if contents.returncode not in (0, 1):
error_msg = (
f"Invoking '{' '.join(contents.args)}' exited with "
f"{contents.returncode}: {contents.stderr}"
)
raise RuntimeError(error_msg)
re_board_chip = None
chip_keyword = None
for port in SUPPORTED_PORTS:
# each port appears to use its own define for the chipset
if port in ["atmel-samd"]:
re_board_chip = re.compile("CHIP_FAMILY\s=\s(\w+)")
chip_keyword = "CHIP_FAMILY"
elif port in ["nrf"]:
re_board_chip = re.compile("MCU_VARIANT\s=\s(\w+)")
settings = {}
for line in contents.stdout.split('\n'):
m = re.match(r'^([A-Z][A-Z0-9_]*) = (.*)$', line)
if m:
settings[m.group(1)] = m.group(2)
port_dir = "ports/{}".format(port)
return settings
port_config_contents = ""
with open(os.path.join(port_dir, "mpconfigport.mk")) as port_config:
port_config_contents = port_config.readlines()
port_config = parse_port_config(port_config_contents, chip_keyword)
def lookup_setting(settings, key, default=''):
while True:
value = settings.get(key, default)
if not value.startswith('$'):
break
key = value[2:-1]
return value
for entry in os.scandir(os.path.join(port_dir, "boards")):
if not entry.is_dir():
continue
contents = ""
board_dir = os.path.join(entry.path, "mpconfigboard.mk")
with open(board_dir) as board:
contents = board.read()
board_chip = re_board_chip.search(contents)
#print(entry.name, board_chip.group(1))
if not board_chip:
board_chip = "Unknown Chip"
else:
board_chip = board_chip.group(1)
# add port_config results to contents
contents += "\n" + "\n".join(port_config["all"])
if board_chip in port_config:
contents += "\n" + "\n".join(port_config[board_chip])
check_dependent_modules = dict()
for module in modules:
board_is_excluded = False
# check if board uses `SMALL_BUILD`. if yes, and current
# module is marked as `FULL_BUILD`, board is excluded
small_build = re.search("CIRCUITPY_SMALL_BUILD = 1", contents)
if small_build and base[module]["full_build"] == "1":
board_is_excluded = True
# check if board uses `MINIMAL_BUILD`. if yes, and current
# module is marked as `DEFAULT_BUILD`, board is excluded
min_build = re.search("CIRCUITPY_MINIMAL_BUILD = 1", contents)
if min_build and base[module]["default_value"] == "CIRCUITPY_DEFAULT_BUILD":
board_is_excluded = True
# check if module is specifically disabled for this board
re_pattern = r"CIRCUITPY_{}\s=\s(\w)".format(module.upper())
find_module = re.search(re_pattern, contents)
if not find_module:
if base[module]["default_value"].isdigit():
# check if default inclusion is off ('0'). if the board doesn't
# have it explicitly enabled, its excluded.
if base[module]["default_value"] == "0":
board_is_excluded = True
else:
# this module is dependent on another module. add it
# to the list to check after processing all other modules.
# only need to check exclusion if it isn't already excluded.
if (not board_is_excluded and
base[module]["default_value"] not in [
"None",
"CIRCUITPY_DEFAULT_BUILD"
]):
check_dependent_modules[module] = base[module]["default_value"]
else:
board_is_excluded = find_module.group(1) == "0"
if board_is_excluded:
if board_chip in base[module]["excluded"]:
base[module]["excluded"][board_chip].append(entry.name)
else:
base[module]["excluded"][board_chip] = [entry.name]
for module in check_dependent_modules:
depend_results = set()
parents = check_dependent_modules[module].split("CIRCUITPY_")
parents = [item.strip(", ").lower() for item in parents if item]
for parent in parents:
if parent in base:
if (board_chip in base[parent]["excluded"] and
entry.name in base[parent]["excluded"][board_chip]):
depend_results.add(False)
else:
depend_results.add(True)
# only exclude the module if there were zero parents enabled
# as determined by the 'depend_results' set.
if not any(depend_results):
if board_chip in base[module]["excluded"]:
base[module]["excluded"][board_chip].append(entry.name)
else:
base[module]["excluded"][board_chip] = [entry.name]
#print(json.dumps(base, indent=2))
return base
def support_matrix_excluded_boards():
""" Compiles a list of available modules, and which board definitions
do not include them.
"""
base = build_module_map()
return get_excluded_boards(base)
def support_matrix_by_board():
def support_matrix_by_board(use_branded_name=True):
""" Compiles a list of the available core modules available for each
board.
"""
base = build_module_map()
base_with_exclusions = get_excluded_boards(base)
boards = dict()
for port in SUPPORTED_PORTS:
port_dir = "ports/{}/boards".format(port)
for entry in os.scandir(port_dir):
port_dir = get_circuitpython_root_dir() / "ports" / port
for entry in (port_dir / "boards").iterdir():
if not entry.is_dir():
continue
board_modules = []
board_name = entry.name
board_contents = ""
with open(os.path.join(entry.path, "mpconfigboard.h")) as get_name:
board_contents = get_name.read()
board_name_re = re.search("(?<=MICROPY_HW_BOARD_NAME)\s+(.+)",
board_contents)
if board_name_re:
board_name = board_name_re.group(1).strip('"')
for module in base_with_exclusions.keys():
#print(module)
board_has_module = True
if base_with_exclusions[module]["excluded"]:
for port in base_with_exclusions[module]["excluded"].values():
#print(port)
if entry.name in port:
board_has_module = False
settings = get_settings_from_makefile(str(port_dir), entry.name)
if board_has_module:
board_modules.append(base_with_exclusions[module]["name"])
if use_branded_name:
with open(entry / "mpconfigboard.h") as get_name:
board_contents = get_name.read()
board_name_re = re.search(r"(?<=MICROPY_HW_BOARD_NAME)\s+(.+)",
board_contents)
if board_name_re:
board_name = board_name_re.group(1).strip('"')
board_modules = []
for module in base:
key = f'CIRCUITPY_{module.upper()}'
if int(lookup_setting(settings, key, '0')):
board_modules.append(base[module]['name'])
boards[board_name] = sorted(board_modules)
#print(json.dumps(boards, indent=2))
return boards
if __name__ == '__main__':
print(json.dumps(support_matrix_by_board(), indent=2))

16
docs/static/customstyle.css vendored
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@ -9,7 +9,19 @@
margin: 4px;
}
/* custom CSS to sticky the ' viewing outdated version'
warning
*/
.document > .admonition {
position: sticky;
top: 0px;
background-color: salmon;
z-index: 2;
}
body {
overflow-x: unset!important;
}
/* override table width restrictions */
@media screen and (min-width: 767px) {
@ -24,3 +36,7 @@
overflow: visible !important;
}
}
.strike {
text-decoration: line-through;
}

13
docs/supported_ports.rst
View File

@ -1,14 +1,19 @@
Supported Ports
==============================
Adafruit's CircuitPython currently has limited support with a focus on supporting the Atmel SAMD
and ESP8266.
CircuitPython supports a number of microcontroller families. Support quality for each varies
depending on the active contributors for each port.
Adafruit sponsored developers are actively contributing to atmel-samd, mimxrt10xx, nrf and stm
ports. They also maintain the other ports in order to ensure the boards build. Additional testing
is limited.
.. toctree::
:maxdepth: 2
../ports/atmel-samd/README
../ports/cxd56/README
../ports/litex/README
../ports/mimxrt10xx/README
../ports/nrf/README
../ports/stm32f4/README
../ports/cxd56/README
../ports/stm/README

1
drivers/wiznet5k/ethernet/w5500/w5500.c
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@ -244,4 +244,3 @@ void wiz_recv_ignore(uint8_t sn, uint16_t len)
ptr += len;
setSn_RX_RD(sn,ptr);
}

641
extmod/machine_i2c.c
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@ -1,641 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include "py/mperrno.h"
#include "py/mphal.h"
#include "py/runtime.h"
#include "extmod/machine_i2c.h"
#include "supervisor/shared/translate.h"
#if MICROPY_PY_MACHINE_I2C
typedef mp_machine_soft_i2c_obj_t machine_i2c_obj_t;
STATIC void mp_hal_i2c_delay(machine_i2c_obj_t *self) {
// We need to use an accurate delay to get acceptable I2C
// speeds (eg 1us should be not much more than 1us).
mp_hal_delay_us_fast(self->us_delay);
}
STATIC void mp_hal_i2c_scl_low(machine_i2c_obj_t *self) {
mp_hal_pin_od_low(self->scl);
}
STATIC int mp_hal_i2c_scl_release(machine_i2c_obj_t *self) {
uint32_t count = self->us_timeout;
mp_hal_pin_od_high(self->scl);
mp_hal_i2c_delay(self);
// For clock stretching, wait for the SCL pin to be released, with timeout.
for (; mp_hal_pin_read(self->scl) == 0 && count; --count) {
mp_hal_delay_us_fast(1);
}
if (count == 0) {
return -MP_ETIMEDOUT;
}
return 0; // success
}
STATIC void mp_hal_i2c_sda_low(machine_i2c_obj_t *self) {
mp_hal_pin_od_low(self->sda);
}
STATIC void mp_hal_i2c_sda_release(machine_i2c_obj_t *self) {
mp_hal_pin_od_high(self->sda);
}
STATIC int mp_hal_i2c_sda_read(machine_i2c_obj_t *self) {
return mp_hal_pin_read(self->sda);
}
STATIC int mp_hal_i2c_start(machine_i2c_obj_t *self) {
mp_hal_i2c_sda_release(self);
mp_hal_i2c_delay(self);
int ret = mp_hal_i2c_scl_release(self);
if (ret != 0) {
return ret;
}
mp_hal_i2c_sda_low(self);
mp_hal_i2c_delay(self);
return 0; // success
}
STATIC int mp_hal_i2c_stop(machine_i2c_obj_t *self) {
mp_hal_i2c_delay(self);
mp_hal_i2c_sda_low(self);
mp_hal_i2c_delay(self);
int ret = mp_hal_i2c_scl_release(self);
mp_hal_i2c_sda_release(self);
mp_hal_i2c_delay(self);
return ret;
}
STATIC void mp_hal_i2c_init(machine_i2c_obj_t *self, uint32_t freq) {
self->us_delay = 500000 / freq;
if (self->us_delay == 0) {
self->us_delay = 1;
}
mp_hal_pin_open_drain(self->scl);
mp_hal_pin_open_drain(self->sda);
mp_hal_i2c_stop(self); // ignore error
}
// return value:
// 0 - byte written and ack received
// 1 - byte written and nack received
// <0 - error, with errno being the negative of the return value
STATIC int mp_hal_i2c_write_byte(machine_i2c_obj_t *self, uint8_t val) {
mp_hal_i2c_delay(self);
mp_hal_i2c_scl_low(self);
for (int i = 7; i >= 0; i--) {
if ((val >> i) & 1) {
mp_hal_i2c_sda_release(self);
} else {
mp_hal_i2c_sda_low(self);
}
mp_hal_i2c_delay(self);
int ret = mp_hal_i2c_scl_release(self);
if (ret != 0) {
mp_hal_i2c_sda_release(self);
return ret;
}
mp_hal_i2c_scl_low(self);
}
mp_hal_i2c_sda_release(self);
mp_hal_i2c_delay(self);
int ret = mp_hal_i2c_scl_release(self);
if (ret != 0) {
return ret;
}
int ack = mp_hal_i2c_sda_read(self);
mp_hal_i2c_delay(self);
mp_hal_i2c_scl_low(self);
return ack;
}
// return value:
// 0 - success
// <0 - error, with errno being the negative of the return value
STATIC int mp_hal_i2c_read_byte(machine_i2c_obj_t *self, uint8_t *val, int nack) {
mp_hal_i2c_delay(self);
mp_hal_i2c_scl_low(self);
mp_hal_i2c_delay(self);
uint8_t data = 0;
for (int i = 7; i >= 0; i--) {
int ret = mp_hal_i2c_scl_release(self);
if (ret != 0) {
return ret;
}
data = (data << 1) | mp_hal_i2c_sda_read(self);
mp_hal_i2c_scl_low(self);
mp_hal_i2c_delay(self);
}
*val = data;
// send ack/nack bit
if (!nack) {
mp_hal_i2c_sda_low(self);
}
mp_hal_i2c_delay(self);
int ret = mp_hal_i2c_scl_release(self);
if (ret != 0) {
mp_hal_i2c_sda_release(self);
return ret;
}
mp_hal_i2c_scl_low(self);
mp_hal_i2c_sda_release(self);
return 0; // success
}
// return value:
// >=0 - number of acks received
// <0 - error, with errno being the negative of the return value
int mp_machine_soft_i2c_writeto(mp_obj_base_t *self_in, uint16_t addr, const uint8_t *src, size_t len, bool stop) {
machine_i2c_obj_t *self = (machine_i2c_obj_t*)self_in;
// start the I2C transaction
int ret = mp_hal_i2c_start(self);
if (ret != 0) {
return ret;
}
// write the slave address
ret = mp_hal_i2c_write_byte(self, addr << 1);
if (ret < 0) {
return ret;
} else if (ret != 0) {
// nack received, release the bus cleanly
mp_hal_i2c_stop(self);
return -MP_ENODEV;
}
// write the buffer to the I2C memory
int num_acks = 0;
while (len--) {
ret = mp_hal_i2c_write_byte(self, *src++);
if (ret < 0) {
return ret;
} else if (ret != 0) {
// nack received, stop sending
break;
}
++num_acks;
}
// finish the I2C transaction
if (stop) {
ret = mp_hal_i2c_stop(self);
if (ret != 0) {
return ret;
}
}
return num_acks;
}
// return value:
// 0 - success
// <0 - error, with errno being the negative of the return value
int mp_machine_soft_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *dest, size_t len, bool stop) {
machine_i2c_obj_t *self = (machine_i2c_obj_t*)self_in;
// start the I2C transaction
int ret = mp_hal_i2c_start(self);
if (ret != 0) {
return ret;
}
// write the slave address
ret = mp_hal_i2c_write_byte(self, (addr << 1) | 1);
if (ret < 0) {
return ret;
} else if (ret != 0) {
// nack received, release the bus cleanly
mp_hal_i2c_stop(self);
return -MP_ENODEV;
}
// read the bytes from the slave
while (len--) {
ret = mp_hal_i2c_read_byte(self, dest++, len == 0);
if (ret != 0) {
return ret;
}
}
// finish the I2C transaction
if (stop) {
ret = mp_hal_i2c_stop(self);
if (ret != 0) {
return ret;
}
}
return 0; // success
}
/******************************************************************************/
// MicroPython bindings for I2C
STATIC void machine_i2c_obj_init_helper(machine_i2c_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
enum { ARG_scl, ARG_sda, ARG_freq, ARG_timeout };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_scl, MP_ARG_REQUIRED | MP_ARG_OBJ },
{ MP_QSTR_sda, MP_ARG_REQUIRED | MP_ARG_OBJ },
{ MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 400000} },
{ MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 255} },
};
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
self->scl = mp_hal_get_pin_obj(args[ARG_scl].u_obj);
self->sda = mp_hal_get_pin_obj(args[ARG_sda].u_obj);
self->us_timeout = args[ARG_timeout].u_int;
mp_hal_i2c_init(self, args[ARG_freq].u_int);
}
STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
// check the id argument, if given
if (n_args > 0) {
if (args[0] != MP_OBJ_NEW_SMALL_INT(-1)) {
#if defined(MICROPY_PY_MACHINE_I2C_MAKE_NEW)
// dispatch to port-specific constructor
extern mp_obj_t MICROPY_PY_MACHINE_I2C_MAKE_NEW(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *all_args, mp_map_t *kw_args);
return MICROPY_PY_MACHINE_I2C_MAKE_NEW(type, n_args, args, kw_args);
#else
mp_raise_ValueError(translate("invalid I2C peripheral"));
#endif
}
--n_args;
++args;
}
// create new soft I2C object
machine_i2c_obj_t *self = m_new_obj(machine_i2c_obj_t);
self->base.type = &machine_i2c_type;
machine_i2c_obj_init_helper(self, n_args, args, kw_args);
return (mp_obj_t)self;
}
STATIC mp_obj_t machine_i2c_obj_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
machine_i2c_obj_init_helper(args[0], n_args - 1, args + 1, kw_args);
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_KW(machine_i2c_init_obj, 1, machine_i2c_obj_init);
STATIC mp_obj_t machine_i2c_scan(mp_obj_t self_in) {
mp_obj_base_t *self = MP_OBJ_TO_PTR(self_in);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
mp_obj_t list = mp_obj_new_list(0, NULL);
// 7-bit addresses 0b0000xxx and 0b1111xxx are reserved
for (int addr = 0x08; addr < 0x78; ++addr) {
int ret = i2c_p->writeto(self, addr, NULL, 0, true);
if (ret == 0) {
mp_obj_list_append(list, MP_OBJ_NEW_SMALL_INT(addr));
}
}
return list;
}
MP_DEFINE_CONST_FUN_OBJ_1(machine_i2c_scan_obj, machine_i2c_scan);
STATIC mp_obj_t machine_i2c_start(mp_obj_t self_in) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(self_in);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
if (i2c_p->start == NULL) {
mp_raise_msg(&mp_type_OSError, translate("I2C operation not supported"));
}
int ret = i2c_p->start(self);
if (ret != 0) {
mp_raise_OSError(-ret);
}
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_1(machine_i2c_start_obj, machine_i2c_start);
STATIC mp_obj_t machine_i2c_stop(mp_obj_t self_in) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(self_in);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
if (i2c_p->stop == NULL) {
mp_raise_msg(&mp_type_OSError, translate("I2C operation not supported"));
}
int ret = i2c_p->stop(self);
if (ret != 0) {
mp_raise_OSError(-ret);
}
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_1(machine_i2c_stop_obj, machine_i2c_stop);
STATIC mp_obj_t machine_i2c_readinto(size_t n_args, const mp_obj_t *args) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(args[0]);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
if (i2c_p->read == NULL) {
mp_raise_msg(&mp_type_OSError, translate("I2C operation not supported"));
}
// get the buffer to read into
mp_buffer_info_t bufinfo;
mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_WRITE);
// work out if we want to send a nack at the end
bool nack = (n_args == 2) ? true : mp_obj_is_true(args[2]);
// do the read
int ret = i2c_p->read(self, bufinfo.buf, bufinfo.len, nack);
if (ret != 0) {
mp_raise_OSError(-ret);
}
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_i2c_readinto_obj, 2, 3, machine_i2c_readinto);
STATIC mp_obj_t machine_i2c_write(mp_obj_t self_in, mp_obj_t buf_in) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(self_in);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
if (i2c_p->write == NULL) {
mp_raise_msg(&mp_type_OSError, translate("I2C operation not supported"));
}
// get the buffer to write from
mp_buffer_info_t bufinfo;
mp_get_buffer_raise(buf_in, &bufinfo, MP_BUFFER_READ);
// do the write
int ret = i2c_p->write(self, bufinfo.buf, bufinfo.len);
if (ret < 0) {
mp_raise_OSError(-ret);
}
// return number of acks received
return MP_OBJ_NEW_SMALL_INT(ret);
}
MP_DEFINE_CONST_FUN_OBJ_2(machine_i2c_write_obj, machine_i2c_write);
STATIC mp_obj_t machine_i2c_readfrom(size_t n_args, const mp_obj_t *args) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(args[0]);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
mp_int_t addr = mp_obj_get_int(args[1]);
vstr_t vstr;
vstr_init_len(&vstr, mp_obj_get_int(args[2]));
bool stop = (n_args == 3) ? true : mp_obj_is_true(args[3]);
int ret = i2c_p->readfrom(self, addr, (uint8_t*)vstr.buf, vstr.len, stop);
if (ret < 0) {
mp_raise_OSError(-ret);
}
return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
}
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_i2c_readfrom_obj, 3, 4, machine_i2c_readfrom);
STATIC mp_obj_t machine_i2c_readfrom_into(size_t n_args, const mp_obj_t *args) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(args[0]);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
mp_int_t addr = mp_obj_get_int(args[1]);
mp_buffer_info_t bufinfo;
mp_get_buffer_raise(args[2], &bufinfo, MP_BUFFER_WRITE);
bool stop = (n_args == 3) ? true : mp_obj_is_true(args[3]);
int ret = i2c_p->readfrom(self, addr, bufinfo.buf, bufinfo.len, stop);
if (ret < 0) {
mp_raise_OSError(-ret);
}
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_i2c_readfrom_into_obj, 3, 4, machine_i2c_readfrom_into);
STATIC mp_obj_t machine_i2c_writeto(size_t n_args, const mp_obj_t *args) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(args[0]);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
mp_int_t addr = mp_obj_get_int(args[1]);
mp_buffer_info_t bufinfo;
mp_get_buffer_raise(args[2], &bufinfo, MP_BUFFER_READ);
bool stop = (n_args == 3) ? true : mp_obj_is_true(args[3]);
int ret = i2c_p->writeto(self, addr, bufinfo.buf, bufinfo.len, stop);
if (ret < 0) {
mp_raise_OSError(-ret);
}
// return number of acks received
return MP_OBJ_NEW_SMALL_INT(ret);
}
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_i2c_writeto_obj, 3, 4, machine_i2c_writeto);
STATIC int read_mem(mp_obj_t self_in, uint16_t addr, uint32_t memaddr, uint8_t addrsize, uint8_t *buf, size_t len) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(self_in);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
uint8_t memaddr_buf[4];
size_t memaddr_len = 0;
for (int16_t i = addrsize - 8; i >= 0; i -= 8) {
memaddr_buf[memaddr_len++] = memaddr >> i;
}
int ret = i2c_p->writeto(self, addr, memaddr_buf, memaddr_len, false);
if (ret != memaddr_len) {
// must generate STOP
i2c_p->writeto(self, addr, NULL, 0, true);
return ret;
}
return i2c_p->readfrom(self, addr, buf, len, true);
}
#define MAX_MEMADDR_SIZE (4)
#define BUF_STACK_SIZE (12)
STATIC int write_mem(mp_obj_t self_in, uint16_t addr, uint32_t memaddr, uint8_t addrsize, const uint8_t *buf, size_t len) {
mp_obj_base_t *self = (mp_obj_base_t*)MP_OBJ_TO_PTR(self_in);
mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t*)mp_proto_get(self, QSTR_protocol_i2c);
// need some memory to create the buffer to send; try to use stack if possible
uint8_t buf2_stack[MAX_MEMADDR_SIZE + BUF_STACK_SIZE];
uint8_t *buf2;
size_t buf2_alloc = 0;
if (len <= BUF_STACK_SIZE) {
buf2 = buf2_stack;
} else {
buf2_alloc = MAX_MEMADDR_SIZE + len;
buf2 = m_new(uint8_t, buf2_alloc);
}
// create the buffer to send
size_t memaddr_len = 0;
for (int16_t i = addrsize - 8; i >= 0; i -= 8) {
buf2[memaddr_len++] = memaddr >> i;
}
memcpy(buf2 + memaddr_len, buf, len);
int ret = i2c_p->writeto(self, addr, buf2, memaddr_len + len, true);
if (buf2_alloc != 0) {
m_del(uint8_t, buf2, buf2_alloc);
}
return ret;
}
STATIC const mp_arg_t machine_i2c_mem_allowed_args[] = {
{ MP_QSTR_addr, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
{ MP_QSTR_memaddr, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
{ MP_QSTR_arg, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
{ MP_QSTR_addrsize, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} },
};
STATIC mp_obj_t machine_i2c_readfrom_mem(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
enum { ARG_addr, ARG_memaddr, ARG_n, ARG_addrsize };
mp_arg_val_t args[MP_ARRAY_SIZE(machine_i2c_mem_allowed_args)];
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args,
MP_ARRAY_SIZE(machine_i2c_mem_allowed_args), machine_i2c_mem_allowed_args, args);
// create the buffer to store data into
vstr_t vstr;
vstr_init_len(&vstr, mp_obj_get_int(args[ARG_n].u_obj));
// do the transfer
int ret = read_mem(pos_args[0], args[ARG_addr].u_int, args[ARG_memaddr].u_int,
args[ARG_addrsize].u_int, (uint8_t*)vstr.buf, vstr.len);
if (ret < 0) {
mp_raise_OSError(-ret);
}
return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
}
MP_DEFINE_CONST_FUN_OBJ_KW(machine_i2c_readfrom_mem_obj, 1, machine_i2c_readfrom_mem);
STATIC mp_obj_t machine_i2c_readfrom_mem_into(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
enum { ARG_addr, ARG_memaddr, ARG_buf, ARG_addrsize };
mp_arg_val_t args[MP_ARRAY_SIZE(machine_i2c_mem_allowed_args)];
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args,
MP_ARRAY_SIZE(machine_i2c_mem_allowed_args), machine_i2c_mem_allowed_args, args);
// get the buffer to store data into
mp_buffer_info_t bufinfo;
mp_get_buffer_raise(args[ARG_buf].u_obj, &bufinfo, MP_BUFFER_WRITE);
// do the transfer
int ret = read_mem(pos_args[0], args[ARG_addr].u_int, args[ARG_memaddr].u_int,
args[ARG_addrsize].u_int, bufinfo.buf, bufinfo.len);
if (ret < 0) {
mp_raise_OSError(-ret);
}
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_KW(machine_i2c_readfrom_mem_into_obj, 1, machine_i2c_readfrom_mem_into);
STATIC mp_obj_t machine_i2c_writeto_mem(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
enum { ARG_addr, ARG_memaddr, ARG_buf, ARG_addrsize };
mp_arg_val_t args[MP_ARRAY_SIZE(machine_i2c_mem_allowed_args)];
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args,
MP_ARRAY_SIZE(machine_i2c_mem_allowed_args), machine_i2c_mem_allowed_args, args);
// get the buffer to write the data from
mp_buffer_info_t bufinfo;
mp_get_buffer_raise(args[ARG_buf].u_obj, &bufinfo, MP_BUFFER_READ);
// do the transfer
int ret = write_mem(pos_args[0], args[ARG_addr].u_int, args[ARG_memaddr].u_int,
args[ARG_addrsize].u_int, bufinfo.buf, bufinfo.len);
if (ret < 0) {
mp_raise_OSError(-ret);
}
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_i2c_writeto_mem_obj, 1, machine_i2c_writeto_mem);
STATIC const mp_rom_map_elem_t machine_i2c_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_i2c_init_obj) },
{ MP_ROM_QSTR(MP_QSTR_scan), MP_ROM_PTR(&machine_i2c_scan_obj) },
// primitive I2C operations
{ MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&machine_i2c_start_obj) },
{ MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&machine_i2c_stop_obj) },
{ MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&machine_i2c_readinto_obj) },
{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&machine_i2c_write_obj) },
// standard bus operations
{ MP_ROM_QSTR(MP_QSTR_readfrom), MP_ROM_PTR(&machine_i2c_readfrom_obj) },
{ MP_ROM_QSTR(MP_QSTR_readfrom_into), MP_ROM_PTR(&machine_i2c_readfrom_into_obj) },
{ MP_ROM_QSTR(MP_QSTR_writeto), MP_ROM_PTR(&machine_i2c_writeto_obj) },
// memory operations
{ MP_ROM_QSTR(MP_QSTR_readfrom_mem), MP_ROM_PTR(&machine_i2c_readfrom_mem_obj) },
{ MP_ROM_QSTR(MP_QSTR_readfrom_mem_into), MP_ROM_PTR(&machine_i2c_readfrom_mem_into_obj) },
{ MP_ROM_QSTR(MP_QSTR_writeto_mem), MP_ROM_PTR(&machine_i2c_writeto_mem_obj) },
};
MP_DEFINE_CONST_DICT(mp_machine_soft_i2c_locals_dict, machine_i2c_locals_dict_table);
int mp_machine_soft_i2c_read(mp_obj_base_t *self_in, uint8_t *dest, size_t len, bool nack) {
machine_i2c_obj_t *self = (machine_i2c_obj_t*)self_in;
while (len--) {
int ret = mp_hal_i2c_read_byte(self, dest++, nack && (len == 0));
if (ret != 0) {
return ret;
}
}
return 0; // success
}
int mp_machine_soft_i2c_write(mp_obj_base_t *self_in, const uint8_t *src, size_t len) {
machine_i2c_obj_t *self = (machine_i2c_obj_t*)self_in;
int num_acks = 0;
while (len--) {
int ret = mp_hal_i2c_write_byte(self, *src++);
if (ret < 0) {
return ret;
} else if (ret != 0) {
// nack received, stop sending
break;
}
++num_acks;
}
return num_acks;
}
STATIC const mp_machine_i2c_p_t mp_machine_soft_i2c_p = {
MP_PROTO_IMPLEMENT(MP_QSTR_protocol_i2c)
.start = (int(*)(mp_obj_base_t*))mp_hal_i2c_start,
.stop = (int(*)(mp_obj_base_t*))mp_hal_i2c_stop,
.read = mp_machine_soft_i2c_read,
.write = mp_machine_soft_i2c_write,
.readfrom = mp_machine_soft_i2c_readfrom,
.writeto = mp_machine_soft_i2c_writeto,
};
const mp_obj_type_t machine_i2c_type = {
{ &mp_type_type },
.name = MP_QSTR_I2C,
.make_new = machine_i2c_make_new,
.protocol = &mp_machine_soft_i2c_p,
.locals_dict = (mp_obj_dict_t*)&mp_machine_soft_i2c_locals_dict,
};
#endif // MICROPY_PY_MACHINE_I2C

58
extmod/machine_i2c.h
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@ -1,58 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_EXTMOD_MACHINE_I2C_H
#define MICROPY_INCLUDED_EXTMOD_MACHINE_I2C_H
#include "py/obj.h"
#include "py/proto.h"
// I2C protocol
// the first 4 methods can be NULL, meaning operation is not supported
typedef struct _mp_machine_i2c_p_t {
MP_PROTOCOL_HEAD
int (*start)(mp_obj_base_t *obj);
int (*stop)(mp_obj_base_t *obj);
int (*read)(mp_obj_base_t *obj, uint8_t *dest, size_t len, bool nack);
int (*write)(mp_obj_base_t *obj, const uint8_t *src, size_t len);
int (*readfrom)(mp_obj_base_t *obj, uint16_t addr, uint8_t *dest, size_t len, bool stop);
int (*writeto)(mp_obj_base_t *obj, uint16_t addr, const uint8_t *src, size_t len, bool stop);
} mp_machine_i2c_p_t;
typedef struct _mp_machine_soft_i2c_obj_t {
mp_obj_base_t base;
uint32_t us_delay;
uint32_t us_timeout;
mp_hal_pin_obj_t scl;
mp_hal_pin_obj_t sda;
} mp_machine_soft_i2c_obj_t;
extern const mp_obj_type_t machine_i2c_type;
extern const mp_obj_dict_t mp_machine_soft_i2c_locals_dict;
int mp_machine_soft_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *dest, size_t len, bool stop);
int mp_machine_soft_i2c_writeto(mp_obj_base_t *self_in, uint16_t addr, const uint8_t *src, size_t len, bool stop);
#endif // MICROPY_INCLUDED_EXTMOD_MACHINE_I2C_H

286
extmod/machine_spi.c
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@ -1,286 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdio.h>
#include <string.h>
#include "py/runtime.h"
#include "extmod/machine_spi.h"
#include "supervisor/shared/translate.h"
#if MICROPY_PY_MACHINE_SPI
// if a port didn't define MSB/LSB constants then provide them
#ifndef MICROPY_PY_MACHINE_SPI_MSB
#define MICROPY_PY_MACHINE_SPI_MSB (0)
#define MICROPY_PY_MACHINE_SPI_LSB (1)
#endif
/******************************************************************************/
// MicroPython bindings for generic machine.SPI
STATIC mp_obj_t mp_machine_soft_spi_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args);
mp_obj_t mp_machine_spi_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
// check the id argument, if given
if (n_args > 0) {
if (args[0] != MP_OBJ_NEW_SMALL_INT(-1)) {
#if defined(MICROPY_PY_MACHINE_SPI_MAKE_NEW)
// dispatch to port-specific constructor
extern mp_obj_t MICROPY_PY_MACHINE_SPI_MAKE_NEW(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args);
return MICROPY_PY_MACHINE_SPI_MAKE_NEW(type, n_args, args, kw_args);
#else
mp_raise_ValueError(translate("invalid SPI peripheral"));
#endif
}
--n_args;
++args;
}
// software SPI
return mp_machine_soft_spi_make_new(type, n_args, args, kw_args);
}
STATIC mp_obj_t machine_spi_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
mp_obj_base_t *s = (mp_obj_base_t*)MP_OBJ_TO_PTR(args[0]);
mp_machine_spi_p_t *spi_p = (mp_machine_spi_p_t*)mp_proto_get(QSTR_protocol_spi, s);
spi_p->init(s, n_args - 1, args + 1, kw_args);
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_spi_init_obj, 1, machine_spi_init);
STATIC mp_obj_t machine_spi_deinit(mp_obj_t self) {
mp_obj_base_t *s = (mp_obj_base_t*)MP_OBJ_TO_PTR(self);
mp_machine_spi_p_t *spi_p = (mp_machine_spi_p_t*)mp_proto_get(QSTR_protocol_spi, s);
if (spi_p->deinit != NULL) {
spi_p->deinit(s);
}
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_spi_deinit_obj, machine_spi_deinit);
STATIC void mp_machine_spi_transfer(mp_obj_t self, size_t len, const void *src, void *dest) {
mp_obj_base_t *s = (mp_obj_base_t*)MP_OBJ_TO_PTR(self);
mp_machine_spi_p_t *spi_p = (mp_machine_spi_p_t*)mp_proto_get(QSTR_protocol_spi, s);
spi_p->transfer(s, len, src, dest);
}
STATIC mp_obj_t mp_machine_spi_read(size_t n_args, const mp_obj_t *args) {
vstr_t vstr;
vstr_init_len(&vstr, mp_obj_get_int(args[1]));
memset(vstr.buf, n_args == 3 ? mp_obj_get_int(args[2]) : 0, vstr.len);
mp_machine_spi_transfer(args[0], vstr.len, vstr.buf, vstr.buf);
return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
}
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_spi_read_obj, 2, 3, mp_machine_spi_read);
STATIC mp_obj_t mp_machine_spi_readinto(size_t n_args, const mp_obj_t *args) {
mp_buffer_info_t bufinfo;
mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_WRITE);
memset(bufinfo.buf, n_args == 3 ? mp_obj_get_int(args[2]) : 0, bufinfo.len);
mp_machine_spi_transfer(args[0], bufinfo.len, bufinfo.buf, bufinfo.buf);
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_spi_readinto_obj, 2, 3, mp_machine_spi_readinto);
STATIC mp_obj_t mp_machine_spi_write(mp_obj_t self, mp_obj_t wr_buf) {
mp_buffer_info_t src;
mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ);
mp_machine_spi_transfer(self, src.len, (const uint8_t*)src.buf, NULL);
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_2(mp_machine_spi_write_obj, mp_machine_spi_write);
STATIC mp_obj_t mp_machine_spi_write_readinto(mp_obj_t self, mp_obj_t wr_buf, mp_obj_t rd_buf) {
mp_buffer_info_t src;
mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ);
mp_buffer_info_t dest;
mp_get_buffer_raise(rd_buf, &dest, MP_BUFFER_WRITE);
if (src.len != dest.len) {
mp_raise_ValueError(translate("buffers must be the same length"));
}
mp_machine_spi_transfer(self, src.len, src.buf, dest.buf);
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_3(mp_machine_spi_write_readinto_obj, mp_machine_spi_write_readinto);
STATIC const mp_rom_map_elem_t machine_spi_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_spi_init_obj) },
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_spi_deinit_obj) },
{ MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_machine_spi_read_obj) },
{ MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_machine_spi_readinto_obj) },
{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&mp_machine_spi_write_obj) },
{ MP_ROM_QSTR(MP_QSTR_write_readinto), MP_ROM_PTR(&mp_machine_spi_write_readinto_obj) },
{ MP_ROM_QSTR(MP_QSTR_MSB), MP_ROM_INT(MICROPY_PY_MACHINE_SPI_MSB) },
{ MP_ROM_QSTR(MP_QSTR_LSB), MP_ROM_INT(MICROPY_PY_MACHINE_SPI_LSB) },
};
MP_DEFINE_CONST_DICT(mp_machine_spi_locals_dict, machine_spi_locals_dict_table);
/******************************************************************************/
// Implementation of soft SPI
STATIC uint32_t baudrate_from_delay_half(uint32_t delay_half) {
#ifdef MICROPY_HW_SOFTSPI_MIN_DELAY
if (delay_half == MICROPY_HW_SOFTSPI_MIN_DELAY) {
return MICROPY_HW_SOFTSPI_MAX_BAUDRATE;
} else
#endif
{
return 500000 / delay_half;
}
}
STATIC uint32_t baudrate_to_delay_half(uint32_t baudrate) {
#ifdef MICROPY_HW_SOFTSPI_MIN_DELAY
if (baudrate >= MICROPY_HW_SOFTSPI_MAX_BAUDRATE) {
return MICROPY_HW_SOFTSPI_MIN_DELAY;
} else
#endif
{
uint32_t delay_half = 500000 / baudrate;
// round delay_half up so that: actual_baudrate <= requested_baudrate
if (500000 % baudrate != 0) {
delay_half += 1;
}
return delay_half;
}
}
STATIC void mp_machine_soft_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
mp_machine_soft_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
mp_printf(print, "SoftSPI(baudrate=%u, polarity=%u, phase=%u,"
" sck=" MP_HAL_PIN_FMT ", mosi=" MP_HAL_PIN_FMT ", miso=" MP_HAL_PIN_FMT ")",
baudrate_from_delay_half(self->spi.delay_half), self->spi.polarity, self->spi.phase,
mp_hal_pin_name(self->spi.sck), mp_hal_pin_name(self->spi.mosi), mp_hal_pin_name(self->spi.miso));
}
STATIC mp_obj_t mp_machine_soft_spi_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *all_args, mp_map_t *kw_args) {
enum { ARG_baudrate, ARG_polarity, ARG_phase, ARG_bits, ARG_firstbit, ARG_sck, ARG_mosi, ARG_miso };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_baudrate, MP_ARG_INT, {.u_int = 500000} },
{ MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
{ MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
{ MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} },
{ MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = MICROPY_PY_MACHINE_SPI_MSB} },
{ MP_QSTR_sck, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
{ MP_QSTR_mosi, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
{ MP_QSTR_miso, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
};
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all(n_args, all_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
// create new object
mp_machine_soft_spi_obj_t *self = m_new_obj(mp_machine_soft_spi_obj_t);
self->base.type = &mp_machine_soft_spi_type;
// set parameters
self->spi.delay_half = baudrate_to_delay_half(args[ARG_baudrate].u_int);
self->spi.polarity = args[ARG_polarity].u_int;
self->spi.phase = args[ARG_phase].u_int;
if (args[ARG_bits].u_int != 8) {
mp_raise_ValueError(translate("bits must be 8"));
}
if (args[ARG_firstbit].u_int != MICROPY_PY_MACHINE_SPI_MSB) {
mp_raise_ValueError(translate("firstbit must be MSB"));
}
if (args[ARG_sck].u_obj == MP_OBJ_NULL
|| args[ARG_mosi].u_obj == MP_OBJ_NULL
|| args[ARG_miso].u_obj == MP_OBJ_NULL) {
mp_raise_ValueError(translate("must specify all of sck/mosi/miso"));
}
self->spi.sck = mp_hal_get_pin_obj(args[ARG_sck].u_obj);
self->spi.mosi = mp_hal_get_pin_obj(args[ARG_mosi].u_obj);
self->spi.miso = mp_hal_get_pin_obj(args[ARG_miso].u_obj);
// configure bus
mp_soft_spi_ioctl(&self->spi, MP_SPI_IOCTL_INIT);
return MP_OBJ_FROM_PTR(self);
}
STATIC void mp_machine_soft_spi_init(mp_obj_base_t *self_in, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
mp_machine_soft_spi_obj_t *self = (mp_machine_soft_spi_obj_t*)self_in;
enum { ARG_baudrate, ARG_polarity, ARG_phase, ARG_sck, ARG_mosi, ARG_miso };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_baudrate, MP_ARG_INT, {.u_int = -1} },
{ MP_QSTR_polarity, MP_ARG_INT, {.u_int = -1} },
{ MP_QSTR_phase, MP_ARG_INT, {.u_int = -1} },
{ MP_QSTR_sck, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
{ MP_QSTR_mosi, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
{ MP_QSTR_miso, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
};
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
if (args[ARG_baudrate].u_int != -1) {
self->spi.delay_half = baudrate_to_delay_half(args[ARG_baudrate].u_int);
}
if (args[ARG_polarity].u_int != -1) {
self->spi.polarity = args[ARG_polarity].u_int;
}
if (args[ARG_phase].u_int != -1) {
self->spi.phase = args[ARG_phase].u_int;
}
if (args[ARG_sck].u_obj != MP_OBJ_NULL) {
self->spi.sck = mp_hal_get_pin_obj(args[ARG_sck].u_obj);
}
if (args[ARG_mosi].u_obj != MP_OBJ_NULL) {
self->spi.mosi = mp_hal_get_pin_obj(args[ARG_mosi].u_obj);
}
if (args[ARG_miso].u_obj != MP_OBJ_NULL) {
self->spi.miso = mp_hal_get_pin_obj(args[ARG_miso].u_obj);
}
// configure bus
mp_soft_spi_ioctl(&self->spi, MP_SPI_IOCTL_INIT);
}
STATIC void mp_machine_soft_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) {
mp_machine_soft_spi_obj_t *self = (mp_machine_soft_spi_obj_t*)self_in;
mp_soft_spi_transfer(&self->spi, len, src, dest);
}
const mp_machine_spi_p_t mp_machine_soft_spi_p = {
MP_PROTO_IMPLEMENT(MP_QSTR_protocol_spi)
.init = mp_machine_soft_spi_init,
.deinit = NULL,
.transfer = mp_machine_soft_spi_transfer,
};
const mp_obj_type_t mp_machine_soft_spi_type = {
{ &mp_type_type },
.name = MP_QSTR_SoftSPI,
.print = mp_machine_soft_spi_print,
.make_new = mp_machine_spi_make_new, // delegate to master constructor
.protocol = &mp_machine_soft_spi_p,
.locals_dict = (mp_obj_dict_t*)&mp_machine_spi_locals_dict,
};
#endif // MICROPY_PY_MACHINE_SPI

58
extmod/machine_spi.h
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@ -1,58 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_EXTMOD_MACHINE_SPI_H
#define MICROPY_INCLUDED_EXTMOD_MACHINE_SPI_H
#include "py/obj.h"
#include "py/proto.h"
#include "py/mphal.h"
#include "drivers/bus/spi.h"
// SPI protocol
typedef struct _mp_machine_spi_p_t {
MP_PROTOCOL_HEAD
void (*init)(mp_obj_base_t *obj, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args);
void (*deinit)(mp_obj_base_t *obj); // can be NULL
void (*transfer)(mp_obj_base_t *obj, size_t len, const uint8_t *src, uint8_t *dest);
} mp_machine_spi_p_t;
typedef struct _mp_machine_soft_spi_obj_t {
mp_obj_base_t base;
mp_soft_spi_obj_t spi;
} mp_machine_soft_spi_obj_t;
extern const mp_machine_spi_p_t mp_machine_soft_spi_p;
extern const mp_obj_type_t mp_machine_soft_spi_type;
extern const mp_obj_dict_t mp_machine_spi_locals_dict;
mp_obj_t mp_machine_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args);
MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_spi_read_obj);
MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_spi_readinto_obj);
MP_DECLARE_CONST_FUN_OBJ_2(mp_machine_spi_write_obj);
MP_DECLARE_CONST_FUN_OBJ_3(mp_machine_spi_write_readinto_obj);
#endif // MICROPY_INCLUDED_EXTMOD_MACHINE_SPI_H

33
extmod/modujson.c
View File

@ -53,6 +53,10 @@ STATIC mp_obj_t mod_ujson_dumps(mp_obj_t obj) {
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_ujson_dumps_obj, mod_ujson_dumps);
#define JSON_DEBUG(...) (void)0
// #define JSON_DEBUG(...) mp_printf(&mp_plat_print __VA_OPT__(,) __VA_ARGS__)
// The function below implements a simple non-recursive JSON parser.
//
// The JSON specification is at http://www.ietf.org/rfc/rfc4627.txt
@ -80,6 +84,7 @@ typedef struct _ujson_stream_t {
STATIC byte ujson_stream_next(ujson_stream_t *s) {
mp_uint_t ret = s->read(s->stream_obj, &s->cur, 1, &s->errcode);
JSON_DEBUG(" usjon_stream_next err:%2d cur: %c \n", s->errcode, s->cur);
if (s->errcode != 0) {
mp_raise_OSError(s->errcode);
}
@ -89,9 +94,10 @@ STATIC byte ujson_stream_next(ujson_stream_t *s) {
return s->cur;
}
STATIC mp_obj_t mod_ujson_load(mp_obj_t stream_obj) {
STATIC mp_obj_t _mod_ujson_load(mp_obj_t stream_obj, bool return_first_json) {
const mp_stream_p_t *stream_p = mp_get_stream_raise(stream_obj, MP_STREAM_OP_READ);
ujson_stream_t s = {stream_obj, stream_p->read, 0, 0};
JSON_DEBUG("got JSON stream\n");
vstr_t vstr;
vstr_init(&vstr, 8);
mp_obj_list_t stack; // we use a list as a simple stack for nested JSON
@ -262,13 +268,18 @@ STATIC mp_obj_t mod_ujson_load(mp_obj_t stream_obj) {
}
}
success:
// eat trailing whitespace
while (unichar_isspace(S_CUR(s))) {
S_NEXT(s);
}
if (!S_END(s)) {
// unexpected chars
goto fail;
// It is legal for a stream to have contents after JSON.
// E.g., A UART is not closed after receiving an object; in load() we will
// return the first complete JSON object, while in loads() we will retain
// strict adherence to the buffer's complete semantic.
if (!return_first_json) {
while (unichar_isspace(S_CUR(s))) {
S_NEXT(s);
}
if (!S_END(s)) {
// unexpected chars
goto fail;
}
}
if (stack_top == MP_OBJ_NULL || stack.len != 0) {
// not exactly 1 object
@ -280,6 +291,10 @@ STATIC mp_obj_t mod_ujson_load(mp_obj_t stream_obj) {
fail:
mp_raise_ValueError(translate("syntax error in JSON"));
}
STATIC mp_obj_t mod_ujson_load(mp_obj_t stream_obj) {
return _mod_ujson_load(stream_obj, true);
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_ujson_load_obj, mod_ujson_load);
STATIC mp_obj_t mod_ujson_loads(mp_obj_t obj) {
@ -287,7 +302,7 @@ STATIC mp_obj_t mod_ujson_loads(mp_obj_t obj) {
const char *buf = mp_obj_str_get_data(obj, &len);
vstr_t vstr = {len, len, (char*)buf, true};
mp_obj_stringio_t sio = {{&mp_type_stringio}, &vstr, 0, MP_OBJ_NULL};
return mod_ujson_load(MP_OBJ_FROM_PTR(&sio));
return _mod_ujson_load(MP_OBJ_FROM_PTR(&sio), false);
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_ujson_loads_obj, mod_ujson_loads);

1
extmod/ulab Submodule

@ -0,0 +1 @@
Subproject commit 48cb939839fcf091fcdcdf742530b1b650066a15

1
frozen/Adafruit_CircuitPython_BLE Submodule

@ -0,0 +1 @@
Subproject commit 5d584576ef79ca36506e6c7470e7ac5204cf0a8d

1
frozen/Adafruit_CircuitPython_BLE_Apple_Notification_Center Submodule

@ -0,0 +1 @@
Subproject commit 3ffb3f02d2046910e09d1f5a74721bd1a4cdf8cf

2
frozen/Adafruit_CircuitPython_BusDevice

@ -1 +1 @@
Subproject commit 0b0d1e999a6c7944e55bed59a30ccc21b3c96666
Subproject commit e9411c4244984b69ec6928370ede40cec014c10b

2
frozen/Adafruit_CircuitPython_CircuitPlayground

@ -1 +1 @@
Subproject commit 2cf0f40ab818fddbc2cecf3ec495ed16067c5f7e
Subproject commit e9f15d61502f34173912ba271aaaf9446dae8da1

2
frozen/Adafruit_CircuitPython_Crickit

@ -1 +1 @@
Subproject commit 09bd10e94894a4eec7e3a02b51ffb5d8581b3024
Subproject commit 0e1230676a54da17a309d1dfffdd7fa90240191c

1
frozen/Adafruit_CircuitPython_DRV2605 Submodule

@ -0,0 +1 @@
Subproject commit 7914a6390318687bb8e2e9c4119aa932fea01531

1
frozen/Adafruit_CircuitPython_DS3231 Submodule

@ -0,0 +1 @@
Subproject commit 0d49a1fcd96c13a94e8bdf26f92abe79b8517906

2
frozen/Adafruit_CircuitPython_DotStar

@ -1 +1 @@
Subproject commit 84eadeafa9144829b8c6faf903b4282d58a77353
Subproject commit f4f66fa03990428c239eac68d37f79a7245b4cd3

2
frozen/Adafruit_CircuitPython_ESP32SPI

@ -1 +1 @@
Subproject commit f523b2316bc3e25220b88c5435868c6a5880dfab
Subproject commit 94b03517c1f4ff68cc2bb09b0963f7e7e3ce3d04

1
frozen/Adafruit_CircuitPython_FocalTouch Submodule

@ -0,0 +1 @@
Subproject commit 72968d3546f9d6c5af138d4c179343007cb9662c

2
frozen/Adafruit_CircuitPython_HID

@ -1 +1 @@
Subproject commit f044548d6d3aa21650b50232bb16e0b29f540b8f
Subproject commit 65fb213b8c554181d54b77f75335e16e2f4c0987

2
frozen/Adafruit_CircuitPython_IRRemote

@ -1 +1 @@
Subproject commit 9dac9628e48675308d447b70b2005f7d1f0ddf6b
Subproject commit d435fc9a9d90cb063608ae037bf5284b33bc5e84

2
frozen/Adafruit_CircuitPython_LIS3DH

@ -1 +1 @@
Subproject commit 42a55eafcb29f563b31e23af902c31dac8289900
Subproject commit 457aba6dd59ad00502b80c9031655d3d26ecc82b

1
frozen/Adafruit_CircuitPython_LSM6DS Submodule

@ -0,0 +1 @@
Subproject commit ee8f2187d4795b08ae4aa60558f564d26c997be9

2
frozen/Adafruit_CircuitPython_Motor

@ -1 +1 @@
Subproject commit ddcd1e7154f1b27f9a87daffb6e691e1e7051b64
Subproject commit 5fd72fb963c4a0318d29282ca2cc988f19787fda

2
frozen/Adafruit_CircuitPython_NeoPixel

@ -1 +1 @@
Subproject commit 10db851c81873fd8db207ff0c4d9342426ee25a4
Subproject commit 59add970cc66f9b0f2d45082e86b25650843a159

2
frozen/Adafruit_CircuitPython_Register

@ -1 +1 @@
Subproject commit c525eedeb0d20c9829febfbf621eab707da71f8a
Subproject commit 56358b4494da825cd99a56a854119f926abca670

2
frozen/Adafruit_CircuitPython_Requests

@ -1 +1 @@
Subproject commit e8a759719e94c69a01f9e07d418ca6db39114db3
Subproject commit 41de8b3c05dd78d7be8893a0f6cb47a7e9b421a2

2
frozen/Adafruit_CircuitPython_SD

@ -1 +1 @@
Subproject commit efd548b1e36c534bbce494f4cb0d9a625dd170cd
Subproject commit 96ee9954a3099ee9c9d7d7b7747f30ab3c6a45bf

2
frozen/Adafruit_CircuitPython_Thermistor

@ -1 +1 @@
Subproject commit ac83a3dc703ec50b2236c773d22c47a0c0aaba43
Subproject commit b5bbdbd56ca205c581ba2c84d927ef99befce88e

2
frozen/Adafruit_CircuitPython_seesaw

@ -1 +1 @@
Subproject commit dc01285aa45dd8260bb3ae35a657e4cdcbf325b8
Subproject commit 76c0dd13294ce8ae0518cb9882dcad5d3668977e

2
frozen/circuitpython-stage

@ -1 +1 @@
Subproject commit 19a66d79f0650a15e502464b42e16692365eab36
Subproject commit 0d2c083a2fb57a1562d4806775f45273abbfbfae

1
lib/libm/erf_lgamma.c
View File

@ -24,6 +24,7 @@
*/
#include "fdlibm.h"
#pragma GCC diagnostic ignored "-Wfloat-equal"
#define __ieee754_logf logf

2
lib/libm/log1pf.c
View File

@ -18,6 +18,8 @@
#include "libm.h"
#pragma GCC diagnostic ignored "-Wfloat-equal"
static const float
ln2_hi = 6.9313812256e-01, /* 0x3f317180 */
ln2_lo = 9.0580006145e-06, /* 0x3717f7d1 */

3
lib/libm/math.c
View File

@ -50,6 +50,9 @@ float copysignf(float x, float y) {
static const float _M_LN10 = 2.30258509299404; // 0x40135d8e
float log10f(float x) { return logf(x) / (float)_M_LN10; }
#undef _M_LN2
static const float _M_LN2 = 0.6931472;
float log2f(float x) { return logf(x) / (float)_M_LN2; }
float tanhf(float x) {
if (isinf(x)) {

2
lib/libm_dbl/__signbit.c
View File

@ -8,5 +8,3 @@ int __signbitd(double x)
} y = { x };
return y.i>>63;
}

1
lib/memzip/README.md
View File

@ -25,4 +25,3 @@ $(BUILD)/memzip-files.c: $(shell find ${MEMZIP_DIR} -type f)
@$(ECHO) "Creating $@"
$(Q)$(PYTHON) $(MAKE_MEMZIP) --zip-file $(BUILD)/memzip-files.zip --c-file $@ $(MEMZIP_DIR)
```

1
lib/memzip/lexermemzip.c
View File

@ -16,4 +16,3 @@ mp_lexer_t *mp_lexer_new_from_file(const char *filename)
return mp_lexer_new_from_str_len(qstr_from_str(filename), (const char *)data, (mp_uint_t)len, 0);
}

1
lib/memzip/make-memzip.py
View File

@ -76,4 +76,3 @@ def main():
if __name__ == "__main__":
main()

6
lib/oofatfs/ff.c
View File

@ -3382,11 +3382,7 @@ FRESULT f_read (
if (!sect) ABORT(fs, FR_INT_ERR);
sect += csect;
cc = btr / SS(fs); /* When remaining bytes >= sector size, */
if (cc
#if _FS_DISK_READ_ALIGNED
&& (((int)rbuff & 3) == 0)
#endif
) {/* Read maximum contiguous sectors directly */
if (cc) {/* Read maximum contiguous sectors directly */
if (csect + cc > fs->csize) { /* Clip at cluster boundary */
cc = fs->csize - csect;
}

6
lib/oofatfs/ffconf.h
View File

@ -343,12 +343,6 @@
/ SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
/ included somewhere in the scope of ff.h. */
// Set to nonzero if buffers passed to disk_read have a word alignment
// restriction
#ifndef _FS_DISK_READ_ALIGNED
#define _FS_DISK_READ_ALIGNED 0
#endif
/* #include <windows.h> // O/S definitions */

1
lib/oofatfs/option/ccsbcs.c
View File

@ -385,4 +385,3 @@ WCHAR ff_wtoupper ( /* Returns upper converted character */
return chr;
}

1
lib/protomatter Submodule

@ -0,0 +1 @@
Subproject commit 9f71088d2c32206c6f0495704ae0c040426d5764

1
lib/tinytest/README
View File

@ -15,4 +15,3 @@ You can get the latest version using Git, by pulling from
Patches are welcome. Patches that turn this from tinytest to hugetest
will not be applied. If you want a huge test framework, use CUnit.

1
lib/tinytest/tinytest.c
View File

@ -474,4 +474,3 @@ tinytest_set_test_skipped_(void)
if (cur_test_outcome==OK)
cur_test_outcome = SKIP;
}

2
lib/tinyusb

@ -1 +1 @@
Subproject commit 1f95f439e11f519e69d75a4a8b7b9f28eaf5060e
Subproject commit dc5445e2f45cb348a44fe24fc1be4bc8b5ba5bab

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locale/ID.po
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locale/circuitpython.pot
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locale/cs.po Normal file
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17
main.c
View File

@ -105,12 +105,18 @@ void start_mp(supervisor_allocation* heap) {
// Stack limit should be less than real stack size, so we have a chance
// to recover from limit hit. (Limit is measured in bytes.)
mp_stack_ctrl_init();
mp_stack_set_limit(stack_alloc->length - 1024);
if (stack_alloc != NULL) {
mp_stack_set_limit(stack_alloc->length - 1024);
}
#if MICROPY_MAX_STACK_USAGE
// _ezero (same as _ebss) is an int, so start 4 bytes above it.
mp_stack_set_bottom(stack_alloc->ptr);
mp_stack_fill_with_sentinel();
if (stack_alloc != NULL) {
mp_stack_set_bottom(stack_alloc->ptr);
mp_stack_fill_with_sentinel();
}
#endif
// Sync the file systems in case any used RAM from the GC to cache. As soon
@ -179,7 +185,7 @@ bool maybe_run_list(const char ** filenames, pyexec_result_t* exec_result) {
}
mp_hal_stdout_tx_str(filename);
const compressed_string_t* compressed = translate(" output:\n");
char decompressed[compressed->length];
char decompressed[decompress_length(compressed)];
decompress(compressed, decompressed);
mp_hal_stdout_tx_str(decompressed);
pyexec_file(filename, exec_result);
@ -430,6 +436,9 @@ int __attribute__((used)) main(void) {
// displays init after filesystem, since they could share the flash SPI
board_init();
// Start the debug serial
serial_early_init();
// Reset everything and prep MicroPython to run boot.py.
reset_port();
reset_board();

1
mpy-cross/.gitignore vendored
View File

@ -3,4 +3,5 @@
/mpy-cross.static
/mpy-cross.static.exe
/mpy-cross.static-raspbian
/mpy-cross.fuzz
/pitools

6
mpy-cross/Makefile.fuzz Normal file
View File

@ -0,0 +1,6 @@
PROG=mpy-cross.fuzz
BUILD=build-static
STATIC_BUILD=1
CC=afl-clang-fast
include mpy-cross.mk

81
ports/atmel-samd/Makefile
View File

@ -86,17 +86,27 @@ INC += -I. \
# NDEBUG disables assert() statements. This reduces code size pretty dramatically, per tannewt.
ifeq ($(CHIP_FAMILY), samd21)
PERIPHERALS_CHIP_FAMILY=samd21
CFLAGS += -Os -DNDEBUG
# TinyUSB defines
CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD21 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=128 -DCFG_TUD_MSC_BUFSIZE=512
endif
ifeq ($(CHIP_FAMILY), samd51)
PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x
CFLAGS += -Os -DNDEBUG
# TinyUSB defines
CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD51 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024
endif
ifeq ($(CHIP_FAMILY), same54)
PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x
CFLAGS += -Os -DNDEBUG
# TinyUSB defines
CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD51 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024
endif
$(echo PERIPHERALS_CHIP_FAMILY=$(PERIPHERALS_CHIP_FAMILY))
#Debugging/Optimization
ifeq ($(DEBUG), 1)
CFLAGS += -ggdb
@ -114,7 +124,7 @@ else
# Do a default shrink for small builds.
ifndef CFLAGS_INLINE_LIMIT
ifeq ($(CIRCUITPY_SMALL_BUILD),1)
ifeq ($(CIRCUITPY_FULL_BUILD),0)
CFLAGS_INLINE_LIMIT = 50
endif
endif
@ -125,7 +135,7 @@ else
CFLAGS += -flto -flto-partition=none
ifeq ($(CIRCUITPY_SMALL_BUILD),1)
ifeq ($(CIRCUITPY_FULL_BUILD),0)
CFLAGS += --param inline-unit-growth=15 --param max-inline-insns-auto=20
endif
@ -134,7 +144,7 @@ else
endif
endif
CFLAGS += $(INC) -Wall -Werror -std=gnu11 -nostdlib $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT)
CFLAGS += $(INC) -Wall -Werror -std=gnu11 -nostdlib -fshort-enums $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT)
ifeq ($(CHIP_FAMILY), samd21)
CFLAGS += \
@ -152,12 +162,21 @@ CFLAGS += \
-mcpu=cortex-m4 \
-mfloat-abi=hard \
-mfpu=fpv4-sp-d16 \
-DSAMD51
-DSAM_D5X_E5X -DSAMD51
endif
ifeq ($(CHIP_FAMILY), same54)
CFLAGS += \
-mthumb \
-mabi=aapcs-linux \
-mcpu=cortex-m4 \
-mfloat-abi=hard \
-mfpu=fpv4-sp-d16 \
-DSAM_D5X_E5X -DSAME54
endif
LDFLAGS = $(CFLAGS) -nostartfiles -fshort-enums -Wl,-nostdlib -Wl,-T,$(GENERATED_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs
LDFLAGS = $(CFLAGS) -nostartfiles -Wl,-nostdlib -Wl,-T,$(GENERATED_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs
LIBS := -lgcc -lc
# Use toolchain libm if we're not using our own.
@ -171,6 +190,9 @@ BOOTLOADER_SIZE := 0x2000
else ifeq ($(CHIP_FAMILY), samd51)
LDFLAGS += -mthumb -mcpu=cortex-m4
BOOTLOADER_SIZE := 0x4000
else ifeq ($(CHIP_FAMILY), same54)
LDFLAGS += -mthumb -mcpu=cortex-m4
BOOTLOADER_SIZE := 0x4000
endif
SRC_ASF := \
@ -194,7 +216,6 @@ SRC_ASF := \
hpl/gclk/hpl_gclk.c \
hpl/nvmctrl/hpl_nvmctrl.c \
hpl/pm/hpl_pm.c \
hpl/rtc/hpl_rtc.c \
hpl/sercom/hpl_sercom.c \
hpl/systick/hpl_systick.c \
hal/utils/src/utils_list.c \
@ -206,6 +227,15 @@ SRC_ASF += \
hpl/sysctrl/hpl_sysctrl.c \
else ifeq ($(CHIP_FAMILY), samd51)
SRC_ASF += \
hal/src/hal_rand_sync.c \
hpl/core/hpl_core_m4.c \
hpl/mclk/hpl_mclk.c \
hpl/osc32kctrl/hpl_osc32kctrl.c \
hpl/oscctrl/hpl_oscctrl.c \
hpl/trng/hpl_trng.c \
else ifeq ($(CHIP_FAMILY), same54)
SRC_ASF += \
hal/src/hal_rand_sync.c \
hpl/core/hpl_core_m4.c \
@ -216,6 +246,14 @@ SRC_ASF += \
endif
ifeq ($(CIRCUITPY_SDIOIO),1)
SRC_ASF += \
hal/src/hal_mci_sync.c \
hpl/sdhc/hpl_sdhc.c \
$(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sdhc/hpl_sdhc.o: CFLAGS += -Wno-cast-align
endif
SRC_ASF := $(addprefix asf4/$(CHIP_FAMILY)/, $(SRC_ASF))
SRC_C = \
@ -241,15 +279,15 @@ SRC_C = \
lib/utils/stdout_helpers.c \
lib/utils/sys_stdio_mphal.c \
mphalport.c \
peripherals/samd/$(CHIP_FAMILY)/adc.c \
peripherals/samd/$(CHIP_FAMILY)/cache.c \
peripherals/samd/$(CHIP_FAMILY)/clocks.c \
peripherals/samd/$(CHIP_FAMILY)/dma.c \
peripherals/samd/$(CHIP_FAMILY)/events.c \
peripherals/samd/$(CHIP_FAMILY)/external_interrupts.c \
peripherals/samd/$(CHIP_FAMILY)/pins.c \
peripherals/samd/$(CHIP_FAMILY)/sercom.c \
peripherals/samd/$(CHIP_FAMILY)/timers.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/adc.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/cache.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/dma.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/events.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/external_interrupts.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/pins.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/sercom.c \
peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/timers.c \
peripherals/samd/clocks.c \
peripherals/samd/dma.c \
peripherals/samd/events.c \
@ -258,9 +296,11 @@ SRC_C = \
peripherals/samd/timers.c \
reset.c \
supervisor/shared/memory.c \
tick.c \
timer_handler.c \
ifeq ($(CIRCUITPY_SDIOIO),1)
SRC_C += ports/atmel-samd/sd_mmc/sd_mmc.c
endif
ifeq ($(CIRCUITPY_NETWORK),1)
CFLAGS += -DMICROPY_PY_NETWORK=1
@ -290,7 +330,7 @@ endif
# The smallest SAMD51 packages don't have I2S. Everything else does.
ifeq ($(CIRCUITPY_AUDIOBUSIO),1)
SRC_C += peripherals/samd/i2s.c peripherals/samd/$(CHIP_FAMILY)/i2s.c
SRC_C += peripherals/samd/i2s.c peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/i2s.c
endif
SRC_COMMON_HAL_EXPANDED = $(addprefix shared-bindings/, $(SRC_COMMON_HAL)) \
@ -306,7 +346,6 @@ SRC_SHARED_MODULE_EXPANDED = $(addprefix shared-bindings/, $(SRC_SHARED_MODULE))
# Doing a $(sort ...) removes duplicates as part of sorting.
SRC_COMMON_HAL_SHARED_MODULE_EXPANDED = $(sort $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED))
SRC_S = supervisor/$(CHIP_FAMILY)_cpu.s
OBJ = $(PY_O) $(SUPERVISOR_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
@ -318,9 +357,13 @@ endif
OBJ += $(addprefix $(BUILD)/, $(SRC_S:.s=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
SRC_QSTR += $(HEADER_BUILD)/sdiodata.h
$(HEADER_BUILD)/sdiodata.h: $(TOP)/tools/mksdiodata.py | $(HEADER_BUILD)
$(Q)$(PYTHON3) $< > $@
SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
# Sources that only hold QSTRs after pre-processing.
SRC_QSTR_PREPROCESSOR += peripherals/samd/$(CHIP_FAMILY)/clocks.c
SRC_QSTR_PREPROCESSOR += peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c
all: $(BUILD)/firmware.bin $(BUILD)/firmware.uf2

238
ports/atmel-samd/README.rst
View File

@ -1,246 +1,24 @@
SAMD21x18
=========
SAMD21 and SAMD51
==================
This port brings MicroPython to SAMD21x18 based development boards under the name
CircuitPython. Supported boards include:
This port supports many development boards that utilize SAMD21 and SAMD51 chips. See
https://circuitpython.org/downloads for all supported boards.
- Adafruit CircuitPlayground Express
- Adafruit Feather M0 Basic
- Adafruit Feather M0 Express
- Adafruit Metro M0 Express
- Adafruit M0 Bluefruit LE
- Arduino Zero
- Arduino MKR Zero
- Arduino Nano 33 IoT
Pinout
------
All of the boards share the same core pin functionality but call pins by
different names. The table below matches the pin order in
`the datasheet <http://ww1.microchip.com/downloads/en/DeviceDoc/40001882A.pdf>`_
and omits the pins only available on the largest package because all supported
boards use smaller version.
===================== =================== =================== =============== =========================== ====================== ================ ================== ========================= ================ ================================ ====================== ================
`microcontroller.pin` `board`
--------------------- -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Datasheet arduino_mkrzero arduino_nano_33_iot arduino_zero circuitplayground_express feather_m0_adalogger feather_m0_basic feather_m0_express gemma_m0 metro_m0_express sparkfun_samd21_mini sparkfun_samd21_dev trinket_m0
===================== =================== =================== =============== =========================== ====================== ================ ================== ========================= ================ ================================ ====================== ================
PA00 ``ACCELEROMETER_SDA`` ``APA102_MOSI`` ``APA102_MOSI``
PA01 ``ACCELEROMETER_SCL`` ``APA102_SCK`` ``APA102_SCK``
PA02 ``A0`` ``A0`` ``A0`` ``A0`` / ``SPEAKER`` ``A0`` ``A0`` ``A0`` ``A0`` / ``D1`` ``A0`` ``A0`` ``A0`` ``D1`` / ``A0``
PA03
PB08 ``L`` ``A4`` / ``SDA`` ``A1`` ``A7`` / ``TX`` ``A1`` ``A1`` ``A1`` ``A1`` ``A1`` ``A1``
PB09 ``BATTERY`` ``A5`` / ``SCL`` ``A2`` ``A6`` / ``RX`` ``A2`` ``A2`` ``A2`` ``A2`` ``A2`` ``A2``
PA04 ``A3`` ``D6`` ``A3`` ``IR_PROXIMITY`` ``A3`` ``A3`` ``A3`` ``D0`` / ``TX`` / ``SDA`` ``A3`` ``A3`` ``A3``
PA05 ``A4`` ``D5`` ``A4`` ``A1`` ``A4`` ``A4`` ``A4`` ``D2`` / ``RX`` / ``SCL`` ``A4`` ``A4``
PA06 ``A5`` ``D7`` ``D8`` ``A2`` ``D8`` / ``GREEN_LED`` ``NEOPIXEL`` ``D8`` ``D8`` ``D8`` ``D4`` / ``TX``
PA07 ``A6`` ``D4`` ``D9`` ``A3`` ``D9`` ``D9`` ``D9`` ``D9`` ``D9`` ``D9`` ``D3`` / ``RX``
PA08 ``D11`` / ``SDA`` ``ESP_RESET`` ``D4`` ``MICROPHONE_DO`` ``D4`` / ``SD_CS`` ``D4`` ``D4`` ``D4`` ``D0`` / ``SDA``
PA09 ``D12`` / ``SCL`` ``A6`` ``D3`` ``TEMPERATURE`` / ``A9`` ``D3`` ``D3`` ``D3`` ``D2`` / ``SCL``
PA10 ``D2`` ``A3`` ``D1`` / ``TX`` ``MICROPHONE_SCK`` ``D1`` / ``TX`` ``D1`` / ``TX`` ``D1`` / ``TX`` ``D1`` / ``TX`` ``D1`` / ``TX`` ``D1`` / ``TX`` ``D13``
PA11 ``D3`` ``A2`` ``D0`` / ``RX`` ``LIGHT`` / ``A8`` ``D0`` / ``RX`` ``D0`` / ``RX`` ``D0`` / ``RX`` ``D0`` / ``RX`` ``D0`` / ``RX`` ``D0`` / ``RX``
PB10 ``D4`` ``D2`` ``MOSI`` ``MOSI`` ``MOSI`` ``MOSI`` ``MOSI`` ``MOSI``
PB11 ``D5`` ``D3`` ``SCK`` ``SCK`` ``SCK`` ``SCK`` ``SCK`` ``SCK``
PA12 ``SD_MOSI`` ``ESP_MOSI`` ``MISO`` ``REMOTEIN`` / ``IR_RX`` ``MISO`` ``MISO`` ``MISO`` ``MISO`` ``MISO``
PA13 ``SD_SCK`` ``ESP_MISO`` ``ACCELEROMETER_INTERRUPT`` ``FLASH_CS`` ``D38``
PA14 ``SD_CS`` ``ESP_CS`` ``D2`` ``BUTTON_B`` / ``D5`` ``D2`` ``D2`` ``D2``
PA15 ``SD_MISO`` ``ESP_SCK`` ``D5`` ``SLIDE_SWITCH`` / ``D7`` ``D5`` ``D5`` ``D5`` ``D5`` ``D5`` ``D5``
PA16 ``D8`` / ``MOSI`` ``D11`` / ``MOSI`` ``D11`` ``MISO`` ``D11`` ``D11`` ``D11`` ``D11`` ``D11`` / ``MOSI`` ``D11``
PA17 ``D9`` / ``SCK`` ``D13`` / ``SCK`` ``D13`` ``D13`` ``D13`` / ``RED_LED`` ``D13`` ``D13`` ``D13`` ``D13`` / ``SCK`` / ``BLUE_LED`` ``D13`` / ``BLUE_LED``
PA18 ``D8`` ``D10`` ``D10`` ``D10`` ``D10`` ``D10`` ``D10`` ``D10``
PA19 ``D10`` / ``MISO`` ``D12`` / ``MISO`` ``D12`` ``D12`` ``D12`` ``D12`` ``D12`` ``D12`` / ``MISO`` ``D12``
PA20 ``D6`` ``D9`` ``D6`` ``MOSI`` ``D6`` ``D6`` ``D6`` ``D6`` ``D6`` ``D6``
PA21 ``D7`` ``D10`` ``D7`` ``SCK`` ``D7`` / ``SD_CD`` ``D7`` ``D7`` ``D7``
PA22 ``D0`` ``ESP_TX`` ``SDA`` ``SDA`` ``SDA`` ``SDA`` ``SDA`` ``SDA`` ``SDA``
PA23 ``D1`` ``ESP_RX`` ``SCL`` ``REMOTEOUT`` / ``IR_TX`` ``SCL`` ``SCL`` ``SCL`` ``L`` / ``D13`` ``SCL`` ``SCL`` ``SCL``
PA24
PA25
PB22 ``D14`` / ``TX`` ``D1`` / ``TX`` ``FLASH_CS`` ``D30`` / ``TX1``
PB23 ``D13`` / ``RX`` ``D0`` / ``RX`` ``NEOPIXEL`` / ``D8`` ``D31`` / ``RX1``
PA27 ``SD_CD`` ``ESP_GPIO0`` ``GREEN_LED`` ``GREEN_LED``
PA28 ``ESP_BUSY`` ``BUTTON_A`` / ``D4``
PA29
PA30 ``SPEAKER_ENABLE`` ``NEOPIXEL``
PA31
PB02 ``A1`` ``A1`` ``A5`` ``A5`` / ``SDA`` ``A5`` ``A5`` ``A5`` ``A5`` ``A5``
PB03 ``A2`` ``A7`` ``A4`` / ``SCL`` ``YELLOW_LED`` ``YELLOW_LED``
===================== =================== =================== =============== =========================== ====================== ================ ================== ========================= ================ ================================ ====================== ================
Here is a table about which pins can do what in CircuitPython terms. However,
just because something is listed, doesn't mean it will always work. Existing use
of other pins and functionality will impact your ability to use a pin for your
desired purpose. For example, only certain combinations of SPI pins will work
because they use shared hardware internally.
===================== ======== ========= ========= ======= ======= ======= ========= ========= ======= ========== ========== ========= ========= ========= ============ ======= ======= =========
`microcontroller.pin` `analogio` `audioio` `bitbangio` `busio` `digitalio` `pulseio` `touchio`
--------------------- ------------------- --------- ------------------------- -------------------------------------------------------------------------------------- ------------ ---------------- ---------
Datasheet AnalogIn AnalogOut AudioOut I2C OneWire SPI I2C - SDA I2C - SCL OneWire SPI - MISO SPI - MOSI SPI - SCK UART - RX UART - TX DigitalInOut PulseIn PWMOut TouchIn
===================== ======== ========= ========= ======= ======= ======= ========= ========= ======= ========== ========== ========= ========= ========= ============ ======= ======= =========
PA00 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA01 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA02 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA03 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PB08 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PB09 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA04 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA05 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA06 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA07 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA08 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA09 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA10 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA11 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PB10 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PB11 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA12 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA13 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA14 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA15 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA16 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA17 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA18 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA19 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA20 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA21 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA22 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA23 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA24
PA25
PB22 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PB23 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA27 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA28 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA29 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA30 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PA31 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PB02 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
PB03 **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes** **Yes**
===================== ======== ========= ========= ======= ======= ======= ========= ========= ======= ========== ========== ========= ========= ========= ============ ======= ======= =========
Setup
-----
An ARM compiler is required for the build, along with the associated binary
utilities. They can be installed as follows:
- Ubuntu
.. code-block:: shell
sudo add-apt-repository ppa:team-gcc-arm-embedded/ppa
sudo apt-get install gcc-arm-embedded
- Arch Linux
.. code-block:: shell
sudo pacman -S arm-none-eabi-gcc arm-none-eabi-newlib
For other systems, the `GNU Arm Embedded Toolchain <https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads>`_
may be available in binary form.
The latest available package from team-gcc-arm-embedded is used to produce the
binaries shipped by AdaFruit. Other compiler versions, particularly older
ones, may not work properly. In particular, the ``gcc-arm-none-eabi`` package
in Debian Stretch is too old.
The compiler can be changed using the ``CROSS_COMPILE`` variable when invoking
``make``.
Building
--------
Before building the firmware for a given board, there are two additional steps.
These commands should be executed from the root directory of the repository
(``circuitpython/``).
1. There are various submodules that reside in different repositories. In order
to have these submodules locally, you must pull them into your clone, using:
.. code-block:: shell
git submodule update --init --recursive
2. The MicroPython cross-compiler must be built; it will be used to pre-compile
some of the built-in scripts to bytecode. The cross-compiler is built and
run on the host machine, using:
.. code-block:: shell
make -C mpy-cross
For build instructions see this guide: https://learn.adafruit.com/building-circuitpython/
Build commands are run from the ``circuitpython/ports/atmel-samd`` directory.
To build for a given board you must specify it by setting ``BOARD``. For example:
.. code-block:: shell
make BOARD=feather_m0_basic
Board names are the directory names in the `boards <https://github.com/adafruit/circuitpython/tree/master/ports/atmel-samd/boards>`_ folder.
Deploying
Debugging
---------
Arduino Bootloader
^^^^^^^^^^^^^^^^^^
For debugging instructions see this guide: https://learn.adafruit.com/debugging-the-samd21-with-gdb
If your board has an existing Arduino bootloader on it then you can use bossac
to flash MicroPython. First, activate the bootloader. On Adafruit Feathers you
can double click the reset button and the #13 will fade in and out. Finally,
run bossac:
tools/bossac_osx -e -w -v -b -R build-feather_m0_basic/firmware.bin
No Bootloader via GDB
^^^^^^^^^^^^^^^^^^^^^
This method works for loading MicroPython onto the Arduino Zero via the
programming port rather than the native USB port.
Note: These instructions are tested on Mac OSX and will vary for different
platforms.
openocd -f ~/Library/Arduino15/packages/arduino/hardware/samd/1.6.6/variants/arduino_zero/openocd_scripts/arduino_zero.cfg
In another terminal from ``micropython/atmel-samd``:
arm-none-eabi-gdb build-arduino_zero/firmware.elf
(gdb) tar ext :3333
...
(gdb) load
...
(gdb) monitor reset init
...
(gdb) continue
Connecting
----------
Serial
^^^^^^
All boards are currently configured to work over USB rather than UART. To
connect to it from OSX do something like this:
screen /dev/tty.usbmodem142422 115200
You may not see a prompt immediately because it doesn't know you connected. To
get one either hit enter to get `>>>` or do CTRL-B to get the full header.
Mass storage
^^^^^^^^^^^^
All boards will also show up as a mass storage device. Make sure to eject it
before resetting or disconnecting the board.
Port Specific modules
---------------------
.. toctree::
bindings/samd/__init__
../../shared-bindings/samd/index

2
ports/atmel-samd/asf4

@ -1 +1 @@
Subproject commit 039b5f3bbc3f4ba4421e581db290560d59fef625
Subproject commit 35a1525796c7ef8a3893d90befdad2f267fca20e

24
ports/atmel-samd/asf4_conf/samd51/hpl_sdhc_config.h Normal file
View File

@ -0,0 +1,24 @@
/* Auto-generated config file hpl_sdhc_config.h */
#ifndef HPL_SDHC_CONFIG_H
#define HPL_SDHC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include "peripheral_clk_config.h"
#ifndef CONF_BASE_FREQUENCY
#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
#endif
// <o> Clock Generator Select
// <0=> Divided Clock mode
// <1=> Programmable Clock mode
// <i> This defines the clock generator mode in the SDCLK Frequency Select field
// <id> sdhc_clk_gsel
#ifndef CONF_SDHC0_CLK_GEN_SEL
#define CONF_SDHC0_CLK_GEN_SEL 0
#endif
// <<< end of configuration section >>>
#endif // HPL_SDHC_CONFIG_H

164
ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
View File

@ -1001,6 +1001,170 @@
#define CONF_GCLK_USB_FREQUENCY 48000000
#endif
// <h> SDHC Clock Settings
// <y> SDHC Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for SDHC.
// <id> sdhc_gclk_selection
#ifndef CONF_GCLK_SDHC0_SRC
#define CONF_GCLK_SDHC0_SRC GCLK_GENCTRL_SRC_DFLL_Val
#endif
// <y> SDHC clock slow source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for SDHC.
// <id> sdhc_slow_gclk_selection
#ifndef CONF_GCLK_SDHC0_SLOW_SRC
#define CONF_GCLK_SDHC0_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
#endif
// </h>
/**
* \def SDHC FREQUENCY
* \brief SDHC's Clock frequency
*/
#ifndef CONF_SDHC0_FREQUENCY
#define CONF_SDHC0_FREQUENCY 12000000
#endif
/**
* \def SDHC FREQUENCY
* \brief SDHC's Clock slow frequency
*/
#ifndef CONF_SDHC0_SLOW_FREQUENCY
#define CONF_SDHC0_SLOW_FREQUENCY 12000000
#endif
// <h> SDHC Clock Settings
// <y> SDHC Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for SDHC.
// <id> sdhc_gclk_selection
#ifndef CONF_GCLK_SDHC1_SRC
#define CONF_GCLK_SDHC1_SRC GCLK_GENCTRL_SRC_DFLL_Val
#endif
// <y> SDHC clock slow source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for SDHC.
// <id> sdhc_slow_gclk_selection
#ifndef CONF_GCLK_SDHC1_SLOW_SRC
#define CONF_GCLK_SDHC1_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
#endif
// </h>
/**
* \def SDHC FREQUENCY
* \brief SDHC's Clock frequency
*/
#ifndef CONF_SDHC1_FREQUENCY
#define CONF_SDHC1_FREQUENCY 12000000
#endif
/**
* \def SDHC FREQUENCY
* \brief SDHC's Clock slow frequency
*/
#ifndef CONF_SDHC1_SLOW_FREQUENCY
#define CONF_SDHC1_SLOW_FREQUENCY 12000000
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H

303
ports/atmel-samd/asf4_conf/same54/hpl_adc_config.h Normal file
View File

@ -0,0 +1,303 @@
/* Auto-generated config file hpl_adc_config.h */
#ifndef HPL_ADC_CONFIG_H
#define HPL_ADC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_ADC_0_ENABLE
#define CONF_ADC_0_ENABLE 1
#endif
// <h> Basic Configuration
// <o> Conversion Result Resolution
// <0x0=>12-bit
// <0x1=>16-bit (averaging must be enabled)
// <0x2=>10-bit
// <0x3=>8-bit
// <i> Defines the bit resolution for the ADC sample values (RESSEL)
// <id> adc_resolution
#ifndef CONF_ADC_0_RESSEL
#define CONF_ADC_0_RESSEL 0x0
#endif
// <o> Reference Selection
// <0x0=>Internal bandgap reference
// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
// <0x3=>VDDANA
// <0x4=>External reference A
// <0x5=>External reference B
// <0x6=>External reference C
// <i> Select the reference for the ADC (REFSEL)
// <id> adc_reference
#ifndef CONF_ADC_0_REFSEL
#define CONF_ADC_0_REFSEL 0x0
#endif
// <o> Prescaler configuration
// <0x0=>Peripheral clock divided by 2
// <0x1=>Peripheral clock divided by 4
// <0x2=>Peripheral clock divided by 8
// <0x3=>Peripheral clock divided by 16
// <0x4=>Peripheral clock divided by 32
// <0x5=>Peripheral clock divided by 64
// <0x6=>Peripheral clock divided by 128
// <0x7=>Peripheral clock divided by 256
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
// <id> adc_prescaler
#ifndef CONF_ADC_0_PRESCALER
#define CONF_ADC_0_PRESCALER 0x3
#endif
// <q> Free Running Mode
// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
// <id> adc_freerunning_mode
#ifndef CONF_ADC_0_FREERUN
#define CONF_ADC_0_FREERUN 0
#endif
// <q> Differential Mode
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
// <id> adc_differential_mode
#ifndef CONF_ADC_0_DIFFMODE
#define CONF_ADC_0_DIFFMODE 0
#endif
// <o> Positive Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x08=>ADC AIN8 pin
// <0x09=>ADC AIN9 pin
// <0x0A=>ADC AIN10 pin
// <0x0B=>ADC AIN11 pin
// <0x0C=>ADC AIN12 pin
// <0x0D=>ADC AIN13 pin
// <0x0E=>ADC AIN14 pin
// <0x0F=>ADC AIN15 pin
// <0x18=>1/4 scaled core supply
// <0x19=>1/4 Scaled VBAT Supply
// <0x1A=>1/4 scaled I/O supply
// <0x1B=>Bandgap voltage
// <0x1C=>Temperature reference (PTAT)
// <0x1D=>Temperature reference (CTAT)
// <0x1E=>DAC Output
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
// <id> adc_pinmux_positive
#ifndef CONF_ADC_0_MUXPOS
#define CONF_ADC_0_MUXPOS 0x0
#endif
// <o> Negative Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x18=>Internal ground
// <0x19=>I/O ground
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
// <id> adc_pinmux_negative
#ifndef CONF_ADC_0_MUXNEG
#define CONF_ADC_0_MUXNEG 0x0
#endif
// </h>
// <e> Advanced Configuration
// <id> adc_advanced_settings
#ifndef CONF_ADC_0_ADVANCED
#define CONF_ADC_0_ADVANCED 0
#endif
// <q> Run in standby
// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
// <id> adc_arch_runstdby
#ifndef CONF_ADC_0_RUNSTDBY
#define CONF_ADC_0_RUNSTDBY 0
#endif
// <q>Debug Run
// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
// <id> adc_arch_dbgrun
#ifndef CONF_ADC_0_DBGRUN
#define CONF_ADC_0_DBGRUN 0
#endif
// <q> On Demand Control
// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
// <id> adc_arch_ondemand
#ifndef CONF_ADC_0_ONDEMAND
#define CONF_ADC_0_ONDEMAND 0
#endif
// <q> Left-Adjusted Result
// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
// <id> adc_arch_leftadj
#ifndef CONF_ADC_0_LEFTADJ
#define CONF_ADC_0_LEFTADJ 0
#endif
// <q> Reference Buffer Offset Compensation Enable
// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
// <id> adc_arch_refcomp
#ifndef CONF_ADC_0_REFCOMP
#define CONF_ADC_0_REFCOMP 0
#endif
// <q>Comparator Offset Compensation Enable
// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
// <id> adc_arch_offcomp
#ifndef CONF_ADC_0_OFFCOMP
#define CONF_ADC_0_OFFCOMP 0
#endif
// <q> Digital Correction Logic Enabled
// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
// <id> adc_arch_corren
#ifndef CONF_ADC_0_CORREN
#define CONF_ADC_0_CORREN 0
#endif
// <o> Offset Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
// <id> adc_arch_offsetcorr
#ifndef CONF_ADC_0_OFFSETCORR
#define CONF_ADC_0_OFFSETCORR 0
#endif
// <o> Gain Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
// <id> adc_arch_gaincorr
#ifndef CONF_ADC_0_GAINCORR
#define CONF_ADC_0_GAINCORR 0
#endif
// <o> Adjusting Result / Division Coefficient <0-7>
// <i> These bits define the division coefficient in 2n steps. (ADJRES)
// <id> adc_arch_adjres
#ifndef CONF_ADC_0_ADJRES
#define CONF_ADC_0_ADJRES 0x0
#endif
// <o.0..10> Number of Samples to be Collected
// <0x0=>1 sample
// <0x1=>2 samples
// <0x2=>4 samples
// <0x3=>8 samples
// <0x4=>16 samples
// <0x5=>32 samples
// <0x6=>64 samples
// <0x7=>128 samples
// <0x8=>256 samples
// <0x9=>512 samples
// <0xA=>1024 samples
// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
// <id> adc_arch_samplenum
#ifndef CONF_ADC_0_SAMPLENUM
#define CONF_ADC_0_SAMPLENUM 0x0
#endif
// <o> Sampling Time Length <0-63>
// <i> These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
// <id> adc_arch_samplen
#ifndef CONF_ADC_0_SAMPLEN
#define CONF_ADC_0_SAMPLEN 0
#endif
// <o> Window Monitor Mode
// <0x0=>No window mode
// <0x1=>Mode 1: RESULT above lower threshold
// <0x2=>Mode 2: RESULT beneath upper threshold
// <0x3=>Mode 3: RESULT inside lower and upper threshold
// <0x4=>Mode 4: RESULT outside lower and upper threshold
// <i> These bits enable and define the window monitor mode. (WINMODE)
// <id> adc_arch_winmode
#ifndef CONF_ADC_0_WINMODE
#define CONF_ADC_0_WINMODE 0x0
#endif
// <o> Window Monitor Lower Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
// <id> adc_arch_winlt
#ifndef CONF_ADC_0_WINLT
#define CONF_ADC_0_WINLT 0
#endif
// <o> Window Monitor Upper Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
// <id> adc_arch_winut
#ifndef CONF_ADC_0_WINUT
#define CONF_ADC_0_WINUT 0
#endif
// <o> Bitmask for positive input sequence <0-4294967295>
// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
// <id> adc_arch_seqen
#ifndef CONF_ADC_0_SEQEN
#define CONF_ADC_0_SEQEN 0x0
#endif
// </e>
// <e> Event Control
// <id> adc_arch_event_settings
#ifndef CONF_ADC_0_EVENT_CONTROL
#define CONF_ADC_0_EVENT_CONTROL 0
#endif
// <q> Window Monitor Event Out
// <i> Enables event output on window event (WINMONEO)
// <id> adc_arch_winmoneo
#ifndef CONF_ADC_0_WINMONEO
#define CONF_ADC_0_WINMONEO 0
#endif
// <q> Result Ready Event Out
// <i> Enables event output on result ready event (RESRDEO)
// <id> adc_arch_resrdyeo
#ifndef CONF_ADC_0_RESRDYEO
#define CONF_ADC_0_RESRDYEO 0
#endif
// <q> Invert flush Event Signal
// <i> Invert the flush event input signal (FLUSHINV)
// <id> adc_arch_flushinv
#ifndef CONF_ADC_0_FLUSHINV
#define CONF_ADC_0_FLUSHINV 0
#endif
// <q> Trigger Flush On Event
// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
// <id> adc_arch_flushei
#ifndef CONF_ADC_0_FLUSHEI
#define CONF_ADC_0_FLUSHEI 0
#endif
// <q> Invert Start Conversion Event Signal
// <i> Invert the start conversion event input signal (STARTINV)
// <id> adc_arch_startinv
#ifndef CONF_ADC_0_STARTINV
#define CONF_ADC_0_STARTINV 0
#endif
// <q> Trigger Conversion On Event
// <i> Trigger a conversion on event. (STARTEI)
// <id> adc_arch_startei
#ifndef CONF_ADC_0_STARTEI
#define CONF_ADC_0_STARTEI 0
#endif
// </e>
// <<< end of configuration section >>>
#endif // HPL_ADC_CONFIG_H

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/* Auto-generated config file hpl_dac_config.h */
#ifndef HPL_DAC_CONFIG_H
#define HPL_DAC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic configuration
// <o> Reference Selection
// <0x00=> Unbuffered external voltage reference
// <0x01=> Voltage supply
// <0x02=> Buffered external voltage reference
// <0x03=> Internal bandgap reference
// <id> dac_arch_refsel
#ifndef CONF_DAC_REFSEL
#define CONF_DAC_REFSEL 0
#endif
// <q> Differential mode
// <i> Indicates whether the differential mode is enabled or not
// <id> dac_arch_diff
#ifndef CONF_DAC_DIFF
#define CONF_DAC_DIFF 0
#endif
// </h>
// <e> Advanced Configuration
// <id> dac_advanced_settings
#ifndef CONF_DAC_ADVANCED_CONFIG
#define CONF_DAC_ADVANCED_CONFIG 0
#endif
// <q> Debug Run
// <i> Indicate whether running when CPU is halted
// <id> adc_arch_dbgrun
#ifndef CONF_DAC_DBGRUN
#define CONF_DAC_DBGRUN 1
#endif
// <h> Channel 0 configuration
// <q> Left Adjusted Data
// <i> Indicate how the data is adjusted in the Data and Data Buffer register
// <id> dac0_arch_leftadj
#ifndef CONF_DAC0_LEFTADJ
#define CONF_DAC0_LEFTADJ 1
#endif
// <o> Current control
// <0=> GCLK_DAC <= 1.2MHz (100kSPS)
// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS)
// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS)
// <i> This defines the current in output buffer according to conversion rate
// <id> dac0_arch_cctrl
#ifndef CONF_DAC0_CCTRL
#define CONF_DAC0_CCTRL 0
#endif
// <q> Run in standby
// <i> Indicates whether the DAC channel will continue running in standby sleep mode or not
// <id> dac0_arch_runstdby
#ifndef CONF_DAC0_RUNSTDBY
#define CONF_DAC0_RUNSTDBY 0
#endif
// <q> Dithering Mode
// <i> Indicate whether dithering mode is enabled
// <id> dac0_arch_ditrher
#ifndef CONF_DAC0_DITHER
#define CONF_DAC0_DITHER 0
#endif
// <o> Refresh period <0x00-0xFF>
// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us
// <id> dac0_arch_refresh
#ifndef CONF_DAC0_REFRESH
#define CONF_DAC0_REFRESH 2
#endif
// </h>
// <h> Channel 1 configuration
// <q> Left Adjusted Data
// <i> Indicate how the data is adjusted in the Data and Data Buffer register
// <id> dac1_arch_leftadj
#ifndef CONF_DAC1_LEFTADJ
#define CONF_DAC1_LEFTADJ 1
#endif
// <o> Current control
// <0=> GCLK_DAC <= 1.2MHz (100kSPS)
// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS)
// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS)
// <i> This defines the current in output buffer according to conversion rate
// <id> dac1_arch_cctrl
#ifndef CONF_DAC1_CCTRL
#define CONF_DAC1_CCTRL 0
#endif
// <q> Run in standby
// <i> Indicates whether the DAC channel will continue running in standby sleep mode or not
// <id> dac1_arch_runstdby
#ifndef CONF_DAC1_RUNSTDBY
#define CONF_DAC1_RUNSTDBY 0
#endif
// <q> Dithering Mode
// <i> Indicate whether dithering mode is enabled
// <id> dac1_arch_ditrher
#ifndef CONF_DAC1_DITHER
#define CONF_DAC1_DITHER 0
#endif
// <o> Refresh period <0x00-0xFF>
// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us
// <id> dac1_arch_refresh
#ifndef CONF_DAC1_REFRESH
#define CONF_DAC1_REFRESH 2
#endif
// </h>
// <h> Event configuration
// <o> Inversion of DAC 0 event
// <0=> Detection on rising edge pf the input event
// <1=> Detection on falling edge pf the input event
// <i> This defines the edge detection of the input event
// <id> dac_arch_invei0
#ifndef CONF_DAC_INVEI0
#define CONF_DAC_INVEI0 0
#endif
// <q> Data Buffer of DAC 0 Empty Event Output
// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not
// <id> dac_arch_emptyeo_0
#ifndef CONF_DAC_EMPTYEO0
#define CONF_DAC_EMPTYEO0 0
#endif
// <q> Start Conversion Event Input DAC 0
// <i> Indicate whether Start input event is enabled
// <id> dac_arch_startei_0
#ifndef CONF_DAC_STARTEI0
#define CONF_DAC_STARTEI0 0
#endif
// <o> Inversion of DAC 1 event
// <0=> Detection on rising edge pf the input event
// <1=> Detection on falling edge pf the input event
// <i> This defines the edge detection of the input event
// <id> dac_arch_invei1
#ifndef CONF_DAC_INVEI1
#define CONF_DAC_INVEI1 0
#endif
// <q> Data Buffer of DAC 1 Empty Event Output
// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not
// <id> dac_arch_emptyeo_1
#ifndef CONF_DAC_EMPTYEO1
#define CONF_DAC_EMPTYEO1 0
#endif
// <q> Start Conversion Event Input DAC 1
// <i> Indicate whether Start input event is enabled
// <id> dac_arch_startei_1
#ifndef CONF_DAC_STARTEI1
#define CONF_DAC_STARTEI1 0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_DAC_CONFIG_H

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// Circuit Python SAMD51 clock tree:
// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5, GCLK6
// GCLK1 (48MHz) -> 48 MHz peripherals
// GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0
// DPLL0 (multiplied up to 120 MHz) -> GCLK0, GCLK4 (output for monitoring)
// GCLK6 (48 MHz divided down to 12 MHz) -> DAC
// We'd like to use XOSC32K as a ref for DFLL48M on boards with a 32kHz crystal,
// but haven't figured that out yet.
// Used in hpl/core/hpl_init.c to define which clocks should be initialized first.
// Not clear why all these need to be specified, but it doesn't work properly otherwise.
//#define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5)
#define CIRCUITPY_GCLK_INIT_1ST 0xffff
/* Auto-generated config file hpl_gclk_config.h */
#ifndef HPL_GCLK_CONFIG_H
#define HPL_GCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> Generic clock generator 0 configuration
// <i> Indicates whether generic clock 0 configuration is enabled or not
// <id> enable_gclk_gen_0
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
#define CONF_GCLK_GENERATOR_0_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 0 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 0
// <id> gclk_gen_0_oscillator
#ifndef CONF_GCLK_GEN_0_SOURCE
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_0_runstdby
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
#define CONF_GCLK_GEN_0_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_0_div_sel
#ifndef CONF_GCLK_GEN_0_DIVSEL
#define CONF_GCLK_GEN_0_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_0_oe
#ifndef CONF_GCLK_GEN_0_OE
#define CONF_GCLK_GEN_0_OE 1
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_0_oov
#ifndef CONF_GCLK_GEN_0_OOV
#define CONF_GCLK_GEN_0_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_0_idc
#ifndef CONF_GCLK_GEN_0_IDC
#define CONF_GCLK_GEN_0_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_0_enable
#ifndef CONF_GCLK_GEN_0_GENEN
#define CONF_GCLK_GEN_0_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
// <id> gclk_gen_0_div
#ifndef CONF_GCLK_GEN_0_DIV
#define CONF_GCLK_GEN_0_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 1 configuration
// <i> Indicates whether generic clock 1 configuration is enabled or not
// <id> enable_gclk_gen_1
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
#define CONF_GCLK_GENERATOR_1_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 1 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SOURCE
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_1_runstdby
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
#define CONF_GCLK_GEN_1_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_1_div_sel
#ifndef CONF_GCLK_GEN_1_DIVSEL
#define CONF_GCLK_GEN_1_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_1_oe
#ifndef CONF_GCLK_GEN_1_OE
#define CONF_GCLK_GEN_1_OE 1
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_1_oov
#ifndef CONF_GCLK_GEN_1_OOV
#define CONF_GCLK_GEN_1_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_1_idc
#ifndef CONF_GCLK_GEN_1_IDC
#define CONF_GCLK_GEN_1_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_1_enable
#ifndef CONF_GCLK_GEN_1_GENEN
#define CONF_GCLK_GEN_1_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
// <id> gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 2 configuration
// <i> Indicates whether generic clock 2 configuration is enabled or not
// <id> enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
#define CONF_GCLK_GENERATOR_2_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 2 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 2
// <id> gclk_gen_2_oscillator
#ifndef CONF_GCLK_GEN_2_SOURCE
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_2_runstdby
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
#define CONF_GCLK_GEN_2_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_2_div_sel
#ifndef CONF_GCLK_GEN_2_DIVSEL
#define CONF_GCLK_GEN_2_DIVSEL 1
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_2_oe
#ifndef CONF_GCLK_GEN_2_OE
#define CONF_GCLK_GEN_2_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_2_oov
#ifndef CONF_GCLK_GEN_2_OOV
#define CONF_GCLK_GEN_2_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_2_idc
#ifndef CONF_GCLK_GEN_2_IDC
#define CONF_GCLK_GEN_2_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
#define CONF_GCLK_GEN_2_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
// <id> gclk_gen_2_div
#ifndef CONF_GCLK_GEN_2_DIV
#define CONF_GCLK_GEN_2_DIV 4
#endif
// </h>
// </e>
// <e> Generic clock generator 3 configuration
// <i> Indicates whether generic clock 3 configuration is enabled or not
// <id> enable_gclk_gen_3
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
#define CONF_GCLK_GENERATOR_3_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 3 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 3
// <id> gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SOURCE
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_3_runstdby
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
#define CONF_GCLK_GEN_3_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_3_div_sel
#ifndef CONF_GCLK_GEN_3_DIVSEL
#define CONF_GCLK_GEN_3_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_3_oe
#ifndef CONF_GCLK_GEN_3_OE
#define CONF_GCLK_GEN_3_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_3_oov
#ifndef CONF_GCLK_GEN_3_OOV
#define CONF_GCLK_GEN_3_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_3_idc
#ifndef CONF_GCLK_GEN_3_IDC
#define CONF_GCLK_GEN_3_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_3_enable
#ifndef CONF_GCLK_GEN_3_GENEN
#define CONF_GCLK_GEN_3_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
// <id> gclk_gen_3_div
#ifndef CONF_GCLK_GEN_3_DIV
#define CONF_GCLK_GEN_3_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 4 configuration
// <i> Indicates whether generic clock 4 configuration is enabled or not
// <id> enable_gclk_gen_4
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
#define CONF_GCLK_GENERATOR_4_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 4 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 4
// <id> gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SOURCE
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DPLL0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_4_runstdby
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
#define CONF_GCLK_GEN_4_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_4_div_sel
#ifndef CONF_GCLK_GEN_4_DIVSEL
#define CONF_GCLK_GEN_4_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_4_oe
#ifndef CONF_GCLK_GEN_4_OE
#define CONF_GCLK_GEN_4_OE 1
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_4_oov
#ifndef CONF_GCLK_GEN_4_OOV
#define CONF_GCLK_GEN_4_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_4_idc
#ifndef CONF_GCLK_GEN_4_IDC
#define CONF_GCLK_GEN_4_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_4_enable
#ifndef CONF_GCLK_GEN_4_GENEN
#define CONF_GCLK_GEN_4_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
// <id> gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
#define CONF_GCLK_GEN_4_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 5 configuration
// <i> Indicates whether generic clock 5 configuration is enabled or not
// <id> enable_gclk_gen_5
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
#define CONF_GCLK_GENERATOR_5_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 5 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 5
// <id> gclk_gen_5_oscillator
#ifndef CONF_GCLK_GEN_5_SOURCE
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DFLL
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_5_runstdby
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
#define CONF_GCLK_GEN_5_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_5_div_sel
#ifndef CONF_GCLK_GEN_5_DIVSEL
#define CONF_GCLK_GEN_5_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_5_oe
#ifndef CONF_GCLK_GEN_5_OE
#define CONF_GCLK_GEN_5_OE 1
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_5_oov
#ifndef CONF_GCLK_GEN_5_OOV
#define CONF_GCLK_GEN_5_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_5_idc
#ifndef CONF_GCLK_GEN_5_IDC
#define CONF_GCLK_GEN_5_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_5_enable
#ifndef CONF_GCLK_GEN_5_GENEN
#define CONF_GCLK_GEN_5_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
// <id> gclk_gen_5_div
#ifndef CONF_GCLK_GEN_5_DIV
#define CONF_GCLK_GEN_5_DIV 24
#endif
// </h>
// </e>
// <e> Generic clock generator 6 configuration
// <i> Indicates whether generic clock 6 configuration is enabled or not
// <id> enable_gclk_gen_6
#ifndef CONF_GCLK_GENERATOR_6_CONFIG
#define CONF_GCLK_GENERATOR_6_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 6 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 6
// <id> gclk_gen_6_oscillator
#ifndef CONF_GCLK_GEN_6_SOURCE
#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_DFLL
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_6_runstdby
#ifndef CONF_GCLK_GEN_6_RUNSTDBY
#define CONF_GCLK_GEN_6_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_6_div_sel
#ifndef CONF_GCLK_GEN_6_DIVSEL
#define CONF_GCLK_GEN_6_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_6_oe
#ifndef CONF_GCLK_GEN_6_OE
#define CONF_GCLK_GEN_6_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_6_oov
#ifndef CONF_GCLK_GEN_6_OOV
#define CONF_GCLK_GEN_6_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_6_idc
#ifndef CONF_GCLK_GEN_6_IDC
#define CONF_GCLK_GEN_6_IDC 1
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_6_enable
#ifndef CONF_GCLK_GEN_6_GENEN
#define CONF_GCLK_GEN_6_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 6 division <0x0000-0xFFFF>
// <id> gclk_gen_6_div
#ifndef CONF_GCLK_GEN_6_DIV
#define CONF_GCLK_GEN_6_DIV 4
#endif
// </h>
// </e>
// <e> Generic clock generator 7 configuration
// <i> Indicates whether generic clock 7 configuration is enabled or not
// <id> enable_gclk_gen_7
#ifndef CONF_GCLK_GENERATOR_7_CONFIG
#define CONF_GCLK_GENERATOR_7_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 7 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 7
// <id> gclk_gen_7_oscillator
#ifndef CONF_GCLK_GEN_7_SOURCE
#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_7_runstdby
#ifndef CONF_GCLK_GEN_7_RUNSTDBY
#define CONF_GCLK_GEN_7_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_7_div_sel
#ifndef CONF_GCLK_GEN_7_DIVSEL
#define CONF_GCLK_GEN_7_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_7_oe
#ifndef CONF_GCLK_GEN_7_OE
#define CONF_GCLK_GEN_7_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_7_oov
#ifndef CONF_GCLK_GEN_7_OOV
#define CONF_GCLK_GEN_7_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_7_idc
#ifndef CONF_GCLK_GEN_7_IDC
#define CONF_GCLK_GEN_7_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_7_enable
#ifndef CONF_GCLK_GEN_7_GENEN
#define CONF_GCLK_GEN_7_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
// <id> gclk_gen_7_div
#ifndef CONF_GCLK_GEN_7_DIV
#define CONF_GCLK_GEN_7_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 8 configuration
// <i> Indicates whether generic clock 8 configuration is enabled or not
// <id> enable_gclk_gen_8
#ifndef CONF_GCLK_GENERATOR_8_CONFIG
#define CONF_GCLK_GENERATOR_8_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 8 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 8
// <id> gclk_gen_8_oscillator
#ifndef CONF_GCLK_GEN_8_SOURCE
#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_8_runstdby
#ifndef CONF_GCLK_GEN_8_RUNSTDBY
#define CONF_GCLK_GEN_8_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_8_div_sel
#ifndef CONF_GCLK_GEN_8_DIVSEL
#define CONF_GCLK_GEN_8_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_8_oe
#ifndef CONF_GCLK_GEN_8_OE
#define CONF_GCLK_GEN_8_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_8_oov
#ifndef CONF_GCLK_GEN_8_OOV
#define CONF_GCLK_GEN_8_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_8_idc
#ifndef CONF_GCLK_GEN_8_IDC
#define CONF_GCLK_GEN_8_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_8_enable
#ifndef CONF_GCLK_GEN_8_GENEN
#define CONF_GCLK_GEN_8_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 8 division <0x0000-0xFFFF>
// <id> gclk_gen_8_div
#ifndef CONF_GCLK_GEN_8_DIV
#define CONF_GCLK_GEN_8_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 9 configuration
// <i> Indicates whether generic clock 9 configuration is enabled or not
// <id> enable_gclk_gen_9
#ifndef CONF_GCLK_GENERATOR_9_CONFIG
#define CONF_GCLK_GENERATOR_9_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 9 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 9
// <id> gclk_gen_9_oscillator
#ifndef CONF_GCLK_GEN_9_SOURCE
#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_9_runstdby
#ifndef CONF_GCLK_GEN_9_RUNSTDBY
#define CONF_GCLK_GEN_9_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_9_div_sel
#ifndef CONF_GCLK_GEN_9_DIVSEL
#define CONF_GCLK_GEN_9_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_9_oe
#ifndef CONF_GCLK_GEN_9_OE
#define CONF_GCLK_GEN_9_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_9_oov
#ifndef CONF_GCLK_GEN_9_OOV
#define CONF_GCLK_GEN_9_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_9_idc
#ifndef CONF_GCLK_GEN_9_IDC
#define CONF_GCLK_GEN_9_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_9_enable
#ifndef CONF_GCLK_GEN_9_GENEN
#define CONF_GCLK_GEN_9_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 9 division <0x0000-0xFFFF>
// <id> gclk_gen_9_div
#ifndef CONF_GCLK_GEN_9_DIV
#define CONF_GCLK_GEN_9_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 10 configuration
// <i> Indicates whether generic clock 10 configuration is enabled or not
// <id> enable_gclk_gen_10
#ifndef CONF_GCLK_GENERATOR_10_CONFIG
#define CONF_GCLK_GENERATOR_10_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 10 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 10
// <id> gclk_gen_10_oscillator
#ifndef CONF_GCLK_GEN_10_SOURCE
#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_10_runstdby
#ifndef CONF_GCLK_GEN_10_RUNSTDBY
#define CONF_GCLK_GEN_10_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_10_div_sel
#ifndef CONF_GCLK_GEN_10_DIVSEL
#define CONF_GCLK_GEN_10_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_10_oe
#ifndef CONF_GCLK_GEN_10_OE
#define CONF_GCLK_GEN_10_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_10_oov
#ifndef CONF_GCLK_GEN_10_OOV
#define CONF_GCLK_GEN_10_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_10_idc
#ifndef CONF_GCLK_GEN_10_IDC
#define CONF_GCLK_GEN_10_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_10_enable
#ifndef CONF_GCLK_GEN_10_GENEN
#define CONF_GCLK_GEN_10_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 10 division <0x0000-0xFFFF>
// <id> gclk_gen_10_div
#ifndef CONF_GCLK_GEN_10_DIV
#define CONF_GCLK_GEN_10_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 11 configuration
// <i> Indicates whether generic clock 11 configuration is enabled or not
// <id> enable_gclk_gen_11
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
#define CONF_GCLK_GENERATOR_11_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 11 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
// <i> This defines the clock source for generic clock generator 11
// <id> gclk_gen_11_oscillator
#ifndef CONF_GCLK_GEN_11_SOURCE
#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_11_runstdby
#ifndef CONF_GCLK_GEN_11_RUNSTDBY
#define CONF_GCLK_GEN_11_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_11_div_sel
#ifndef CONF_GCLK_GEN_11_DIVSEL
#define CONF_GCLK_GEN_11_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_11_oe
#ifndef CONF_GCLK_GEN_11_OE
#define CONF_GCLK_GEN_11_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_11_oov
#ifndef CONF_GCLK_GEN_11_OOV
#define CONF_GCLK_GEN_11_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_11_idc
#ifndef CONF_GCLK_GEN_11_IDC
#define CONF_GCLK_GEN_11_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_11_enable
#ifndef CONF_GCLK_GEN_11_GENEN
#define CONF_GCLK_GEN_11_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 11 division <0x0000-0xFFFF>
// <id> gclk_gen_11_div
#ifndef CONF_GCLK_GEN_11_DIV
#define CONF_GCLK_GEN_11_DIV 1
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_GCLK_CONFIG_H

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/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
#endif
// <y> Low Power Clock Division
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_lpdiv
#ifndef CONF_MCLK_LPDIV
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
#endif
// <y> High-Speed Clock Division
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
// <id> mclk_arch_hsdiv
#ifndef CONF_MCLK_HSDIV
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H

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/* Auto-generated config file hpl_nvmctrl_config.h */
#ifndef HPL_NVMCTRL_CONFIG_H
#define HPL_NVMCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Settings
// <o> Power Reduction Mode During Sleep
// <0x00=> Wake On Access
// <0x01=> Wake Up Instant
// <0x03=> Disabled
// <id> nvm_arch_sleepprm
#ifndef CONF_NVM_SLEEPPRM
#define CONF_NVM_SLEEPPRM 0
#endif
// <q> AHB0 Cache Disable
// <i> Indicate whether AHB0 cache is disable or not
// <id> nvm_arch_cache0
#ifndef CONF_NVM_CACHE0
#define CONF_NVM_CACHE0 1
#endif
// <q> AHB1 Cache Disable
// <i> Indicate whether AHB1 cache is disable or not
// <id> nvm_arch_cache1
#ifndef CONF_NVM_CACHE1
#define CONF_NVM_CACHE1 1
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_NVMCTRL_CONFIG_H

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/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 1
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 0
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 0
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 0
#endif
// <o> Control Gain Mode
// <0x0=>Low Power mode
// <0x1=>Standard mode
// <0x2=>High Speed mode
// <id> xosc32k_arch_cgm
#ifndef CONF_XOSC32K_CGM
#define CONF_XOSC32K_CGM 0x1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x3F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H

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/* Auto-generated config file hpl_oscctrl_config.h */
#ifndef HPL_OSCCTRL_CONFIG_H
#define HPL_OSCCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for XOSC0 is enabled or not
// <id> enable_xosc0
#ifndef CONF_XOSC0_CONFIG
#define CONF_XOSC0_CONFIG 0
#endif
// <o> Frequency <8000000-48000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc0_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC0_FREQUENCY 12000000
#endif
// <h> External Multipurpose Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
// <id> xosc0_arch_enable
#ifndef CONF_XOSC0_ENABLE
#define CONF_XOSC0_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>31us
// <0x1=>61us
// <0x2=>122us
// <0x3=>244us
// <0x4=>488us
// <0x5=>977us
// <0x6=>1953us
// <0x7=>3906us
// <0x8=>7813us
// <0x9=>15625us
// <0xA=>31250us
// <0xB=>62500us
// <0xC=>125000us
// <0xD=>250000us
// <0xE=>500000us
// <0xF=>1000000us
// <id> xosc0_arch_startup
#ifndef CONF_XOSC0_STARTUP
#define CONF_XOSC0_STARTUP 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc0_arch_swben
#ifndef CONF_XOSC0_SWBEN
#define CONF_XOSC0_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc0_arch_cfden
#ifndef CONF_XOSC0_CFDEN
#define CONF_XOSC0_CFDEN 0
#endif
// <q> Automatic Loop Control Enable
// <i> Indicates whether Automatic Loop Control is enabled or not
// <id> xosc0_arch_enalc
#ifndef CONF_XOSC0_ENALC
#define CONF_XOSC0_ENALC 0
#endif
// <q> Low Buffer Gain Enable
// <i> Indicates whether Low Buffer Gain is enabled or not
// <id> xosc0_arch_lowbufgain
#ifndef CONF_XOSC0_LOWBUFGAIN
#define CONF_XOSC0_LOWBUFGAIN 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc0_arch_ondemand
#ifndef CONF_XOSC0_ONDEMAND
#define CONF_XOSC0_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc0_arch_runstdby
#ifndef CONF_XOSC0_RUNSTDBY
#define CONF_XOSC0_RUNSTDBY 0
#endif
// <q> Crystal connected to XIN/XOUT Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc0_arch_xtalen
#ifndef CONF_XOSC0_XTALEN
#define CONF_XOSC0_XTALEN 0
#endif
//</h>
//</e>
#if CONF_XOSC0_FREQUENCY >= 32000000
#define CONF_XOSC0_CFDPRESC 0x0
#define CONF_XOSC0_IMULT 0x7
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 24000000
#define CONF_XOSC0_CFDPRESC 0x1
#define CONF_XOSC0_IMULT 0x6
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 16000000
#define CONF_XOSC0_CFDPRESC 0x2
#define CONF_XOSC0_IMULT 0x5
#define CONF_XOSC0_IPTAT 0x3
#elif CONF_XOSC0_FREQUENCY >= 8000000
#define CONF_XOSC0_CFDPRESC 0x3
#define CONF_XOSC0_IMULT 0x4
#define CONF_XOSC0_IPTAT 0x3
#endif
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for XOSC1 is enabled or not
// <id> enable_xosc1
#ifndef CONF_XOSC1_CONFIG
#define CONF_XOSC1_CONFIG 0
#endif
// <o> Frequency <8000000-48000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc1_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC1_FREQUENCY 12000000
#endif
// <h> External Multipurpose Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
// <id> xosc1_arch_enable
#ifndef CONF_XOSC1_ENABLE
#define CONF_XOSC1_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>31us
// <0x1=>61us
// <0x2=>122us
// <0x3=>244us
// <0x4=>488us
// <0x5=>977us
// <0x6=>1953us
// <0x7=>3906us
// <0x8=>7813us
// <0x9=>15625us
// <0xA=>31250us
// <0xB=>62500us
// <0xC=>125000us
// <0xD=>250000us
// <0xE=>500000us
// <0xF=>1000000us
// <id> xosc1_arch_startup
#ifndef CONF_XOSC1_STARTUP
#define CONF_XOSC1_STARTUP 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc1_arch_swben
#ifndef CONF_XOSC1_SWBEN
#define CONF_XOSC1_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc1_arch_cfden
#ifndef CONF_XOSC1_CFDEN
#define CONF_XOSC1_CFDEN 0
#endif
// <q> Automatic Loop Control Enable
// <i> Indicates whether Automatic Loop Control is enabled or not
// <id> xosc1_arch_enalc
#ifndef CONF_XOSC1_ENALC
#define CONF_XOSC1_ENALC 0
#endif
// <q> Low Buffer Gain Enable
// <i> Indicates whether Low Buffer Gain is enabled or not
// <id> xosc1_arch_lowbufgain
#ifndef CONF_XOSC1_LOWBUFGAIN
#define CONF_XOSC1_LOWBUFGAIN 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc1_arch_ondemand
#ifndef CONF_XOSC1_ONDEMAND
#define CONF_XOSC1_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc1_arch_runstdby
#ifndef CONF_XOSC1_RUNSTDBY
#define CONF_XOSC1_RUNSTDBY 0
#endif
// <q> Crystal connected to XIN/XOUT Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc1_arch_xtalen
#ifndef CONF_XOSC1_XTALEN
#define CONF_XOSC1_XTALEN 0
#endif
//</h>
//</e>
#if CONF_XOSC1_FREQUENCY >= 32000000
#define CONF_XOSC1_CFDPRESC 0x0
#define CONF_XOSC1_IMULT 0x7
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 24000000
#define CONF_XOSC1_CFDPRESC 0x1
#define CONF_XOSC1_IMULT 0x6
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 16000000
#define CONF_XOSC1_CFDPRESC 0x2
#define CONF_XOSC1_IMULT 0x5
#define CONF_XOSC1_IPTAT 0x3
#elif CONF_XOSC1_FREQUENCY >= 8000000
#define CONF_XOSC1_CFDPRESC 0x3
#define CONF_XOSC1_IMULT 0x4
#define CONF_XOSC1_IPTAT 0x3
#endif
// <e> DFLL Configuration
// <i> Indicates whether configuration for DFLL is enabled or not
// <id> enable_dfll
#ifndef CONF_DFLL_CONFIG
#define CONF_DFLL_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source
// <id> dfll_ref_clock
#ifndef CONF_DFLL_GCLK
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
// <h> Digital Frequency Locked Loop Control
// <q> DFLL Enable
// <i> Indicates whether DFLL is enabled or not
// <id> dfll_arch_enable
#ifndef CONF_DFLL_ENABLE
#define CONF_DFLL_ENABLE 1
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> dfll_arch_ondemand
#ifndef CONF_DFLL_ONDEMAND
#define CONF_DFLL_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> dfll_arch_runstdby
#ifndef CONF_DFLL_RUNSTDBY
#define CONF_DFLL_RUNSTDBY 0
#endif
// <q> USB Clock Recovery Mode
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
// <id> dfll_arch_usbcrm
#ifndef CONF_DFLL_USBCRM
#define CONF_DFLL_USBCRM 1
#endif
// <q> Wait Lock
// <i> Indicates whether Wait Lock is enabled or not
// <id> dfll_arch_waitlock
#ifndef CONF_DFLL_WAITLOCK
#define CONF_DFLL_WAITLOCK 1
#endif
// <q> Bypass Coarse Lock
// <i> Indicates whether Bypass Coarse Lock is enabled or not
// <id> dfll_arch_bplckc
#ifndef CONF_DFLL_BPLCKC
#define CONF_DFLL_BPLCKC 0
#endif
// <q> Quick Lock Disable
// <i> Indicates whether Quick Lock Disable is enabled or not
// <id> dfll_arch_qldis
#ifndef CONF_DFLL_QLDIS
#define CONF_DFLL_QLDIS 0
#endif
// <q> Chill Cycle Disable
// <i> Indicates whether Chill Cycle Disable is enabled or not
// <id> dfll_arch_ccdis
#ifndef CONF_DFLL_CCDIS
#define CONF_DFLL_CCDIS 1
#endif
// <q> Lose Lock After Wake
// <i> Indicates whether Lose Lock After Wake is enabled or not
// <id> dfll_arch_llaw
#ifndef CONF_DFLL_LLAW
#define CONF_DFLL_LLAW 0
#endif
// <q> Stable DFLL Frequency
// <i> Indicates whether Stable DFLL Frequency is enabled or not
// <id> dfll_arch_stable
#ifndef CONF_DFLL_STABLE
#define CONF_DFLL_STABLE 0
#endif
// <o> Operating Mode Selection
// <0=>Open Loop Mode
// <1=>Closed Loop Mode
// <id> dfll_mode
#ifndef CONF_DFLL_MODE
#define CONF_DFLL_MODE 0x0
#endif
// <o> Coarse Maximum Step <0x0-0x1F>
// <id> dfll_arch_cstep
#ifndef CONF_DFLL_CSTEP
#define CONF_DFLL_CSTEP 0x1
#endif
// <o> Fine Maximum Step <0x0-0xFF>
// <id> dfll_arch_fstep
#ifndef CONF_DFLL_FSTEP
#define CONF_DFLL_FSTEP 0x1
#endif
// <o> DFLL Multiply Factor <0x0-0xFFFF>
// <id> dfll_mul
#ifndef CONF_DFLL_MUL
#define CONF_DFLL_MUL 0x0
#endif
// <e> DFLL Calibration Overwrite
// <i> Indicates whether Overwrite Calibration value of DFLL
// <id> dfll_arch_calibration
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
#endif
// <o> Coarse Value <0x0-0x3F>
// <id> dfll_arch_coarse
#ifndef CONF_DFLL_COARSE
#define CONF_DFLL_COARSE (0x1f / 4)
#endif
// <o> Fine Value <0x0-0xFF>
// <id> dfll_arch_fine
#ifndef CONF_DFLL_FINE
#define CONF_DFLL_FINE (0x80)
#endif
//</e>
//</h>
//</e>
// <e> FDPLL0 Configuration
// <i> Indicates whether configuration for FDPLL0 is enabled or not
// <id> enable_fdpll0
#ifndef CONF_FDPLL0_CONFIG
#define CONF_FDPLL0_CONFIG 1
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source.
// <id> fdpll0_ref_clock
#ifndef CONF_FDPLL0_GCLK
#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK5_Val
#endif
// <h> Digital Phase Locked Loop Control
// <q> Enable
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll0_arch_enable
#ifndef CONF_FDPLL0_ENABLE
#define CONF_FDPLL0_ENABLE 1
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> fdpll0_arch_ondemand
#ifndef CONF_FDPLL0_ONDEMAND
#define CONF_FDPLL0_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> fdpll0_arch_runstdby
#ifndef CONF_FDPLL0_RUNSTDBY
#define CONF_FDPLL0_RUNSTDBY 0
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
// <id> fdpll0_ldrfrac
#ifndef CONF_FDPLL0_LDRFRAC
#define CONF_FDPLL0_LDRFRAC 0x0
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
// <id> fdpll0_ldr
#ifndef CONF_FDPLL0_LDR
#define CONF_FDPLL0_LDR 59
#endif
// <o> Clock Divider <0x0-0x7FF>
// <id> fdpll0_clock_div
#ifndef CONF_FDPLL0_DIV
#define CONF_FDPLL0_DIV 0x0
#endif
// <q> DCO Filter Enable
// <i> Indicates whether DCO Filter Enable is enabled or not
// <id> fdpll0_arch_dcoen
#ifndef CONF_FDPLL0_DCOEN
#define CONF_FDPLL0_DCOEN 0
#endif
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
// <id> fdpll0_clock_dcofilter
#ifndef CONF_FDPLL0_DCOFILTER
#define CONF_FDPLL0_DCOFILTER 0x0
#endif
// <q> Lock Bypass
// <i> Indicates whether Lock Bypass is enabled or not
// <id> fdpll0_arch_lbypass
#ifndef CONF_FDPLL0_LBYPASS
#define CONF_FDPLL0_LBYPASS 0
#endif
// <o> Lock Time
// <0x0=>No time-out, automatic lock
// <0x4=>The Time-out if no lock within 800 us
// <0x5=>The Time-out if no lock within 900 us
// <0x6=>The Time-out if no lock within 1 ms
// <0x7=>The Time-out if no lock within 11 ms
// <id> fdpll0_arch_ltime
#ifndef CONF_FDPLL0_LTIME
#define CONF_FDPLL0_LTIME 0x0
#endif
// <o> Reference Clock Selection
// <0x0=>GCLK clock reference
// <0x1=>XOSC32K clock reference
// <0x2=>XOSC0 clock reference
// <0x3=>XOSC1 clock reference
// <id> fdpll0_arch_refclk
#ifndef CONF_FDPLL0_REFCLK
#define CONF_FDPLL0_REFCLK 0x0
#endif
// <q> Wake Up Fast
// <i> Indicates whether Wake Up Fast is enabled or not
// <id> fdpll0_arch_wuf
#ifndef CONF_FDPLL0_WUF
#define CONF_FDPLL0_WUF 0
#endif
// <o> Proportional Integral Filter Selection <0x0-0xF>
// <id> fdpll0_arch_filter
#ifndef CONF_FDPLL0_FILTER
#define CONF_FDPLL0_FILTER 0x0
#endif
//</h>
//</e>
// <e> FDPLL1 Configuration
// <i> Indicates whether configuration for FDPLL1 is enabled or not
// <id> enable_fdpll1
#ifndef CONF_FDPLL1_CONFIG
#define CONF_FDPLL1_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source.
// <id> fdpll1_ref_clock
#ifndef CONF_FDPLL1_GCLK
#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
#endif
// <h> Digital Phase Locked Loop Control
// <q> Enable
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll1_arch_enable
#ifndef CONF_FDPLL1_ENABLE
#define CONF_FDPLL1_ENABLE 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> fdpll1_arch_ondemand
#ifndef CONF_FDPLL1_ONDEMAND
#define CONF_FDPLL1_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> fdpll1_arch_runstdby
#ifndef CONF_FDPLL1_RUNSTDBY
#define CONF_FDPLL1_RUNSTDBY 0
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
// <id> fdpll1_ldrfrac
#ifndef CONF_FDPLL1_LDRFRAC
#define CONF_FDPLL1_LDRFRAC 0xd
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
// <id> fdpll1_ldr
#ifndef CONF_FDPLL1_LDR
#define CONF_FDPLL1_LDR 0x5b7
#endif
// <o> Clock Divider <0x0-0x7FF>
// <id> fdpll1_clock_div
#ifndef CONF_FDPLL1_DIV
#define CONF_FDPLL1_DIV 0x0
#endif
// <q> DCO Filter Enable
// <i> Indicates whether DCO Filter Enable is enabled or not
// <id> fdpll1_arch_dcoen
#ifndef CONF_FDPLL1_DCOEN
#define CONF_FDPLL1_DCOEN 0
#endif
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
// <id> fdpll1_clock_dcofilter
#ifndef CONF_FDPLL1_DCOFILTER
#define CONF_FDPLL1_DCOFILTER 0x0
#endif
// <q> Lock Bypass
// <i> Indicates whether Lock Bypass is enabled or not
// <id> fdpll1_arch_lbypass
#ifndef CONF_FDPLL1_LBYPASS
#define CONF_FDPLL1_LBYPASS 0
#endif
// <o> Lock Time
// <0x0=>No time-out, automatic lock
// <0x4=>The Time-out if no lock within 800 us
// <0x5=>The Time-out if no lock within 900 us
// <0x6=>The Time-out if no lock within 1 ms
// <0x7=>The Time-out if no lock within 11 ms
// <id> fdpll1_arch_ltime
#ifndef CONF_FDPLL1_LTIME
#define CONF_FDPLL1_LTIME 0x0
#endif
// <o> Reference Clock Selection
// <0x0=>GCLK clock reference
// <0x1=>XOSC32K clock reference
// <0x2=>XOSC0 clock reference
// <0x3=>XOSC1 clock reference
// <id> fdpll1_arch_refclk
#ifndef CONF_FDPLL1_REFCLK
#define CONF_FDPLL1_REFCLK 0x1
#endif
// <q> Wake Up Fast
// <i> Indicates whether Wake Up Fast is enabled or not
// <id> fdpll1_arch_wuf
#ifndef CONF_FDPLL1_WUF
#define CONF_FDPLL1_WUF 0
#endif
// <o> Proportional Integral Filter Selection <0x0-0xF>
// <id> fdpll1_arch_filter
#ifndef CONF_FDPLL1_FILTER
#define CONF_FDPLL1_FILTER 0x0
#endif
//</h>
//</e>
// <<< end of configuration section >>>
#endif // HPL_OSCCTRL_CONFIG_H

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ports/atmel-samd/asf4_conf/same54/hpl_rtc_config.h Normal file
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/* Auto-generated config file hpl_rtc_config.h */
#ifndef HPL_RTC_CONFIG_H
#define HPL_RTC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic settings
#ifndef CONF_RTC_ENABLE
#define CONF_RTC_ENABLE 1
#endif
// <q> Force reset RTC on initialization
// <i> Force RTC to reset on initialization.
// <i> Note that the previous power down data in RTC is lost if it's enabled.
// <id> rtc_arch_init_reset
#ifndef CONF_RTC_INIT_RESET
#define CONF_RTC_INIT_RESET 0
#endif
// <o> Prescaler configuration
// <0x0=>OFF(Peripheral clock divided by 1)
// <0x1=>Peripheral clock divided by 1
// <0x2=>Peripheral clock divided by 2
// <0x3=>Peripheral clock divided by 4
// <0x4=>Peripheral clock divided by 8
// <0x5=>Peripheral clock divided by 16
// <0x6=>Peripheral clock divided by 32
// <0x7=>Peripheral clock divided by 64
// <0x8=>Peripheral clock divided by 128
// <0x9=>Peripheral clock divided by 256
// <0xA=>Peripheral clock divided by 512
// <0xB=>Peripheral clock divided by 1024
// <i> These bits define the RTC clock relative to the peripheral clock
// <id> rtc_arch_prescaler
#ifndef CONF_RTC_PRESCALER
#define CONF_RTC_PRESCALER 0xb
#endif
// <o> Compare Value <1-4294967295>
// <i> These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value),
// <i> by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms.
// <id> rtc_arch_comp_val
#ifndef CONF_RTC_COMP_VAL
#define CONF_RTC_COMP_VAL 1
#endif
// <e> Event control
// <id> rtc_event_control
#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
#define CONF_RTC_EVENT_CONTROL_ENABLE 0
#endif
// <q> Periodic Interval 0 Event Output
// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
// <id> rtc_pereo0
#ifndef CONF_RTC_PEREO0
#define CONF_RTC_PEREO0 0
#endif
// <q> Periodic Interval 1 Event Output
// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
// <id> rtc_pereo1
#ifndef CONF_RTC_PEREO1
#define CONF_RTC_PEREO1 0
#endif
// <q> Periodic Interval 2 Event Output
// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
// <id> rtc_pereo2
#ifndef CONF_RTC_PEREO2
#define CONF_RTC_PEREO2 0
#endif
// <q> Periodic Interval 3 Event Output
// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
// <id> rtc_pereo3
#ifndef CONF_RTC_PEREO3
#define CONF_RTC_PEREO3 0
#endif
// <q> Periodic Interval 4 Event Output
// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
// <id> rtc_pereo4
#ifndef CONF_RTC_PEREO4
#define CONF_RTC_PEREO4 0
#endif
// <q> Periodic Interval 5 Event Output
// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
// <id> rtc_pereo5
#ifndef CONF_RTC_PEREO5
#define CONF_RTC_PEREO5 0
#endif
// <q> Periodic Interval 6 Event Output
// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
// <id> rtc_pereo6
#ifndef CONF_RTC_PEREO6
#define CONF_RTC_PEREO6 0
#endif
// <q> Periodic Interval 7 Event Output
// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
// <id> rtc_pereo7
#ifndef CONF_RTC_PEREO7
#define CONF_RTC_PEREO7 0
#endif
// <q> Compare 0 Event Output
// <i> This bit indicates whether Compare O event is enabled and will be generated
// <id> rtc_cmpeo0
#ifndef CONF_RTC_COMPE0
#define CONF_RTC_COMPE0 0
#endif
// <q> Compare 1 Event Output
// <i> This bit indicates whether Compare 1 event is enabled and will be generated
// <id> rtc_cmpeo1
#ifndef CONF_RTC_COMPE1
#define CONF_RTC_COMPE1 0
#endif
// <q> Overflow Event Output
// <i> This bit indicates whether Overflow event is enabled and will be generated
// <id> rtc_ovfeo
#ifndef CONF_RTC_OVFEO
#define CONF_RTC_OVFEO 0
#endif
// <q> Tamper Event Output
// <i> This bit indicates whether Tamper event output is enabled and will be generated
// <id> rtc_tampereo
#ifndef CONF_RTC_TAMPEREO
#define CONF_RTC_TAMPEREO 0
#endif
// <q> Tamper Event Input
// <i> This bit indicates whether Tamper event input is enabled and will be generated
// <id> rtc_tampevei
#ifndef CONF_RTC_TAMPEVEI
#define CONF_RTC_TAMPEVEI 0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_RTC_CONFIG_H

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ports/atmel-samd/asf4_conf/same54/hpl_sdhc_config.h Normal file
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/* Auto-generated config file hpl_sdhc_config.h */
#ifndef HPL_SDHC_CONFIG_H
#define HPL_SDHC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include "peripheral_clk_config.h"
#ifndef CONF_BASE_FREQUENCY
#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
#endif
// <o> Clock Generator Select
// <0=> Divided Clock mode
// <1=> Programmable Clock mode
// <i> This defines the clock generator mode in the SDCLK Frequency Select field
// <id> sdhc_clk_gsel
#ifndef CONF_SDHC0_CLK_GEN_SEL
#define CONF_SDHC0_CLK_GEN_SEL 0
#endif
// <<< end of configuration section >>>
#endif // HPL_SDHC_CONFIG_H

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ports/atmel-samd/asf4_conf/same54/hpl_sercom_config.h Normal file
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// For CircuitPython, use SERCOM settings as prototypes to set
// the default settings. This file defines these SERCOMs
//
// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous
// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous
// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous
// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA
#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0
#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY
#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1
#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2
#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY
/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// Enable configuration of module
#ifndef CONF_SERCOM_0_SPI_ENABLE
#define CONF_SERCOM_0_SPI_ENABLE 1
#endif
// Set module in SPI Master mode
#ifndef CONF_SERCOM_0_SPI_MODE
#define CONF_SERCOM_0_SPI_MODE 0x03
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable receive buffer to receive data from slave (RXEN)
// <id> spi_master_rx_enable
#ifndef CONF_SERCOM_0_SPI_RXEN
#define CONF_SERCOM_0_SPI_RXEN 0x1
#endif
// <o> Character Size
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
// <0x0=>8 bits
// <0x1=>9 bits
// <id> spi_master_character_size
#ifndef CONF_SERCOM_0_SPI_CHSIZE
#define CONF_SERCOM_0_SPI_CHSIZE 0x0
#endif
// <o> Baud rate <1-12000000>
// <i> The SPI data transfer rate
// <id> spi_master_baud_rate
#ifndef CONF_SERCOM_0_SPI_BAUD
#define CONF_SERCOM_0_SPI_BAUD 50000
#endif
// </h>
// <e> Advanced Configuration
// <id> spi_master_advanced
#ifndef CONF_SERCOM_0_SPI_ADVANCED
#define CONF_SERCOM_0_SPI_ADVANCED 1
#endif
// <o> Dummy byte <0x00-0x1ff>
// <id> spi_master_dummybyte
// <i> Dummy byte used when reading data from the slave without sending any data
#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE
#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff
#endif
// <o> Data Order
// <0=>MSB first
// <1=>LSB first
// <i> I least significant or most significant bit is shifted out first (DORD)
// <id> spi_master_arch_dord
#ifndef CONF_SERCOM_0_SPI_DORD
#define CONF_SERCOM_0_SPI_DORD 0x0
#endif
// <o> Clock Polarity
// <0=>SCK is low when idle
// <1=>SCK is high when idle
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
// <id> spi_master_arch_cpol
#ifndef CONF_SERCOM_0_SPI_CPOL
#define CONF_SERCOM_0_SPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Sample input on leading edge
// <0x1=>Sample input on trailing edge
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
// <id> spi_master_arch_cpha
#ifndef CONF_SERCOM_0_SPI_CPHA
#define CONF_SERCOM_0_SPI_CPHA 0x0
#endif
// <o> Immediate Buffer Overflow Notification
// <i> Controls when OVF is asserted (IBON)
// <0x0=>In data stream
// <0x1=>On buffer overflow
// <id> spi_master_arch_ibon
#ifndef CONF_SERCOM_0_SPI_IBON
#define CONF_SERCOM_0_SPI_IBON 0x0
#endif
// <q> Run in stand-by
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
// <id> spi_master_arch_runstdby
#ifndef CONF_SERCOM_0_SPI_RUNSTDBY
#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
// <0=>Keep running
// <1=>Halt
// <id> spi_master_arch_dbgstop
#ifndef CONF_SERCOM_0_SPI_DBGSTOP
#define CONF_SERCOM_0_SPI_DBGSTOP 0
#endif
// </e>
// Address mode disabled in master mode
#ifndef CONF_SERCOM_0_SPI_AMODE_EN
#define CONF_SERCOM_0_SPI_AMODE_EN 0
#endif
#ifndef CONF_SERCOM_0_SPI_AMODE
#define CONF_SERCOM_0_SPI_AMODE 0
#endif
#ifndef CONF_SERCOM_0_SPI_ADDR
#define CONF_SERCOM_0_SPI_ADDR 0
#endif
#ifndef CONF_SERCOM_0_SPI_ADDRMASK
#define CONF_SERCOM_0_SPI_ADDRMASK 0
#endif
#ifndef CONF_SERCOM_0_SPI_SSDE
#define CONF_SERCOM_0_SPI_SSDE 0
#endif
#ifndef CONF_SERCOM_0_SPI_MSSEN
#define CONF_SERCOM_0_SPI_MSSEN 0x0
#endif
#ifndef CONF_SERCOM_0_SPI_PLOADEN
#define CONF_SERCOM_0_SPI_PLOADEN 0
#endif
// <o> Receive Data Pinout
// <0x0=>PAD[0]
// <0x1=>PAD[1]
// <0x2=>PAD[2]
// <0x3=>PAD[3]
// <id> spi_master_rxpo
#ifndef CONF_SERCOM_0_SPI_RXPO
#define CONF_SERCOM_0_SPI_RXPO 2
#endif
// <o> Transmit Data Pinout
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK
// <id> spi_master_txpo
#ifndef CONF_SERCOM_0_SPI_TXPO
#define CONF_SERCOM_0_SPI_TXPO 0
#endif
// Calculate baud register value from requested baudrate value
#ifndef CONF_SERCOM_0_SPI_BAUD_RATE
#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1
#endif
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_1_I2CM_ENABLE
#define CONF_SERCOM_1_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_1_I2CM_BAUD
#define CONF_SERCOM_1_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 1
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_1_I2CM_TRISE
#define CONF_SERCOM_1_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
#define CONF_SERCOM_1_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_1_I2CM_INACTOUT
#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_1_I2CM_SPEED
#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_1_I2CM_TRISE
#define CONF_SERCOM_1_I2CM_TRISE 215
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \
- (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \
/ 1000)) \
* 10 \
+ 5) \
/ (CONF_SERCOM_1_I2CM_BAUD * 10))
#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_1_I2CM_BAUD_RATE \
((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
#include <peripheral_clk_config.h>
#ifndef CONF_SERCOM_2_USART_ENABLE
#define CONF_SERCOM_2_USART_ENABLE 1
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable input buffer in SERCOM module
// <id> usart_rx_enable
#ifndef CONF_SERCOM_2_USART_RXEN
#define CONF_SERCOM_2_USART_RXEN 1
#endif
// <q> Transmitt buffer enable
// <i> Enable output buffer in SERCOM module
// <id> usart_tx_enable
#ifndef CONF_SERCOM_2_USART_TXEN
#define CONF_SERCOM_2_USART_TXEN 1
#endif
// <o> Frame parity
// <0x0=>No parity
// <0x1=>Even parity
// <0x2=>Odd parity
// <i> Parity bit mode for USART frame
// <id> usart_parity
#ifndef CONF_SERCOM_2_USART_PARITY
#define CONF_SERCOM_2_USART_PARITY 0x0
#endif
// <o> Character Size
// <0x0=>8 bits
// <0x1=>9 bits
// <0x5=>5 bits
// <0x6=>6 bits
// <0x7=>7 bits
// <i> Data character size in USART frame
// <id> usart_character_size
#ifndef CONF_SERCOM_2_USART_CHSIZE
#define CONF_SERCOM_2_USART_CHSIZE 0x0
#endif
// <o> Stop Bit
// <0=>One stop bit
// <1=>Two stop bits
// <i> Number of stop bits in USART frame
// <id> usart_stop_bit
#ifndef CONF_SERCOM_2_USART_SBMODE
#define CONF_SERCOM_2_USART_SBMODE 0
#endif
// <o> Baud rate <1-3000000>
// <i> USART baud rate setting
// <id> usart_baud_rate
#ifndef CONF_SERCOM_2_USART_BAUD
#define CONF_SERCOM_2_USART_BAUD 9600
#endif
// </h>
// <e> Advanced configuration
// <id> usart_advanced
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 1
#endif
// <q> Run in stand-by
// <i> Keep the module running in standby sleep mode
// <id> usart_arch_runstdby
#ifndef CONF_SERCOM_2_USART_RUNSTDBY
#define CONF_SERCOM_2_USART_RUNSTDBY 0
#endif
// <q> Immediate Buffer Overflow Notification
// <i> Controls when the BUFOVF status bit is asserted
// <id> usart_arch_ibon
#ifndef CONF_SERCOM_2_USART_IBON
#define CONF_SERCOM_2_USART_IBON 0
#endif
// <q> Start of Frame Detection Enable
// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
// <id> usart_arch_sfde
#ifndef CONF_SERCOM_2_USART_SFDE
#define CONF_SERCOM_2_USART_SFDE 0
#endif
// <q> Collision Detection Enable
// <i> Collision detection enable
// <id> usart_arch_cloden
#ifndef CONF_SERCOM_2_USART_CLODEN
#define CONF_SERCOM_2_USART_CLODEN 0
#endif
// <o> Operating Mode
// <0x0=>USART with external clock
// <0x1=>USART with internal clock
// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
// <id> usart_arch_clock_mode
#ifndef CONF_SERCOM_2_USART_MODE
#define CONF_SERCOM_2_USART_MODE 0x1
#endif
// <o> Sample Rate
// <0x0=>16x arithmetic
// <0x1=>16x fractional
// <0x2=>8x arithmetic
// <0x3=>8x fractional
// <0x3=>3x
// <i> How many over-sampling bits used when samling data state
// <id> usart_arch_sampr
#ifndef CONF_SERCOM_2_USART_SAMPR
#define CONF_SERCOM_2_USART_SAMPR 0x0
#endif
// <o> Sample Adjustment
// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
// <i> Adjust which samples to use for data sampling in asynchronous mode
// <id> usart_arch_sampa
#ifndef CONF_SERCOM_2_USART_SAMPA
#define CONF_SERCOM_2_USART_SAMPA 0x0
#endif
// <o> Fractional Part <0-7>
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
// <id> usart_arch_fractional
#ifndef CONF_SERCOM_2_USART_FRACTIONAL
#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
#endif
// <o> Data Order
// <0=>MSB is transmitted first
// <1=>LSB is transmitted first
// <i> Data order of the data bits in the frame
// <id> usart_arch_dord
#ifndef CONF_SERCOM_2_USART_DORD
#define CONF_SERCOM_2_USART_DORD 1
#endif
// Does not do anything in UART mode
#define CONF_SERCOM_2_USART_CPOL 0
// <o> Encoding Format
// <0=>No encoding
// <1=>IrDA encoded
// <id> usart_arch_enc
#ifndef CONF_SERCOM_2_USART_ENC
#define CONF_SERCOM_2_USART_ENC 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> usart_arch_dbgstop
#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_2_USART_INACK
#define CONF_SERCOM_2_USART_INACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_DSNACK
#define CONF_SERCOM_2_USART_DSNACK 0x0
#endif
#ifndef CONF_SERCOM_2_USART_MAXITER
#define CONF_SERCOM_2_USART_MAXITER 0x7
#endif
#ifndef CONF_SERCOM_2_USART_GTIME
#define CONF_SERCOM_2_USART_GTIME 0x2
#endif
#define CONF_SERCOM_2_USART_RXINV 0x0
#define CONF_SERCOM_2_USART_TXINV 0x0
#ifndef CONF_SERCOM_2_USART_CMODE
#define CONF_SERCOM_2_USART_CMODE 0
#endif
#ifndef CONF_SERCOM_2_USART_RXPO
#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA08 */
#endif
#ifndef CONF_SERCOM_2_USART_TXPO
#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA09 */
#endif
/* Set correct parity settings in register interface based on PARITY setting */
#if CONF_SERCOM_2_USART_PARITY == 0
#define CONF_SERCOM_2_USART_PMODE 0
#define CONF_SERCOM_2_USART_FORM 0
#else
#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
#define CONF_SERCOM_2_USART_FORM 1
#endif
// Calculate BAUD register value in UART mode
#if CONF_SERCOM_2_USART_SAMPR == 0
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 1
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 2
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 3
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#elif CONF_SERCOM_2_USART_SAMPR == 4
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
#define CONF_SERCOM_2_USART_BAUD_RATE \
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
#endif
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
#endif
#endif
#include <peripheral_clk_config.h>
// Enable configuration of module
#ifndef CONF_SERCOM_3_SPI_ENABLE
#define CONF_SERCOM_3_SPI_ENABLE 1
#endif
//<o> SPI DMA TX Channel <0-32>
//<i> This defines DMA channel to be used
//<id> spi_master_dma_tx_channel
#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL
#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0
#endif
// <e> SPI RX Channel Enable
// <id> spi_master_rx_channel
#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL
#define CONF_SERCOM_3_SPI_RX_CHANNEL 1
#endif
//<o> DMA Channel <0-32>
//<i> This defines DMA channel to be used
//<id> spi_master_dma_rx_channel
#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL
#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1
#endif
// </e>
// Set module in SPI Master mode
#ifndef CONF_SERCOM_3_SPI_MODE
#define CONF_SERCOM_3_SPI_MODE 0x03
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable receive buffer to receive data from slave (RXEN)
// <id> spi_master_rx_enable
#ifndef CONF_SERCOM_3_SPI_RXEN
#define CONF_SERCOM_3_SPI_RXEN 0x1
#endif
// <o> Character Size
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
// <0x0=>8 bits
// <0x1=>9 bits
// <id> spi_master_character_size
#ifndef CONF_SERCOM_3_SPI_CHSIZE
#define CONF_SERCOM_3_SPI_CHSIZE 0x0
#endif
// <o> Baud rate <1-12000000>
// <i> The SPI data transfer rate
// <id> spi_master_baud_rate
#ifndef CONF_SERCOM_3_SPI_BAUD
#define CONF_SERCOM_3_SPI_BAUD 50000
#endif
// </h>
// <e> Advanced Configuration
// <id> spi_master_advanced
#ifndef CONF_SERCOM_3_SPI_ADVANCED
#define CONF_SERCOM_3_SPI_ADVANCED 0
#endif
// <o> Dummy byte <0x00-0x1ff>
// <id> spi_master_dummybyte
// <i> Dummy byte used when reading data from the slave without sending any data
#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE
#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff
#endif
// <o> Data Order
// <0=>MSB first
// <1=>LSB first
// <i> I least significant or most significant bit is shifted out first (DORD)
// <id> spi_master_arch_dord
#ifndef CONF_SERCOM_3_SPI_DORD
#define CONF_SERCOM_3_SPI_DORD 0x0
#endif
// <o> Clock Polarity
// <0=>SCK is low when idle
// <1=>SCK is high when idle
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
// <id> spi_master_arch_cpol
#ifndef CONF_SERCOM_3_SPI_CPOL
#define CONF_SERCOM_3_SPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Sample input on leading edge
// <0x1=>Sample input on trailing edge
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
// <id> spi_master_arch_cpha
#ifndef CONF_SERCOM_3_SPI_CPHA
#define CONF_SERCOM_3_SPI_CPHA 0x0
#endif
// <o> Immediate Buffer Overflow Notification
// <i> Controls when OVF is asserted (IBON)
// <0x0=>In data stream
// <0x1=>On buffer overflow
// <id> spi_master_arch_ibon
#ifndef CONF_SERCOM_3_SPI_IBON
#define CONF_SERCOM_3_SPI_IBON 0x0
#endif
// <q> Run in stand-by
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
// <id> spi_master_arch_runstdby
#ifndef CONF_SERCOM_3_SPI_RUNSTDBY
#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
// <0=>Keep running
// <1=>Halt
// <id> spi_master_arch_dbgstop
#ifndef CONF_SERCOM_3_SPI_DBGSTOP
#define CONF_SERCOM_3_SPI_DBGSTOP 0
#endif
// </e>
// Address mode disabled in master mode
#ifndef CONF_SERCOM_3_SPI_AMODE_EN
#define CONF_SERCOM_3_SPI_AMODE_EN 0
#endif
#ifndef CONF_SERCOM_3_SPI_AMODE
#define CONF_SERCOM_3_SPI_AMODE 0
#endif
#ifndef CONF_SERCOM_3_SPI_ADDR
#define CONF_SERCOM_3_SPI_ADDR 0
#endif
#ifndef CONF_SERCOM_3_SPI_ADDRMASK
#define CONF_SERCOM_3_SPI_ADDRMASK 0
#endif
#ifndef CONF_SERCOM_3_SPI_SSDE
#define CONF_SERCOM_3_SPI_SSDE 0
#endif
#ifndef CONF_SERCOM_3_SPI_MSSEN
#define CONF_SERCOM_3_SPI_MSSEN 0x0
#endif
#ifndef CONF_SERCOM_3_SPI_PLOADEN
#define CONF_SERCOM_3_SPI_PLOADEN 0
#endif
// <o> Receive Data Pinout
// <0x0=>PAD[0]
// <0x1=>PAD[1]
// <0x2=>PAD[2]
// <0x3=>PAD[3]
// <id> spi_master_rxpo
#ifndef CONF_SERCOM_3_SPI_RXPO
#define CONF_SERCOM_3_SPI_RXPO 2
#endif
// <o> Transmit Data Pinout
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK
// <id> spi_master_txpo
#ifndef CONF_SERCOM_3_SPI_TXPO
#define CONF_SERCOM_3_SPI_TXPO 0
#endif
// Calculate baud register value from requested baudrate value
#ifndef CONF_SERCOM_3_SPI_BAUD_RATE
#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H

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