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stmhal: Generate modstm constants per build 

This causes unnecessary constants to no longer be generated.
Some constants (like UART_BRR) are different between the F4 and F7
This commit is contained in:
Dave Hylands 2015-08-02 10:42:09 -07:00 committed by Damien George
parent 4836bcc957
commit be66a9ecf6
14 changed files with 33 additions and 512 deletions
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14
stmhal/Makefile
View File

@ -13,7 +13,7 @@ include ../py/mkenv.mk
include boards/$(BOARD)/mpconfigboard.mk include boards/$(BOARD)/mpconfigboard.mk
# qstr definitions (must come before including py.mk) # qstr definitions (must come before including py.mk)
QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h $(BUILD)/modstm_qstr.h
# include py core make definitions # include py core make definitions
include ../py/py.mk include ../py/py.mk
@ -325,6 +325,18 @@ $(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(BUILD)/
$(BUILD)/pins_$(BOARD).o: $(BUILD)/pins_$(BOARD).c $(BUILD)/pins_$(BOARD).o: $(BUILD)/pins_$(BOARD).c
$(call compile_c) $(call compile_c)
GEN_STMCONST_HDR = $(HEADER_BUILD)/modstm_const.h
GEN_STMCONST_QSTR = $(BUILD)/modstm_qstr.h
CMSIS_MCU_LOWER = $(shell echo $(CMSIS_MCU) | tr '[:upper:]' '[:lower:]')
CMSIS_MCU_HDR = cmsis/devinc/$(CMSIS_MCU_LOWER).h
$(BUILD)/modstm.o: $(GEN_STMCONST_HDR)
# Use a pattern rule here so that make will only call make-stmconst.py once to
# make both modstm_const.h and modstm_qstr.h
$(HEADER_BUILD)/%_const.h $(BUILD)/%_qstr.h: $(CMSIS_MCU_HDR) make-stmconst.py
$(ECHO) "Create stmconst $@"
$(Q)$(PYTHON) make-stmconst.py --qstr $(GEN_STMCONST_QSTR) $(CMSIS_MCU_HDR) > $(GEN_STMCONST_HDR)
$(GEN_CDCINF_HEADER): $(GEN_CDCINF_FILE) $(FILE2H) $(GEN_CDCINF_HEADER): $(GEN_CDCINF_FILE) $(FILE2H)
$(ECHO) "Create $@" $(ECHO) "Create $@"
$(Q)$(PYTHON) $(FILE2H) $< > $@ $(Q)$(PYTHON) $(FILE2H) $< > $@

1
stmhal/boards/CERB40/mpconfigboard.mk
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@ -1,3 +1,4 @@
MCU_SERIES = f4 MCU_SERIES = f4
CMSIS_MCU = STM32F405xx
AF_FILE = boards/stm32f405_af.csv AF_FILE = boards/stm32f405_af.csv
LD_FILE = boards/stm32f405.ld LD_FILE = boards/stm32f405.ld

1
stmhal/boards/ESPRUINO_PICO/mpconfigboard.mk
View File

@ -1,3 +1,4 @@
MCU_SERIES = f4 MCU_SERIES = f4
CMSIS_MCU = STM32F401xE
AF_FILE = boards/stm32f401_af.csv AF_FILE = boards/stm32f401_af.csv
LD_FILE = boards/stm32f401.ld LD_FILE = boards/stm32f401.ld

1
stmhal/boards/HYDRABUS/mpconfigboard.mk
View File

@ -1,3 +1,4 @@
MCU_SERIES = f4 MCU_SERIES = f4
CMSIS_MCU = STM32F405xx
AF_FILE = boards/stm32f405_af.csv AF_FILE = boards/stm32f405_af.csv
LD_FILE = boards/stm32f405.ld LD_FILE = boards/stm32f405.ld

1
stmhal/boards/NETDUINO_PLUS_2/mpconfigboard.mk
View File

@ -1,3 +1,4 @@
MCU_SERIES = f4 MCU_SERIES = f4
CMSIS_MCU = STM32F405xx
AF_FILE = boards/stm32f405_af.csv AF_FILE = boards/stm32f405_af.csv
LD_FILE = boards/stm32f405.ld LD_FILE = boards/stm32f405.ld

1
stmhal/boards/PYBV10/mpconfigboard.mk
View File

@ -1,3 +1,4 @@
MCU_SERIES = f4 MCU_SERIES = f4
CMSIS_MCU = STM32F405xx
AF_FILE = boards/stm32f405_af.csv AF_FILE = boards/stm32f405_af.csv
LD_FILE = boards/stm32f405.ld LD_FILE = boards/stm32f405.ld

1
stmhal/boards/PYBV3/mpconfigboard.mk
View File

@ -1,3 +1,4 @@
MCU_SERIES = f4 MCU_SERIES = f4
CMSIS_MCU = STM32F405xx
AF_FILE = boards/stm32f405_af.csv AF_FILE = boards/stm32f405_af.csv
LD_FILE = boards/stm32f405.ld LD_FILE = boards/stm32f405.ld

1
stmhal/boards/PYBV4/mpconfigboard.mk
View File

@ -1,3 +1,4 @@
MCU_SERIES = f4 MCU_SERIES = f4
CMSIS_MCU = STM32F405xx
AF_FILE = boards/stm32f405_af.csv AF_FILE = boards/stm32f405_af.csv
LD_FILE = boards/stm32f405.ld LD_FILE = boards/stm32f405.ld

1
stmhal/boards/STM32F4DISC/mpconfigboard.mk
View File

@ -1,3 +1,4 @@
MCU_SERIES = f4 MCU_SERIES = f4
CMSIS_MCU = STM32F407xx
AF_FILE = boards/stm32f405_af.csv AF_FILE = boards/stm32f405_af.csv
LD_FILE = boards/stm32f405.ld LD_FILE = boards/stm32f405.ld

1
stmhal/boards/STM32F7DISC/mpconfigboard.mk
View File

@ -1,3 +1,4 @@
MCU_SERIES = f7 MCU_SERIES = f7
CMSIS_MCU = STM32F746xx
AF_FILE = boards/stm32f746_af.csv AF_FILE = boards/stm32f746_af.csv
LD_FILE = boards/stm32f746.ld LD_FILE = boards/stm32f746.ld

14
stmhal/make-stmconst.py
View File

@ -7,6 +7,8 @@ expected to change. After generating the file, some manual intervention is
needed to copy the new qstr definitions to qstrdefsport.h. needed to copy the new qstr definitions to qstrdefsport.h.
""" """
from __future__ import print_function
import argparse import argparse
import re import re
@ -34,7 +36,7 @@ class Lexer:
('typedef struct', re.compile(r'typedef struct$')), ('typedef struct', re.compile(r'typedef struct$')),
('{', re.compile(r'{$')), ('{', re.compile(r'{$')),
('}', re.compile(r'}$')), ('}', re.compile(r'}$')),
('} TypeDef', re.compile(r'} *(?P<id>[A-Z][A-Za-z0-9_]+)_(?P<global>(Global)?)TypeDef;$')), ('} TypeDef', re.compile(r'} *(?P<id>[A-Z][A-Za-z0-9_]+)_(?P<global>([A-Za-z0-9_]+)?)TypeDef;$')),
('IO reg', re.compile(re_io_reg + r'; +/\*!< ' + re_comment + r', +' + re_addr_offset + r' *\*/')), ('IO reg', re.compile(re_io_reg + r'; +/\*!< ' + re_comment + r', +' + re_addr_offset + r' *\*/')),
('IO reg array', re.compile(re_io_reg + r'\[(?P<array>[2-8])\]; +/\*!< ' + re_comment + r', +' + re_addr_offset + r'-(0x[0-9A-Z]{2,3}) *\*/')), ('IO reg array', re.compile(re_io_reg + r'\[(?P<array>[2-8])\]; +/\*!< ' + re_comment + r', +' + re_addr_offset + r'-(0x[0-9A-Z]{2,3}) *\*/')),
) )
@ -157,6 +159,8 @@ const mp_obj_module_t stm_%s_obj = {
def main(): def main():
cmd_parser = argparse.ArgumentParser(description='Extract ST constants from a C header file.') cmd_parser = argparse.ArgumentParser(description='Extract ST constants from a C header file.')
cmd_parser.add_argument('file', nargs=1, help='input file') cmd_parser.add_argument('file', nargs=1, help='input file')
cmd_parser.add_argument('-q', '--qstr', dest='qstr_filename', default='build/stmconst_qstr.h',
help='Specified the name of the generated qstr header file')
args = cmd_parser.parse_args() args = cmd_parser.parse_args()
periphs, reg_defs = parse_file(args.file[0]) periphs, reg_defs = parse_file(args.file[0])
@ -198,7 +202,8 @@ def main():
'WWDG', 'WWDG',
'RNG', 'RNG',
): ):
print_regs(reg, reg_defs[reg], needed_qstrs) if reg in reg_defs:
print_regs(reg, reg_defs[reg], needed_qstrs)
#print_regs_as_submodules(reg, reg_defs[reg], modules, needed_qstrs) #print_regs_as_submodules(reg, reg_defs[reg], modules, needed_qstrs)
#print("#define MOD_STM_CONST_MODULES \\") #print("#define MOD_STM_CONST_MODULES \\")
@ -207,8 +212,9 @@ def main():
print("") print("")
for qstr in sorted(needed_qstrs): with open(args.qstr_filename, 'wt') as qstr_file:
print('Q({})'.format(qstr)) for qstr in sorted(needed_qstrs):
print('Q({})'.format(qstr), file=qstr_file)
if __name__ == "__main__": if __name__ == "__main__":
main() main()

2
stmhal/modstm.c
View File

@ -120,7 +120,7 @@ STATIC const mp_map_elem_t stm_module_globals_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_mem16), (mp_obj_t)&stm_mem16_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_mem16), (mp_obj_t)&stm_mem16_obj },
{ MP_OBJ_NEW_QSTR(MP_QSTR_mem32), (mp_obj_t)&stm_mem32_obj }, { MP_OBJ_NEW_QSTR(MP_QSTR_mem32), (mp_obj_t)&stm_mem32_obj },
#include "modstmconst.gen.c" #include "genhdr/modstm_const.h"
}; };
STATIC MP_DEFINE_CONST_DICT(stm_module_globals, stm_module_globals_table); STATIC MP_DEFINE_CONST_DICT(stm_module_globals, stm_module_globals_table);

253
stmhal/modstmconst.gen.c
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@ -1,253 +0,0 @@
// Automatically generated from cmsis/devinc/stm32f405xx.h by make-stmconst.py
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM2), MP_OBJ_NEW_SMALL_INT(0x40000000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM3), MP_OBJ_NEW_SMALL_INT(0x40000400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM4), MP_OBJ_NEW_SMALL_INT(0x40000800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM5), MP_OBJ_NEW_SMALL_INT(0x40000c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM6), MP_OBJ_NEW_SMALL_INT(0x40001000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM7), MP_OBJ_NEW_SMALL_INT(0x40001400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM12), MP_OBJ_NEW_SMALL_INT(0x40001800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM13), MP_OBJ_NEW_SMALL_INT(0x40001c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM14), MP_OBJ_NEW_SMALL_INT(0x40002000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC), MP_OBJ_NEW_SMALL_INT(0x40002800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_WWDG), MP_OBJ_NEW_SMALL_INT(0x40002c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_IWDG), MP_OBJ_NEW_SMALL_INT(0x40003000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2S2EXT), MP_OBJ_NEW_SMALL_INT(0x40003400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI2), MP_OBJ_NEW_SMALL_INT(0x40003800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI3), MP_OBJ_NEW_SMALL_INT(0x40003c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2S3EXT), MP_OBJ_NEW_SMALL_INT(0x40004000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART2), MP_OBJ_NEW_SMALL_INT(0x40004400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART3), MP_OBJ_NEW_SMALL_INT(0x40004800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_UART4), MP_OBJ_NEW_SMALL_INT(0x40004c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_UART5), MP_OBJ_NEW_SMALL_INT(0x40005000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C1), MP_OBJ_NEW_SMALL_INT(0x40005400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C2), MP_OBJ_NEW_SMALL_INT(0x40005800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C3), MP_OBJ_NEW_SMALL_INT(0x40005c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN1), MP_OBJ_NEW_SMALL_INT(0x40006400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN2), MP_OBJ_NEW_SMALL_INT(0x40006800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_PWR), MP_OBJ_NEW_SMALL_INT(0x40007000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC), MP_OBJ_NEW_SMALL_INT(0x40007400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM1), MP_OBJ_NEW_SMALL_INT(0x40010000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM8), MP_OBJ_NEW_SMALL_INT(0x40010400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART1), MP_OBJ_NEW_SMALL_INT(0x40011000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART6), MP_OBJ_NEW_SMALL_INT(0x40011400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC), MP_OBJ_NEW_SMALL_INT(0x40012300) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC1), MP_OBJ_NEW_SMALL_INT(0x40012000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC2), MP_OBJ_NEW_SMALL_INT(0x40012100) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC3), MP_OBJ_NEW_SMALL_INT(0x40012200) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDIO), MP_OBJ_NEW_SMALL_INT(0x40012c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI1), MP_OBJ_NEW_SMALL_INT(0x40013000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SYSCFG), MP_OBJ_NEW_SMALL_INT(0x40013800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_EXTI), MP_OBJ_NEW_SMALL_INT(0x40013c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM9), MP_OBJ_NEW_SMALL_INT(0x40014000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM10), MP_OBJ_NEW_SMALL_INT(0x40014400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM11), MP_OBJ_NEW_SMALL_INT(0x40014800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOA), MP_OBJ_NEW_SMALL_INT(0x40020000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOB), MP_OBJ_NEW_SMALL_INT(0x40020400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOC), MP_OBJ_NEW_SMALL_INT(0x40020800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOD), MP_OBJ_NEW_SMALL_INT(0x40020c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOE), MP_OBJ_NEW_SMALL_INT(0x40021000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOF), MP_OBJ_NEW_SMALL_INT(0x40021400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOG), MP_OBJ_NEW_SMALL_INT(0x40021800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOH), MP_OBJ_NEW_SMALL_INT(0x40021c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIOI), MP_OBJ_NEW_SMALL_INT(0x40022000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CRC), MP_OBJ_NEW_SMALL_INT(0x40023000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC), MP_OBJ_NEW_SMALL_INT(0x40023800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH), MP_OBJ_NEW_SMALL_INT(0x40023c00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_DMA1), MP_OBJ_NEW_SMALL_INT(0x40026000) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_DMA2), MP_OBJ_NEW_SMALL_INT(0x40026400) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RNG), MP_OBJ_NEW_SMALL_INT(0x50060800) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_SR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, ADC status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_CR1), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, ADC control register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_CR2), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, ADC control register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_SMPR1), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, ADC sample time register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_SMPR2), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, ADC sample time register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JOFR1), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, ADC injected channel data offset register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JOFR2), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, ADC injected channel data offset register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JOFR3), MP_OBJ_NEW_SMALL_INT(0x1c) }, // 32-bits, ADC injected channel data offset register 3
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JOFR4), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, ADC injected channel data offset register 4
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_HTR), MP_OBJ_NEW_SMALL_INT(0x24) }, // 32-bits, ADC watchdog higher threshold register
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_LTR), MP_OBJ_NEW_SMALL_INT(0x28) }, // 32-bits, ADC watchdog lower threshold register
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_SQR1), MP_OBJ_NEW_SMALL_INT(0x2c) }, // 32-bits, ADC regular sequence register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_SQR2), MP_OBJ_NEW_SMALL_INT(0x30) }, // 32-bits, ADC regular sequence register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_SQR3), MP_OBJ_NEW_SMALL_INT(0x34) }, // 32-bits, ADC regular sequence register 3
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JSQR), MP_OBJ_NEW_SMALL_INT(0x38) }, // 32-bits, ADC injected sequence register
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JDR1), MP_OBJ_NEW_SMALL_INT(0x3c) }, // 32-bits, ADC injected data register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JDR2), MP_OBJ_NEW_SMALL_INT(0x40) }, // 32-bits, ADC injected data register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JDR3), MP_OBJ_NEW_SMALL_INT(0x44) }, // 32-bits, ADC injected data register 3
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_JDR4), MP_OBJ_NEW_SMALL_INT(0x48) }, // 32-bits, ADC injected data register 4
{ MP_OBJ_NEW_QSTR(MP_QSTR_ADC_DR), MP_OBJ_NEW_SMALL_INT(0x4c) }, // 32-bits, ADC regular data register
{ MP_OBJ_NEW_QSTR(MP_QSTR_CRC_DR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, CRC Data register
{ MP_OBJ_NEW_QSTR(MP_QSTR_CRC_IDR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 8-bits, CRC Independent data register
{ MP_OBJ_NEW_QSTR(MP_QSTR_CRC_CR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, CRC Control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_CR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, DAC control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_SWTRIGR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, DAC software trigger register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR12R1), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, DAC channel1 12-bit right-aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR12L1), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, DAC channel1 12-bit left aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR8R1), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, DAC channel1 8-bit right aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR12R2), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, DAC channel2 12-bit right aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR12L2), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, DAC channel2 12-bit left aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR8R2), MP_OBJ_NEW_SMALL_INT(0x1c) }, // 32-bits, DAC channel2 8-bit right-aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR12RD), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, Dual DAC 12-bit right-aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR12LD), MP_OBJ_NEW_SMALL_INT(0x24) }, // 32-bits, DUAL DAC 12-bit left aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DHR8RD), MP_OBJ_NEW_SMALL_INT(0x28) }, // 32-bits, DUAL DAC 8-bit right aligned data holding register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DOR1), MP_OBJ_NEW_SMALL_INT(0x2c) }, // 32-bits, DAC channel1 data output register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_DOR2), MP_OBJ_NEW_SMALL_INT(0x30) }, // 32-bits, DAC channel2 data output register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAC_SR), MP_OBJ_NEW_SMALL_INT(0x34) }, // 32-bits, DAC status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DBGMCU_IDCODE), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, MCU device ID code
{ MP_OBJ_NEW_QSTR(MP_QSTR_DBGMCU_CR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, Debug MCU configuration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DBGMCU_APB1FZ), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, Debug MCU APB1 freeze register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DBGMCU_APB2FZ), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, Debug MCU APB2 freeze register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DMA_LISR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, DMA low interrupt status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DMA_HISR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, DMA high interrupt status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DMA_LIFCR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, DMA low interrupt flag clear register
{ MP_OBJ_NEW_QSTR(MP_QSTR_DMA_HIFCR), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, DMA high interrupt flag clear register
{ MP_OBJ_NEW_QSTR(MP_QSTR_EXTI_IMR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, EXTI Interrupt mask register
{ MP_OBJ_NEW_QSTR(MP_QSTR_EXTI_EMR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, EXTI Event mask register
{ MP_OBJ_NEW_QSTR(MP_QSTR_EXTI_RTSR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, EXTI Rising trigger selection register
{ MP_OBJ_NEW_QSTR(MP_QSTR_EXTI_FTSR), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, EXTI Falling trigger selection register
{ MP_OBJ_NEW_QSTR(MP_QSTR_EXTI_SWIER), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, EXTI Software interrupt event register
{ MP_OBJ_NEW_QSTR(MP_QSTR_EXTI_PR), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, EXTI Pending register
{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_ACR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, FLASH access control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_KEYR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, FLASH key register
{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_OPTKEYR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, FLASH option key register
{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_SR), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, FLASH status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_CR), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, FLASH control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_OPTCR), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, FLASH option control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_OPTCR1), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, FLASH option control register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_MODER), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, GPIO port mode register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_OTYPER), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, GPIO port output type register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_OSPEEDR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, GPIO port output speed register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_PUPDR), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, GPIO port pull-up/pull-down register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_IDR), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, GPIO port input data register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_ODR), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, GPIO port output data register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_BSRRL), MP_OBJ_NEW_SMALL_INT(0x18) }, // 16-bits, GPIO port bit set/reset low register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_BSRRH), MP_OBJ_NEW_SMALL_INT(0x1a) }, // 16-bits, GPIO port bit set/reset high register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_LCKR), MP_OBJ_NEW_SMALL_INT(0x1c) }, // 32-bits, GPIO port configuration lock register
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_AFR0), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, GPIO alternate function registers
{ MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_AFR1), MP_OBJ_NEW_SMALL_INT(0x24) }, // 32-bits, GPIO alternate function registers
{ MP_OBJ_NEW_QSTR(MP_QSTR_SYSCFG_MEMRMP), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, SYSCFG memory remap register
{ MP_OBJ_NEW_QSTR(MP_QSTR_SYSCFG_PMC), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, SYSCFG peripheral mode configuration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_SYSCFG_EXTICR0), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, SYSCFG external interrupt configuration registers
{ MP_OBJ_NEW_QSTR(MP_QSTR_SYSCFG_EXTICR1), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, SYSCFG external interrupt configuration registers
{ MP_OBJ_NEW_QSTR(MP_QSTR_SYSCFG_EXTICR2), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, SYSCFG external interrupt configuration registers
{ MP_OBJ_NEW_QSTR(MP_QSTR_SYSCFG_EXTICR3), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, SYSCFG external interrupt configuration registers
{ MP_OBJ_NEW_QSTR(MP_QSTR_SYSCFG_CMPCR), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, SYSCFG Compensation cell control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_CR1), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, I2C Control register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_CR2), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, I2C Control register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_OAR1), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, I2C Own address register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_OAR2), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, I2C Own address register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_DR), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, I2C Data register
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_SR1), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, I2C Status register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_SR2), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, I2C Status register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_CCR), MP_OBJ_NEW_SMALL_INT(0x1c) }, // 32-bits, I2C Clock control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_TRISE), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, I2C TRISE register
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C_FLTR), MP_OBJ_NEW_SMALL_INT(0x24) }, // 32-bits, I2C FLTR register
{ MP_OBJ_NEW_QSTR(MP_QSTR_IWDG_KR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, IWDG Key register
{ MP_OBJ_NEW_QSTR(MP_QSTR_IWDG_PR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, IWDG Prescaler register
{ MP_OBJ_NEW_QSTR(MP_QSTR_IWDG_RLR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, IWDG Reload register
{ MP_OBJ_NEW_QSTR(MP_QSTR_IWDG_SR), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, IWDG Status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_PWR_CR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, PWR power control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_PWR_CSR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, PWR power control/status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_CR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, RCC clock control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_PLLCFGR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, RCC PLL configuration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_CFGR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, RCC clock configuration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_CIR), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, RCC clock interrupt register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB1RSTR), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, RCC AHB1 peripheral reset register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB2RSTR), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, RCC AHB2 peripheral reset register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB3RSTR), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, RCC AHB3 peripheral reset register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_APB1RSTR), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, RCC APB1 peripheral reset register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_APB2RSTR), MP_OBJ_NEW_SMALL_INT(0x24) }, // 32-bits, RCC APB2 peripheral reset register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB1ENR), MP_OBJ_NEW_SMALL_INT(0x30) }, // 32-bits, RCC AHB1 peripheral clock register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB2ENR), MP_OBJ_NEW_SMALL_INT(0x34) }, // 32-bits, RCC AHB2 peripheral clock register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB3ENR), MP_OBJ_NEW_SMALL_INT(0x38) }, // 32-bits, RCC AHB3 peripheral clock register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_APB1ENR), MP_OBJ_NEW_SMALL_INT(0x40) }, // 32-bits, RCC APB1 peripheral clock enable register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_APB2ENR), MP_OBJ_NEW_SMALL_INT(0x44) }, // 32-bits, RCC APB2 peripheral clock enable register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB1LPENR), MP_OBJ_NEW_SMALL_INT(0x50) }, // 32-bits, RCC AHB1 peripheral clock enable in low power mode register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB2LPENR), MP_OBJ_NEW_SMALL_INT(0x54) }, // 32-bits, RCC AHB2 peripheral clock enable in low power mode register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_AHB3LPENR), MP_OBJ_NEW_SMALL_INT(0x58) }, // 32-bits, RCC AHB3 peripheral clock enable in low power mode register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_APB1LPENR), MP_OBJ_NEW_SMALL_INT(0x60) }, // 32-bits, RCC APB1 peripheral clock enable in low power mode register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_APB2LPENR), MP_OBJ_NEW_SMALL_INT(0x64) }, // 32-bits, RCC APB2 peripheral clock enable in low power mode register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_BDCR), MP_OBJ_NEW_SMALL_INT(0x70) }, // 32-bits, RCC Backup domain control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_SSCGR), MP_OBJ_NEW_SMALL_INT(0x80) }, // 32-bits, RCC spread spectrum clock generation register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RCC_PLLI2SCFGR), MP_OBJ_NEW_SMALL_INT(0x84) }, // 32-bits, RCC PLLI2S configuration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_TR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, RTC time register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_DR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, RTC date register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_CR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, RTC control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_ISR), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, RTC initialization and status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_PRER), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, RTC prescaler register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_WUTR), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, RTC wakeup timer register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_CALIBR), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, RTC calibration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_ALRMAR), MP_OBJ_NEW_SMALL_INT(0x1c) }, // 32-bits, RTC alarm A register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_ALRMBR), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, RTC alarm B register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_WPR), MP_OBJ_NEW_SMALL_INT(0x24) }, // 32-bits, RTC write protection register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_SSR), MP_OBJ_NEW_SMALL_INT(0x28) }, // 32-bits, RTC sub second register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_SHIFTR), MP_OBJ_NEW_SMALL_INT(0x2c) }, // 32-bits, RTC shift control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_TSTR), MP_OBJ_NEW_SMALL_INT(0x30) }, // 32-bits, RTC time stamp time register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_TSDR), MP_OBJ_NEW_SMALL_INT(0x34) }, // 32-bits, RTC time stamp date register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_TSSSR), MP_OBJ_NEW_SMALL_INT(0x38) }, // 32-bits, RTC time-stamp sub second register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_CALR), MP_OBJ_NEW_SMALL_INT(0x3c) }, // 32-bits, RTC calibration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_TAFCR), MP_OBJ_NEW_SMALL_INT(0x40) }, // 32-bits, RTC tamper and alternate function configuration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP0R), MP_OBJ_NEW_SMALL_INT(0x50) }, // 32-bits, RTC backup register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP1R), MP_OBJ_NEW_SMALL_INT(0x54) }, // 32-bits, RTC backup register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP2R), MP_OBJ_NEW_SMALL_INT(0x58) }, // 32-bits, RTC backup register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP3R), MP_OBJ_NEW_SMALL_INT(0x5c) }, // 32-bits, RTC backup register 3
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP4R), MP_OBJ_NEW_SMALL_INT(0x60) }, // 32-bits, RTC backup register 4
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP5R), MP_OBJ_NEW_SMALL_INT(0x64) }, // 32-bits, RTC backup register 5
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP6R), MP_OBJ_NEW_SMALL_INT(0x68) }, // 32-bits, RTC backup register 6
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP7R), MP_OBJ_NEW_SMALL_INT(0x6c) }, // 32-bits, RTC backup register 7
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP8R), MP_OBJ_NEW_SMALL_INT(0x70) }, // 32-bits, RTC backup register 8
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP9R), MP_OBJ_NEW_SMALL_INT(0x74) }, // 32-bits, RTC backup register 9
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP10R), MP_OBJ_NEW_SMALL_INT(0x78) }, // 32-bits, RTC backup register 10
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP11R), MP_OBJ_NEW_SMALL_INT(0x7c) }, // 32-bits, RTC backup register 11
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP12R), MP_OBJ_NEW_SMALL_INT(0x80) }, // 32-bits, RTC backup register 12
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP13R), MP_OBJ_NEW_SMALL_INT(0x84) }, // 32-bits, RTC backup register 13
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP14R), MP_OBJ_NEW_SMALL_INT(0x88) }, // 32-bits, RTC backup register 14
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP15R), MP_OBJ_NEW_SMALL_INT(0x8c) }, // 32-bits, RTC backup register 15
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP16R), MP_OBJ_NEW_SMALL_INT(0x90) }, // 32-bits, RTC backup register 16
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP17R), MP_OBJ_NEW_SMALL_INT(0x94) }, // 32-bits, RTC backup register 17
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP18R), MP_OBJ_NEW_SMALL_INT(0x98) }, // 32-bits, RTC backup register 18
{ MP_OBJ_NEW_QSTR(MP_QSTR_RTC_BKP19R), MP_OBJ_NEW_SMALL_INT(0x9c) }, // 32-bits, RTC backup register 19
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_CR1), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, SPI control register 1 (not used in I2S mode)
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_CR2), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, SPI control register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_SR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, SPI status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_DR), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, SPI data register
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_CRCPR), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, SPI CRC polynomial register (not used in I2S mode)
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_RXCRCR), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, SPI RX CRC register (not used in I2S mode)
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_TXCRCR), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, SPI TX CRC register (not used in I2S mode)
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_I2SCFGR), MP_OBJ_NEW_SMALL_INT(0x1c) }, // 32-bits, SPI_I2S configuration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI_I2SPR), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, SPI_I2S prescaler register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CR1), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, TIM control register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CR2), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, TIM control register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_SMCR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, TIM slave mode control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_DIER), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, TIM DMA/interrupt enable register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_SR), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, TIM status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_EGR), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, TIM event generation register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CCMR1), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, TIM capture/compare mode register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CCMR2), MP_OBJ_NEW_SMALL_INT(0x1c) }, // 32-bits, TIM capture/compare mode register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CCER), MP_OBJ_NEW_SMALL_INT(0x20) }, // 32-bits, TIM capture/compare enable register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CNT), MP_OBJ_NEW_SMALL_INT(0x24) }, // 32-bits, TIM counter register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_PSC), MP_OBJ_NEW_SMALL_INT(0x28) }, // 32-bits, TIM prescaler
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_ARR), MP_OBJ_NEW_SMALL_INT(0x2c) }, // 32-bits, TIM auto-reload register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_RCR), MP_OBJ_NEW_SMALL_INT(0x30) }, // 32-bits, TIM repetition counter register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CCR1), MP_OBJ_NEW_SMALL_INT(0x34) }, // 32-bits, TIM capture/compare register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CCR2), MP_OBJ_NEW_SMALL_INT(0x38) }, // 32-bits, TIM capture/compare register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CCR3), MP_OBJ_NEW_SMALL_INT(0x3c) }, // 32-bits, TIM capture/compare register 3
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_CCR4), MP_OBJ_NEW_SMALL_INT(0x40) }, // 32-bits, TIM capture/compare register 4
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_BDTR), MP_OBJ_NEW_SMALL_INT(0x44) }, // 32-bits, TIM break and dead-time register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_DCR), MP_OBJ_NEW_SMALL_INT(0x48) }, // 32-bits, TIM DMA control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_DMAR), MP_OBJ_NEW_SMALL_INT(0x4c) }, // 32-bits, TIM DMA address for full transfer
{ MP_OBJ_NEW_QSTR(MP_QSTR_TIM_OR), MP_OBJ_NEW_SMALL_INT(0x50) }, // 32-bits, TIM option register
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART_SR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, USART Status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART_DR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, USART Data register
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART_BRR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, USART Baud rate register
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART_CR1), MP_OBJ_NEW_SMALL_INT(0xc) }, // 32-bits, USART Control register 1
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART_CR2), MP_OBJ_NEW_SMALL_INT(0x10) }, // 32-bits, USART Control register 2
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART_CR3), MP_OBJ_NEW_SMALL_INT(0x14) }, // 32-bits, USART Control register 3
{ MP_OBJ_NEW_QSTR(MP_QSTR_USART_GTPR), MP_OBJ_NEW_SMALL_INT(0x18) }, // 32-bits, USART Guard time and prescaler register
{ MP_OBJ_NEW_QSTR(MP_QSTR_WWDG_CR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, WWDG Control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_WWDG_CFR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, WWDG Configuration register
{ MP_OBJ_NEW_QSTR(MP_QSTR_WWDG_SR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, WWDG Status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RNG_CR), MP_OBJ_NEW_SMALL_INT(0x0) }, // 32-bits, RNG control register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RNG_SR), MP_OBJ_NEW_SMALL_INT(0x4) }, // 32-bits, RNG status register
{ MP_OBJ_NEW_QSTR(MP_QSTR_RNG_DR), MP_OBJ_NEW_SMALL_INT(0x8) }, // 32-bits, RNG data register

253
stmhal/qstrdefsport.h
View File

@ -474,256 +474,3 @@ Q(mem)
Q(mem8) Q(mem8)
Q(mem16) Q(mem16)
Q(mem32) Q(mem32)
// for stm constants
Q(ADC)
Q(ADC1)
Q(ADC2)
Q(ADC3)
Q(ADC_CR1)
Q(ADC_CR2)
Q(ADC_DR)
Q(ADC_HTR)
Q(ADC_JDR1)
Q(ADC_JDR2)
Q(ADC_JDR3)
Q(ADC_JDR4)
Q(ADC_JOFR1)
Q(ADC_JOFR2)
Q(ADC_JOFR3)
Q(ADC_JOFR4)
Q(ADC_JSQR)
Q(ADC_LTR)
Q(ADC_SMPR1)
Q(ADC_SMPR2)
Q(ADC_SQR1)
Q(ADC_SQR2)
Q(ADC_SQR3)
Q(ADC_SR)
Q(CAN1)
Q(CAN2)
Q(CRC)
Q(CRC_CR)
Q(CRC_DR)
Q(CRC_IDR)
Q(DAC)
Q(DAC_CR)
Q(DAC_DHR12L1)
Q(DAC_DHR12L2)
Q(DAC_DHR12LD)
Q(DAC_DHR12R1)
Q(DAC_DHR12R2)
Q(DAC_DHR12RD)
Q(DAC_DHR8R1)
Q(DAC_DHR8R2)
Q(DAC_DHR8RD)
Q(DAC_DOR1)
Q(DAC_DOR2)
Q(DAC_SR)
Q(DAC_SWTRIGR)
Q(DBGMCU_APB1FZ)
Q(DBGMCU_APB2FZ)
Q(DBGMCU_CR)
Q(DBGMCU_IDCODE)
Q(DMA1)
Q(DMA2)
Q(DMA_HIFCR)
Q(DMA_HISR)
Q(DMA_LIFCR)
Q(DMA_LISR)
Q(EXTI)
Q(EXTI_EMR)
Q(EXTI_FTSR)
Q(EXTI_IMR)
Q(EXTI_PR)
Q(EXTI_RTSR)
Q(EXTI_SWIER)
Q(FLASH)
Q(FLASH_ACR)
Q(FLASH_CR)
Q(FLASH_KEYR)
Q(FLASH_OPTCR)
Q(FLASH_OPTCR1)
Q(FLASH_OPTKEYR)
Q(FLASH_SR)
Q(GPIOA)
Q(GPIOB)
Q(GPIOC)
Q(GPIOD)
Q(GPIOE)
Q(GPIOF)
Q(GPIOG)
Q(GPIOH)
Q(GPIOI)
Q(GPIO_AFR0)
Q(GPIO_AFR1)
Q(GPIO_BSRRH)
Q(GPIO_BSRRL)
Q(GPIO_IDR)
Q(GPIO_LCKR)
Q(GPIO_MODER)
Q(GPIO_ODR)
Q(GPIO_OSPEEDR)
Q(GPIO_OTYPER)
Q(GPIO_PUPDR)
Q(I2C1)
Q(I2C2)
Q(I2C3)
Q(I2C_CCR)
Q(I2C_CR1)
Q(I2C_CR2)
Q(I2C_DR)
Q(I2C_FLTR)
Q(I2C_OAR1)
Q(I2C_OAR2)
Q(I2C_SR1)
Q(I2C_SR2)
Q(I2C_TRISE)
Q(I2S2EXT)
Q(I2S3EXT)
Q(IWDG)
Q(IWDG_KR)
Q(IWDG_PR)
Q(IWDG_RLR)
Q(IWDG_SR)
Q(PWR)
Q(PWR_CR)
Q(PWR_CSR)
Q(RCC)
Q(RCC_AHB1ENR)
Q(RCC_AHB1LPENR)
Q(RCC_AHB1RSTR)
Q(RCC_AHB2ENR)
Q(RCC_AHB2LPENR)
Q(RCC_AHB2RSTR)
Q(RCC_AHB3ENR)
Q(RCC_AHB3LPENR)
Q(RCC_AHB3RSTR)
Q(RCC_APB1ENR)
Q(RCC_APB1LPENR)
Q(RCC_APB1RSTR)
Q(RCC_APB2ENR)
Q(RCC_APB2LPENR)
Q(RCC_APB2RSTR)
Q(RCC_BDCR)
Q(RCC_CFGR)
Q(RCC_CIR)
Q(RCC_CR)
Q(RCC_PLLCFGR)
Q(RCC_PLLI2SCFGR)
Q(RCC_SSCGR)
Q(RNG)
Q(RNG_CR)
Q(RNG_DR)
Q(RNG_SR)
Q(RTC)
Q(RTC_ALRMAR)
Q(RTC_ALRMBR)
Q(RTC_BKP0R)
Q(RTC_BKP10R)
Q(RTC_BKP11R)
Q(RTC_BKP12R)
Q(RTC_BKP13R)
Q(RTC_BKP14R)
Q(RTC_BKP15R)
Q(RTC_BKP16R)
Q(RTC_BKP17R)
Q(RTC_BKP18R)
Q(RTC_BKP19R)
Q(RTC_BKP1R)
Q(RTC_BKP2R)
Q(RTC_BKP3R)
Q(RTC_BKP4R)
Q(RTC_BKP5R)
Q(RTC_BKP6R)
Q(RTC_BKP7R)
Q(RTC_BKP8R)
Q(RTC_BKP9R)
Q(RTC_CALIBR)
Q(RTC_CALR)
Q(RTC_CR)
Q(RTC_DR)
Q(RTC_ISR)
Q(RTC_PRER)
Q(RTC_SHIFTR)
Q(RTC_SSR)
Q(RTC_TAFCR)
Q(RTC_TR)
Q(RTC_TSDR)
Q(RTC_TSSSR)
Q(RTC_TSTR)
Q(RTC_WPR)
Q(RTC_WUTR)
Q(SDIO)
Q(SPI1)
Q(SPI2)
Q(SPI3)
Q(SPI_CR1)
Q(SPI_CR2)
Q(SPI_CRCPR)
Q(SPI_DR)
Q(SPI_I2SCFGR)
Q(SPI_I2SPR)
Q(SPI_RXCRCR)
Q(SPI_SR)
Q(SPI_TXCRCR)
Q(SYSCFG)
Q(SYSCFG_CMPCR)
Q(SYSCFG_EXTICR0)
Q(SYSCFG_EXTICR1)
Q(SYSCFG_EXTICR2)
Q(SYSCFG_EXTICR3)
Q(SYSCFG_MEMRMP)
Q(SYSCFG_PMC)
Q(TIM1)
Q(TIM10)
Q(TIM11)
Q(TIM12)
Q(TIM13)
Q(TIM14)
Q(TIM2)
Q(TIM3)
Q(TIM4)
Q(TIM5)
Q(TIM6)
Q(TIM7)
Q(TIM8)
Q(TIM9)
Q(TIM_ARR)
Q(TIM_BDTR)
Q(TIM_CCER)
Q(TIM_CCMR1)
Q(TIM_CCMR2)
Q(TIM_CCR1)
Q(TIM_CCR2)
Q(TIM_CCR3)
Q(TIM_CCR4)
Q(TIM_CNT)
Q(TIM_CR1)
Q(TIM_CR2)
Q(TIM_DCR)
Q(TIM_DIER)
Q(TIM_DMAR)
Q(TIM_EGR)
Q(TIM_OR)
Q(TIM_PSC)
Q(TIM_RCR)
Q(TIM_SMCR)
Q(TIM_SR)
Q(UART4)
Q(UART5)
Q(USART1)
Q(USART2)
Q(USART3)
Q(USART6)
Q(USART_BRR)
Q(USART_CR1)
Q(USART_CR2)
Q(USART_CR3)
Q(USART_DR)
Q(USART_GTPR)
Q(USART_SR)
Q(WWDG)
Q(WWDG_CFR)
Q(WWDG_CR)
Q(WWDG_SR)